CN109256361B - Selective back gold chip packaging structure and process method thereof - Google Patents
Selective back gold chip packaging structure and process method thereof Download PDFInfo
- Publication number
- CN109256361B CN109256361B CN201810868990.9A CN201810868990A CN109256361B CN 109256361 B CN109256361 B CN 109256361B CN 201810868990 A CN201810868990 A CN 201810868990A CN 109256361 B CN109256361 B CN 109256361B
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- Prior art keywords
- chip
- packaging
- laser
- welding pad
- gold
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910052737 gold Inorganic materials 0.000 title abstract description 14
- 239000010931 gold Substances 0.000 title abstract description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 title abstract description 5
- 238000003466 welding Methods 0.000 claims abstract description 25
- 239000011810 insulating material Substances 0.000 claims abstract description 13
- 239000005022 packaging material Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052709 silver Inorganic materials 0.000 claims abstract description 8
- 239000004332 silver Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000003292 glue Substances 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 238000006748 scratching Methods 0.000 claims description 2
- 230000002393 scratching effect Effects 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a selective back gold chip packaging structure and a process method thereof, wherein the packaging structure comprises a substrate (1), a chip (3) is arranged on the substrate (1) through silver paste (2), the chip (3) comprises an RF signal welding pad (31) and a grounding welding pad (32), a plastic packaging material (7) is packaged above the chip (3), a groove (5) is formed in an isolation area corresponding to the space between the RF signal welding pad (31) and the grounding welding pad (32) on the plastic packaging material (7), the groove (5) extends downwards to the surface of the substrate (1), and an insulating material (6) is filled in the groove (5). In the invention, under the condition that the chip is designed to be selective back-gold, the laser grooved channel is arranged on the surface of the chip, and the laser passes through the plastic packaging material layer and the chip layer after normal chip packaging and encapsulation and is filled with insulating materials to isolate and block the grounding welding pad and the signal welding pad, thereby solving the problem that the bridging or the signal welding pad can not be connected with the chip when the selective back-gold chip is packaged.
Description
Technical Field
The invention relates to a selective back gold chip packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging.
Background
Now some GaAs chips, in order to meet the electrical performance requirement, will design the chip into a selective back gold design, as shown in fig. 1, where the areas a and C are gold-plated areas, the area B is an isolation area, the gold-plated areas C on the left and right sides are signal pads, the middle bulk gold-plated area a is a ground pad, the signal pad must not bridge with any other gold-plated area, otherwise the performance will be affected by short circuit.
However, as the chip is made smaller and smaller, the distance between the signal pad and the ground pad is small, and the substrate design problem is solved, if the traditional dispensing process is used, not only is the bridging risk very large, but also the left and right signal pads may not be covered by the silver paste, which causes the problem that the connection with the chip cannot be realized.
Disclosure of Invention
The invention aims to solve the technical problem of providing a selective back-gold chip packaging structure and a process method thereof aiming at the prior art, wherein under the condition that a chip is designed to be selective back-gold, a laser grooved channel is arranged on the surface of the chip, and a laser passes through a plastic packaging material layer and a chip layer after normal chip packaging and encapsulation and is filled with an insulating material to isolate and block a grounding welding pad and a signal welding pad, so that the problem that the bridging or the signal welding pad cannot be connected with the chip in selective back-gold chip packaging is solved.
The technical scheme adopted by the invention for solving the problems is as follows: the utility model provides a selectivity back of body golden chip packaging structure, it includes the base plate, be provided with the chip through the silver glue on the base plate, the chip includes signal weld pad and ground weld pad, the encapsulation of chip top has the plastic envelope material, the groove has been seted up corresponding to the isolation region between signal weld pad and the ground weld pad on the plastic envelope material, the groove downwardly extending is to the base plate surface, pack insulating material in the groove.
The size of the groove of the plastic packaging material area is larger than that of the groove of the chip area.
A process method of a selective gold-backed chip package structure, the method comprising the steps of:
firstly, performing glue scratching operation on the back of a chip in a normal mode to ensure the coverage rate of silver glue on the back of the chip;
step two, normal operation chip mounting and routing are carried out until the packaging is finished;
thirdly, laser grooving, forming grooves on the surface of the plastic packaging material corresponding to the isolation areas between the chip grounding welding pads and the signal welding pads through laser after packaging, and enabling the laser to pass through the plastic packaging layer and the chip layer in sequence until the surface of the substrate;
filling insulating materials in the grooves to achieve the effect of blocking the grounding welding pads and the signal welding pads;
step five, curing the insulating material in the groove;
and step six, cutting and other subsequent processes to finish the packaging.
Preferably, in the third step, the range of the laser grooves of the plastic packaging material layer is larger than that of the laser grooves of the chip layer.
Compared with the prior art, the invention has the advantages that:
the invention relates to a selective back-gold chip packaging structure and a process method thereof, wherein a channel for laser grooving is arranged on the surface of a chip under the condition that the chip is designed to be selective back-gold, and a grounding welding pad and a signal welding pad are isolated and blocked in a mode of laser plastic packaging material and the chip and filling insulating material after normal chip packaging, so that the problem that the bridging or the signal welding pad cannot be connected with the chip when the selective back-gold chip is packaged is solved.
Drawings
Fig. 1 is a schematic structural diagram of a selective gold-backed chip.
Fig. 2 is a schematic diagram of a selective gold-backed chip package structure according to the present invention.
Fig. 3 to 6 are schematic diagrams illustrating the process flows of the process of the selective gold-backed chip package structure according to the present invention.
Wherein:
Groove 5
And (7) plastic packaging material.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
As shown in fig. 2, the selective back-gold chip package structure in this embodiment includes a substrate 1, a chip 3 is disposed on the substrate 1 through a silver paste 2, the chip 3 includes a signal pad 31 and a ground pad 32, a molding compound 7 is encapsulated above the chip 3, a trench 5 is disposed on the molding compound 7 in an isolation region corresponding to a space between the signal pad 31 and the ground pad 32, the trench 5 extends downward to a surface of the substrate 1, and an insulating material 6 is filled in the trench 5;
the size of the groove 5 in the plastic material 7 area is larger than that of the groove 5 in the chip 3 area.
The process method comprises the following steps:
step one, referring to fig. 3, performing a scribing operation on the back surface of the chip in a normal mode to ensure the coverage rate of the silver adhesive on the back surface of the chip;
step two, referring to fig. 4, normal operation of chip mounting and routing is performed until the packaging is completed;
step three, referring to fig. 5, performing laser grooving, forming a groove on the surface of the plastic packaging material corresponding to the position of an isolation area between a chip grounding welding pad and a signal welding pad through laser after packaging, and enabling the laser to sequentially pass through a plastic packaging layer and a chip layer until the surface of the substrate;
the laser range of the plastic packaging material layer is larger than that of the chip layer;
the chip is not provided with a circuit in the longitudinal area of the ditching groove;
step four, referring to fig. 6, the grooves are filled with insulating materials, so that the effect of blocking the grounding welding pads and the signal welding pads is achieved;
step five, curing the insulating material in the groove;
and step six, manufacturing processes after cutting and the like are carried out, and packaging is finished.
In addition to the above embodiments, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the scope of the claims of the present invention.
Claims (2)
1. A process method of a selective gold-backed chip packaging structure is characterized by comprising the following steps:
firstly, performing glue scratching operation on the back of a chip to ensure the coverage rate of silver glue on the back of the chip;
step two, operation mounting and routing are carried out until the packaging is finished;
thirdly, laser grooving, forming grooves on the surface of the plastic packaging material corresponding to the isolation areas between the chip grounding welding pads and the signal welding pads through laser after packaging, and enabling the laser to pass through the plastic packaging layer and the chip layer in sequence until the surface of the substrate;
filling insulating materials in the grooves to achieve the effect of blocking the grounding welding pads and the signal welding pads;
step five, curing the insulating material in the groove;
and step six, cutting to finish packaging.
2. The process of claim 1, wherein the process comprises: and in the third step, the laser range of the plastic packaging material layer is larger than that of the chip layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810868990.9A CN109256361B (en) | 2018-08-02 | 2018-08-02 | Selective back gold chip packaging structure and process method thereof |
| PCT/CN2018/124572 WO2020024547A1 (en) | 2018-08-02 | 2018-12-28 | Selective back-metallized chip package structure and process method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810868990.9A CN109256361B (en) | 2018-08-02 | 2018-08-02 | Selective back gold chip packaging structure and process method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109256361A CN109256361A (en) | 2019-01-22 |
| CN109256361B true CN109256361B (en) | 2020-06-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810868990.9A Active CN109256361B (en) | 2018-08-02 | 2018-08-02 | Selective back gold chip packaging structure and process method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109256361B (en) |
| WO (1) | WO2020024547A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560920A (en) * | 2004-02-19 | 2005-01-05 | 友达光电股份有限公司 | Carrier |
| CN102254933A (en) * | 2011-08-02 | 2011-11-23 | 上海先进半导体制造股份有限公司 | PN junction isolating structure and forming method thereof |
| CN107068825A (en) * | 2017-02-14 | 2017-08-18 | 盐城东紫光电科技有限公司 | A kind of high pressure flip LED chips structure and its manufacture method |
| JP2017220576A (en) * | 2016-06-08 | 2017-12-14 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060118947A1 (en) * | 2004-12-03 | 2006-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermal expansion compensating flip chip ball grid array package structure |
| CN101295650A (en) * | 2007-04-25 | 2008-10-29 | 矽品精密工业股份有限公司 | Semiconductor device and its manufacturing method |
| CN101355071A (en) * | 2007-07-24 | 2009-01-28 | 矽品精密工业股份有限公司 | Conductor holder type semiconductor package and making method thereof |
| CN101226915B (en) * | 2008-02-05 | 2010-09-29 | 日月光半导体（上海）股份有限公司 | Package substrate and manufacturing method thereof |
| US10115862B2 (en) * | 2011-12-27 | 2018-10-30 | eLux Inc. | Fluidic assembly top-contact LED disk |
| CN103682043A (en) * | 2013-11-28 | 2014-03-26 | 天津金玛光电有限公司 | Die bonding method for horizontal LED chips and LED light source manufactured by die bonding method |
| TW201624213A (en) * | 2014-12-19 | 2016-07-01 | 中華映管股份有限公司 | Touch display device and noise-shielding method of touch display device |
| CN106856220B (en) * | 2015-12-08 | 2020-03-06 | 上海芯元基半导体科技有限公司 | Flip LED device packaged in wafer level, and segmentation unit and manufacturing method thereof |
| CN108091753B (en) * | 2018-01-22 | 2023-08-25 | 扬州大学 | Light source element |
-
2018
- 2018-08-02 CN CN201810868990.9A patent/CN109256361B/en active Active
- 2018-12-28 WO PCT/CN2018/124572 patent/WO2020024547A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560920A (en) * | 2004-02-19 | 2005-01-05 | 友达光电股份有限公司 | Carrier |
| CN102254933A (en) * | 2011-08-02 | 2011-11-23 | 上海先进半导体制造股份有限公司 | PN junction isolating structure and forming method thereof |
| JP2017220576A (en) * | 2016-06-08 | 2017-12-14 | 三菱電機株式会社 | Semiconductor device |
| CN107068825A (en) * | 2017-02-14 | 2017-08-18 | 盐城东紫光电科技有限公司 | A kind of high pressure flip LED chips structure and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109256361A (en) | 2019-01-22 |
| WO2020024547A1 (en) | 2020-02-06 |
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