CN105895587A - Method for overcoming layering of substrate and die through bonding performance of DAF and low-roughness silicon wafer - Google Patents
Method for overcoming layering of substrate and die through bonding performance of DAF and low-roughness silicon wafer Download PDFInfo
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- CN105895587A CN105895587A CN201510015033.8A CN201510015033A CN105895587A CN 105895587 A CN105895587 A CN 105895587A CN 201510015033 A CN201510015033 A CN 201510015033A CN 105895587 A CN105895587 A CN 105895587A
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- Prior art keywords
- wafer
- chip
- daf
- sheet
- substrate
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a method for overcoming layering of a substrate and a die through bonding performance of a DAF and a low-roughness silicon wafer. The method adopts the die, a film layer, the substrate and an added layer, wherein the bottom surface of the added layer is covered with a new DAF which is bonded with the substrate in advance. The method is implemented in five steps, and the new DAF covering the back surface of the die is bonded with the substrate in advance, thereby effectively improving the layering without affecting electrical characteristics of products.
Description
Technical field
The invention belongs to integrated antenna package field, disclose DAF with low roughness silicon chip associativity to overcome substrate to divide with chip
Layer method.
Background technology
Currently, in integrated antenna package, high power capacity Multifunctional ultrathin integrated antenna package (IC) becomes main flow, ultra-thin integrated electricity
The internal packaged type that can use stacking chip wafer in road encapsulation (IC), these chip wafers (Die) generally ratio is relatively thin, by
In to the consideration combined between chip wafer and substrate, it is necessary to the glue-line of use, thus the thickness to glue-line, flatness, all
Even property requires high.And the film (DAF) typically now using the chip wafer back side to paste is combined with substrate, on wafer generally
Have different grades of single wafer to exist, in encapsulation process, the preferentially Grade A operation to wafer, other grade of wafer
Would generally store temporarily, wait subjob again, single wafer granule one-stop operation on the wafer also having is cannotd be used up, and it remains
Remaining also to wait lower subjob.
On the other hand, the characteristic of DAF film is in the condition specified, and such as fast setting under temperature and time, typical temperature is 100
More than degree, but also can produce under conditions of 25 degree of workshop of encapsulation and react slowly, the crystalline substance of subjob again is waited for these
Circle DAF film at the back side during depositing is affected by many external conditions such as temperature humidity, it may occur that slight solidification.
Due to the roughness of substrate surface solder mask, the DAF film that these qualities change is when being combined with substrate, it is impossible to by substrate
Matsurface fully absorb, have air and be encapsulated in the inside, and because the contact surface with substrate after slight solidification bonds and do not has
The most firmly be easy for produce separate condition (referring to figure two), serious situation be product after completing injection molding packaging, product
Surface is it is seen that bulge phenomenon, and this air heats when generally going through Reflow Soldering high temperature inside encapsulating expands, and bulge is entered
One step deteriorate by complete to chip wafer and substrate the distending even resin of molding and substrate also together with separate, connect crystalline substance during this
The metal filament of round core sheet and substrate can be torn, and product failure is scrapped；Less serious conditions is to reflux through encapsulation procedure
Postwelding ultrasonic scanning, it can be seen that slight layering, but after packaging is accomplished through transport, client deposits the nature moisture absorption, SMT
After Reflow Soldering and heavy industry Reflow Soldering, layering deteriorates, product failure；Slight situation is that encapsulation process is not layered, and ultrasonic scanning is just
Often, after client's SMT Reflow Soldering, there is slight layering, do not cause product failure, but the stability of end product and use the longevity
Life can be impacted.
Summary of the invention
In order to solve for waiting that the chip wafer of subjob again is affected by many external condition during depositing in prior art,
Upper slice, after plastic packaging, blue film is deteriorated with substrate associativity, is easily layered, the problem causing product failure, the present invention relates to purpose and be
By being provided with increase layer, increase layer another side and use new DAF film to be first combined with substrate, can change by increasing the selection of layer
It is apt to layering and don't affects product electrical characteristic.
The invention discloses DAF with low roughness silicon chip associativity to overcome substrate and chip layered approach, including chip wafer,
Glue-line and substrate, also include increasing layer, and described increase layer is the wafer vacation sheet that bottom surface covers new DAF film, its elder generation and substrate junction
Close, realize through the following steps:
Step one, preparation full wafer wafer vacation sheet, be thinned to desired thickness by reduction process by monoblock wafer vacation sheet, false at wafer
New DAF film is sticked at the back side of sheet, is cut with DAF film by monoblock wafer vacation sheet, be cut into crystalline substance together with wafer cutting technique
Round core sheet wafer of a size vacation sheet；
Step 2, wafer vacation sheet is fitted on substrate by die bond processing procedure, allows the new DAF glue-line at the wafer vacation sheet back side and base
Plate surface combines；
Step 3, product chip wafer granule is attached on the wafer vacation sheet that step 2 has been cut by die bond processing procedure, allows wafer core
DAF film and the silicon surface of low roughness on sheet combine；
Step 4, continuation finishing operations: bonding wire, plastic packaging；
Step 5, complete encapsulation after, according to the requirement of chip wafer application level, tens single IC of random choose do reliability
Experiment.
Limit ground further as the present invention, the base material of described chip wafer is silicon.
Limit ground further as the present invention, the uniform ground thickness difference of described DAF film is less than or equal to 5um.
Limit ground further as the present invention, described cutting technique is that the wafer vacation sheet of full wafer is cut into single square wafer vacation sheet
Granule.
Limit ground further as the present invention, described substrate surface is provided with solder mask, and its roughness is less than or equal to 10um.
Compared with prior art, the medicine have the advantages that product covers the wafer vacation sheet of new DAF film by adding the back side
First be combined with substrate so that it is be tightly combined with substrate, effectively improve layering and don't affect product electrical characteristic.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the method for packing of existing chip wafer.
Fig. 2 is the product schematic diagram after the encapsulation of existing chip wafer.
Fig. 3 be in the present invention DAF and low roughness silicon chip associativity to overcome the schematic flow sheet of substrate and chip layered approach.
Fig. 4 be in the present invention DAF and low roughness silicon chip associativity to overcome substrate and chip layered approach step one schematic diagram.
Fig. 5 be in the present invention DAF and low roughness silicon chip associativity to overcome substrate and chip layered approach step 2 schematic diagram.
Fig. 7 be in the present invention DAF and low roughness silicon chip associativity to overcome substrate and chip layered approach step 3 schematic diagram.
Fig. 8 be in the present invention DAF and low roughness silicon chip associativity to overcome the product signal after substrate and chip layered approach
Figure.
In figure: chip wafer 1, DAF film 2, wafer vacation sheet 3, new DAF film 5, then the chip wafer 4 of subjob, base
Plate 6, space 7.
Detailed description of the invention
The present invention will be further described below in conjunction with the accompanying drawings, it will be appreciated that specific embodiment described herein is only used for explaining
The present invention, is not intended to limit the present invention.
As depicted in figs. 1 and 2, in existing chip wafer packaging technology, mainly by die bond, bonding wire, plastic packaging, after its
Its packaging process, reliability demonstration realizes, and IC encapsulation company inevitably produces temporarily to deposit and waits subjob again
Chip wafer, owing to it is expensive, generally will not do and scrap process.
As shown in Fig. 3 to Fig. 7, the invention discloses DAF with low roughness silicon chip associativity to overcome substrate and chip layering side
Method, including chip wafer 1, glue-line 2 and substrate 6, also includes increasing layer, and described increase layer is that the bottom surface of wafer vacation sheet 3 covers
New DAF glue-line 2, its elder generation is combined with substrate 6, and it realizes through the following steps:
Step one, preparation monoblock wafer vacation sheet, be thinned to desired thickness by reduction process by monoblock wafer vacation sheet, false at wafer
New DAF film is sticked at the back side of sheet, is cut with DAF film by monoblock wafer vacation sheet, be cut into crystalline substance together with wafer cutting technique
Round core sheet wafer of a size vacation sheet；
Step 2, wafer vacation sheet is fitted on substrate by die bond processing procedure, allows the new DAF film at the wafer vacation sheet back side and base
Plate surface combines；
Step 3, product chip wafer will be attached on the wafer vacation sheet that step 2 has been cut by die bond processing procedure, allow wafer core
DAF film and the silicon surface of low roughness on sheet combine；
Step 4, continuation finishing operations: bonding wire, plastic packaging；
Step 5, complete encapsulation after, according to the requirement of chip wafer application level, random choose tens single is packaged
IC does failtests.
Further, the solder mask roughness of described integrated antenna package (IC) substrate used thereof is generally at about 10um, typically
Contact surface roughness the least DAF film is the biggest with the actual bonded area in this face, and the air between DAF film and substrate is the fewest,
Associativity is the best, and at substrate and product chip wafer (Die), described chip wafer is the chip wafer having posted DAF film,
Between chip wafer, increase by a bed roughness little, the material of the minute surface of approximate ideal, allow DAF film on product chip wafer with
Increase laminating closes, and increases layer another side and uses new DAF film to be combined with substrate again, if increased, layer selection is proper can be improved
It is layered and don't affects product electrical characteristic.
It addition, in the selection increasing layer, the base material of described chip wafer is silicon (Si), so arranges, the material of silicon used
It is not affect product electrical characteristic and select as far as possible the material of similar element；And use wafer vacation sheet (Dummy wafer), this crystalline substance
A kind of Silicon Wafer (mirror not laying circuit layer that the false sheet of circle i.e. integrated antenna package IC Packaging Industry are commonly used very much
Wafer), thinning board is commonly used to do process certification, and board is verified, reforms into the crystalline substance of single after full wafer wafer vacation sheet is cleaved
The false sheet granule (Dummy Die) of circle, is so arranged, and the wafer vacation sheet of the most single is for the assessment of packaging technology workability and board
Assessment.And monoblock wafer vacation sheet is cheap and is prone to thinning and polishing, roughness can control at below 0.1um, far
Roughness less than substrate solder mask.
As it is shown in fig. 7, owing to wafer vacation sheet surface roughness is relatively low, though with the chip wafer 4 and DAF film of subjob again
Associativity, also can be better than the combination with substrate.
As shown in Figure 8, owing to integrated antenna package size has its standard, it is substantially fixing, wafer core packaged inside
The thickness of sheet includes 2 points: 1. packaging body surface to the chip wafer surface distance being attached on substrate do not affect plastic packaging time resin horizontal
The mobility in direction, 2. needs bonding wire to go to connect the golden finger on substrate due to chip wafer surface, and line exceeds chip wafer table
The radian in face has certain span of control, it is ensured that IC plastic packaging carries surface and retains certain distance to bank peak, is unlikely to gold thread
Leak outside.By the packing forms of superposition, such as, plastic-sealed body height T1500um, chip wafer (D2) thickness 80, DAF is thick
Degree 20, then chip wafer surface is to plastic-sealed body surface distance C 400um, and bank controls exceeding chip wafer surface 110um,
Then bank peak carries surface distance 290um to plastic packaging does not affect packaging technology, increases layer D1 and selects one layer of 80um thickness
Wafer vacation sheet, pastes the thick DAF film of 20um below wafer vacation sheet, after superposition, upper strata chip wafer (D2) surface is to plastic-sealed body surface
Distance C is that 300um still meets packaging technology requirement, if increasing layer (D1) to select the wafer vacation sheet of 400um, then pastes
The DAF film of 20um, then gross thickness 520um after 2 layers of chip wafer superposition, will be beyond plastic-sealed body height, and this technique can not
Use.
The invention discloses DAF with low roughness silicon chip associativity to overcome substrate and chip layered approach, product is by adding the back of the body
Face covers new DAF film wafer vacation sheet and is first combined with substrate, effectively improves layering and don't affects product electrical characteristic.Need
It is noted that above-mentioned better embodiment is only technology design and the feature of the explanation present invention, its object is to allow and be familiar with this skill
The personage of art will appreciate that present disclosure and implements according to this, can not limit the scope of the invention with this.All according to this
Significant Change that spirit essence is made or modification, all should contain within protection scope of the present invention.
Claims (5)
1.DAF and low roughness silicon chip associativity overcome substrate and chip layered approach, including chip wafer, glue-line and substrate,
It is characterized in that: also include increasing layer, described increase layer is the wafer vacation sheet that bottom surface covers new DAF film, its elder generation and substrate junction
Close, realize through the following steps:
Step one, preparation monoblock wafer vacation sheet, be thinned to desired thickness by reduction process by monoblock wafer vacation sheet, false at wafer
New DAF film is sticked at the back side of sheet, is cut with DAF film by full wafer wafer vacation sheet, be cut into crystalline substance together with wafer cutting technique
Round core sheet wafer of a size vacation sheet granule；
Step 2, wafer vacation sheet granule is fitted on substrate by die bond processing procedure, allows the new DAF at the wafer vacation sheet granule back side
Film and substrate surface combine；
Step 3, product chip wafer granule is attached under step on completed wafer vacation sheet by die bond processing procedure, allows wafer
DAF film and the silicon surface of low roughness on chip combine；
Step 4, continuation finishing operations: bonding wire, plastic packaging；
Step 5, complete encapsulation after, according to the requirement of chip wafer application level, tens single IC of random choose do reliably
Property experiment.
DAF the most according to claim 1 and low roughness silicon chip associativity overcome substrate and chip layered approach, its
It is characterised by: the base material of described chip wafer is silicon.
DAF the most according to claim 1 and low roughness silicon chip associativity overcome substrate and chip layered approach, its
It is characterised by: the uniform ground thickness difference of described DAF film is less than or equal to 5um.
DAF the most according to claim 1 and low roughness silicon chip associativity overcome substrate and chip layered approach, its
It is characterised by: described cutting technique is that the wafer vacation sheet of full wafer is cut into single square wafer vacation sheet granule.
DAF the most according to claim 1 and low roughness silicon chip associativity overcome substrate and chip layered approach, its
Being characterised by: described substrate surface is provided with solder mask, its roughness is less than or equal to 10um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510015033.8A CN105895587A (en) | 2015-01-09 | 2015-01-09 | Method for overcoming layering of substrate and die through bonding performance of DAF and low-roughness silicon wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510015033.8A CN105895587A (en) | 2015-01-09 | 2015-01-09 | Method for overcoming layering of substrate and die through bonding performance of DAF and low-roughness silicon wafer |
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| CN105895587A true CN105895587A (en) | 2016-08-24 |
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| CN201510015033.8A Pending CN105895587A (en) | 2015-01-09 | 2015-01-09 | Method for overcoming layering of substrate and die through bonding performance of DAF and low-roughness silicon wafer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091605A (en) * | 2017-12-06 | 2018-05-29 | 英特尔产品（成都）有限公司 | A kind of method for reducing wafer and removing by mistake |
| WO2021185002A1 (en) * | 2020-03-19 | 2021-09-23 | 深圳纽迪瑞科技开发有限公司 | Preparation method for strain sensitive film, strain sensitive film, and pressure sensor |
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| CN101355071A (en) * | 2007-07-24 | 2009-01-28 | 矽品精密工业股份有限公司 | Conductor holder type semiconductor package and making method thereof |
| CN102184872A (en) * | 2011-04-08 | 2011-09-14 | 嘉盛半导体(苏州)有限公司 | Semiconductor packaging bonding process |
| US20140353850A1 (en) * | 2013-05-28 | 2014-12-04 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
-
2015
- 2015-01-09 CN CN201510015033.8A patent/CN105895587A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101355071A (en) * | 2007-07-24 | 2009-01-28 | 矽品精密工业股份有限公司 | Conductor holder type semiconductor package and making method thereof |
| CN102184872A (en) * | 2011-04-08 | 2011-09-14 | 嘉盛半导体(苏州)有限公司 | Semiconductor packaging bonding process |
| US20140353850A1 (en) * | 2013-05-28 | 2014-12-04 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and fabrication method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108091605A (en) * | 2017-12-06 | 2018-05-29 | 英特尔产品（成都）有限公司 | A kind of method for reducing wafer and removing by mistake |
| CN108091605B (en) * | 2017-12-06 | 2018-12-21 | 英特尔产品（成都）有限公司 | A method of it reducing wafer and accidentally removes |
| WO2021185002A1 (en) * | 2020-03-19 | 2021-09-23 | 深圳纽迪瑞科技开发有限公司 | Preparation method for strain sensitive film, strain sensitive film, and pressure sensor |
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Application publication date: 20160824 |
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