CN105789146A - Stacked die package structure - Google Patents
Stacked die package structure Download PDFInfo
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- CN105789146A CN105789146A CN201410789163.2A CN201410789163A CN105789146A CN 105789146 A CN105789146 A CN 105789146A CN 201410789163 A CN201410789163 A CN 201410789163A CN 105789146 A CN105789146 A CN 105789146A
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- packaging structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention provides a stacked die package structure, which comprises a substrate, a substrate die, a plurality of stacked dies and a binder layer, wherein the substrate die is arranged on the substrate; the plurality of stacked dies are successively stacked and arranged on the substrate die, and each stacked die is provided with a source surface and a back surface; the binder layer is arranged between the substrate die and the substrate and between the adjacent stacked dies; the back surface of each stacked die comprises one or a plurality of first surfaces and one or a plurality of second surfaces, wherein the one or the plurality of first surfaces are parallel to an active surface, a distance between the first surfaces and the active surface is H1, and the binder layer is arranged on the first surface; and the one or the plurality of second surfaces are parallel to the active surface, the distance between the second surfaces and the active surface is H2, and H1 is greater than H2. The back surface of each stacked die is provided with a first surface and a second surface, wherein the first surface and the second surface have different heights, a routing space is provided by the height difference of the first surface and the second surface during packaging, a gap layer arranged for polymer materials is omitted, and the problem of the thermal deformation or cracking of the die due to different coefficients of thermal expansion is avoided.
Description
Technical field
The application relates to technical field of manufacturing semiconductors, in particular to a kind of stack type chip packaging structure.
Background technology
Stacked chip packages (stackeddiepackage) structure is to utilize three-dimensional packaging technology by semiconductor package stacking for multiple Chip Verticals, can be used in the storage device such as memory module, memory card.
nullStack type chip packaging structure common at present is as shown in Figure 1，Generally comprise a substrate 100 '，Multiple chips 300 ' are to be arranged on substrate 100 ' in the way of being stacked with，And by an interlayer gap layer 200 ' interval between chip 300 ' and chip 300 '，Think that the wire 500 ' (bondingwires) that routing is formed provides enough height，On the conductive plate 400 ' that this wire is connected to be fixed on substrate 100 '，Owing to the existence of above-mentioned clearance layer makes bonding process be unlikely to because highly deficiency causes avalanche，This clearance layer 200 ' is generally adopted epoxy resin or other polymer as its material，But the material of clearance layer 200 ' is different from the material of chip 300 '，Both thermal coefficient of expansions (CTE) are different，It is easily caused and in combination with place, crack occurs or cause chip 300 ' thermal deformation；It is additionally, since chip 300 ' more and more thinner, bursts apart owing to thermal coefficient of expansion difference is likely to result in chip 300 '.
Summary of the invention
The application aims to provide a kind of stack type chip packaging structure, to solve the problem that in the middle of prior art, gap layer is easily caused chip deformation.
To achieve these goals, an aspect according to the application, it is provided that a kind of stack type chip packaging structure, including: substrate；Base chip, is arranged on substrate；Multiple stacked dies, stack gradually and are arranged on base chip, and stacked die has active surface and back surface；Adhesive layer, it is arranged between base chip with substrate and between adjacent stacked die, the back surface of each stacked die includes: one or more first surfaces, is parallel to active surface and the distance with active surface is H1, and adhesive layer is arranged on the first surface；One or more second surfaces, are parallel to active surface and are H2 with the distance of active surface, and H1 is more than H2.
Further, the active surface of above-mentioned base chip and the spacing of back surface are that H3, H2 are equal to H3.
Further, the quantity of above-mentioned stacked die is more than or equal to 1.
Further, above-mentioned second surface is one and arranges around first surface.
Further, the width of above-mentioned back surface is D1, and the ratio that the inward flange of second surface and outer peripheral distance are D2, D2 and D1 is 1/5～1/3.
Further, above-mentioned first surface is one.
Further, the binding agent in above-mentioned adhesive layer is epoxy resin or thermoplastic resin modified epoxy resin, and thermoplastic resin is Pioloform, polyvinyl acetal, nylon, Merlon or polysulfones.
Further, above-mentioned stack type chip packaging structure also includes: one or more conductive plates, conductive plate is arranged on substrate；A plurality of wire, each wire is electrically connected active surface and conductive plate by the mode that routing combines, and is arranged on the active surface relative with second surface with the node of active surface.
Further, above-mentioned stack type chip packaging structure also includes packing colloid, and packing colloid is arranged on substrate and wraps up base chip, stacked die, adhesive layer, conductive plate and wire.
Further, above-mentioned stack type chip packaging structure also includes soldered ball, soldered ball be arranged on substrate away from the surface of base chip.
The technical scheme of application the application, it is that highly different first surfaces and second surface and H1 are more than H2 by the back surface design of stacked die, thus the difference in height between first surface and second surface prominent on back surface can be utilized to provide routing space when encapsulation, the clearance layer that the polymeric material of prior art is arranged need not be utilized, avoid the chip thermal deformation owing to the thermal coefficient of expansion difference of different materials causes or the problem burst apart, and owing to eliminating the use of polymeric material, also reduce packaging cost, simplify encapsulation step.
Accompanying drawing explanation
The Figure of description constituting the part of the application is used for providing further understanding of the present application, and the schematic description and description of the application is used for explaining the application, is not intended that the improper restriction to the application.In the accompanying drawings:
Fig. 1 illustrates the cross-sectional view of stack type chip packaging structure common in prior art；
Fig. 2 illustrates the cross-sectional view of the stack type chip packaging structure of a kind of preferred implementation offer of the application；
Fig. 3 illustrates the cross-sectional view of a chip of stacked die in the stack type chip packaging structure shown in Fig. 2；
Fig. 4 illustrates the cross-sectional view of the stack type chip packaging structure that the application another kind preferred implementation provides；
Fig. 5 illustrates the cross-sectional view of the stack type chip packaging structure that another preferred implementation of the application provides；
Fig. 6 illustrates that the wafer rear completing manufacture of semiconductor carries out polishing is thinning, obtain thinning after the cross-sectional view of wafer；
Fig. 7 illustrates and adopts the blade that thickness is bigger that wafer rear shown in Fig. 6 is cut, the wafer cross-sectional view obtained；
Fig. 8 illustrates the cross-sectional view of the multiple individual chips adopting conventional cutter that the wafer shown in Fig. 7 is cut and to be formed；
Fig. 9 illustrates the cross-sectional view of the stacked structure that the mode being fixed on substrate by base chip and conductive plate and adopt routing to engage obtains after base chip and conductive plate being electrically connected；And
Figure 10 illustrates and is fixed on the base chip shown in Fig. 9 by the chip shown in first Fig. 8, and adopts the mode that routing combines to be connected with conductive plate by the superiors' chip, the cross-sectional view of the stacked structure obtained.
Detailed description of the invention
It it is noted that described further below is all exemplary, it is intended to provide further instruction to the application.Unless otherwise, all technology used herein and scientific terminology have the identical meanings being generally understood that with the application person of an ordinary skill in the technical field.
It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to the restricted root illustrative embodiments according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to include plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " including " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For the ease of describing, here can use space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for describing the spatial relation of a device or feature and other devices or feature as shown in the figure.It should be appreciated that space relative terms is intended to the different azimuth in use or operation comprised except the orientation that device is described in the drawings.Such as, " in other devices or structure lower section " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can include " in ... top " and " in ... lower section " two kinds of orientation.This device can also other different modes location (90-degree rotation or be in other orientation), and space used herein above described relatively make respective explanations.
Now, the illustrative embodiments according to the application it is more fully described with reference to the accompanying drawings.But, these illustrative embodiments can be implemented by multiple different form, and should not be construed to be limited solely to embodiments set forth herein.Should be understood that, these embodiments are provided so that disclosure herein is thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use identical accompanying drawing labelling to represent identical device, thus description of them will be omitted.
Introduce as background technology, the material that in the middle of existing stack type chip packaging structure, gap layer adopts is different from the thermal coefficient of expansion of the material of chip, cause that chip thermal deformation occurs or bursts apart, in order to solve as above problem, present applicant proposes a kind of stack type chip packaging structure, Fig. 2 illustrates the cross-sectional view of the stack type chip packaging structure that a kind of preferred implementation provides, this stack type chip packaging structure include substrate 100, base chip 300, multiple stacked die 400 and multiple adhesive layer 200,；Base chip 300 arranges on the substrate 100, and stacked die 400 stacks gradually and is arranged on base chip 300, and stacked die 400 has active surface 401 and back surface 402；Adhesive layer 200 is arranged between base chip 300 with substrate 100 and between adjacent stacked die 400, the back surface 402 of each stacked die 400 includes one or more first surface 421 and one or more second surface 422, first surface 421 is parallel to active surface 401 and the distance with active surface 401 is H1, and adhesive layer 200 is arranged on first surface 421；Second surface 422 is parallel to active surface 401 and is H2 with the distance of active surface 401, and H1 is more than H2.
There is the stack type chip packaging structure of said structure, the back surface 402 of stacked die 400 is designed as highly different first surfaces 421 and second surface 422, make H1 more than H2, the structure of this chip can referring to Fig. 3, thus the difference in height between first surface 421 and second surface 422 prominent on back surface 402 can be utilized to provide routing space when encapsulation, the clearance layer that the polymeric material of prior art is arranged need not be utilized, avoid and cause chip thermal deformation or the problem burst apart due to the thermal coefficient of expansion difference of different materials, and owing to eliminating the use of polymeric material, also reduce packaging cost, simplify encapsulation step.
What it should be clear to a person skilled in the art that is, the base chip of above-mentioned stack type chip packaging structure and stacked die can meet encapsulation requirement, in order to reduce stack type chip packaging structure to the full extent at three-dimensional thickness, the thickness of preferred above-mentioned base chip is the chip general thickness when encapsulation, namely the active surface of base chip and the spacing of back surface are general thickness during chip package, and at stacked die in the routing space basis that the difference in height utilizing first surface 421 and second surface 422 provides enough, control above-mentioned H2 equal to H3, namely general thickness when stacked die 400 has a chip package in the position of corresponding second surface 422.
The stack type chip packaging structure of the application can be applied at present conventional packaging technology, and the quantity of stacked die therein is more than or equal to 1, even if its quantity is relatively big without the chip thermal deformation existed owing to thermal coefficient of expansion difference causes or burst apart.
Pass through described above, those skilled in the art are it is clearly understood that the application utilizes first surface 421 different from the distance of active surface 401 with second surface 422 thus being provided as routing to provide space just, as long as the back surface 402 being so capable of above-mentioned purpose designs structure and is used equally to the application, the application is in order to simplify the preparation method of each chip in stacked die 400, it is preferable that above-mentioned second surface 422 is one and arranges around first surface 421；It is preferred that above-mentioned first surface 421 is one.And the active surface 401 of above-mentioned second surface 422 correspondence needs enough areas and provides the node of routing, custom requirements according to current routing node, the width of preferred back surface 402 is D1, and the ratio that the inward flange of second surface 422 and outer peripheral distance are D2, D2 and D1 is 1/5～1/3.
The Main Function of above-mentioned adhesive layer 200 is for base chip is fixed on the substrate 100, fixed by chip each in stacked die 400, therefore, the binding agent kind of adhesive layer 200 is not had particular/special requirement by the application, the binding agent of this area routine is used equally to the application, such as epoxy resin or thermoplastic resin modified epoxy resin, thermoplastic resin therein is Pioloform, polyvinyl acetal, nylon, Merlon or polysulfones.
In the application another preferred embodiment, above-mentioned stack type chip packaging structure also includes one or more conductive plate 500 and a plurality of wire 600, and as shown in Figure 4, conductive plate 500 is arranged on the substrate 100；Each wire 600 is electrically connected active surface 401 and conductive plate 500 by the mode that routing combines, and is arranged on the node of active surface 401 in the part relative with second surface 422 of active surface 401.Conductive plate 500 is set on the substrate 100, then wire 600 is utilized active surface 401 and conductive plate 500 to be electrically connected, wherein wire 600 is thought to adopt the weld pad arranged at active surface 401 with node such as those skilled in the art of active surface 401, the method to set up of this weld pad and and be all referred to prior art with the connected mode of stacked die 400 active structure, do not repeat them here.
After completing the stacking of stacked die 400 and being electrically connected, preferred above-mentioned stack type chip packaging structure adopts colloid encapsulation this stack encapsulation structure i.e. also to include packing colloid 700, as shown in Figure 4, this packing colloid 700 arranges on the substrate 100 and wraps up base chip 300, stacked die 400, adhesive layer 200, conductive plate 500 and wire 600.Utilizing packing colloid 700 to completely cut off pollution and the dampness in the external world, its concrete material adopted can be the encapsulating materials commonly used in the art such as epoxy resin.
In order to convenient, the stack type chip packaging structure of the application is carried out bond package with other encapsulating structures or electrical part, the application another preferred embodiment in, above-mentioned stack type chip packaging structure also includes soldered ball 800, as it is shown in figure 5, soldered ball 800 is arranged on the surface away from base chip 300 of substrate 100.
The application, in order to make those skilled in the art be easier to understand above-mentioned stack type chip packaging structure, will illustrate the manufacture method of the stack type chip packaging structure shown in above-mentioned Fig. 5 below.
First, the wafer rear completing manufacture of semiconductor (FAB) is carried out polishing thinning, obtain shown in Fig. 6 thinning after wafer, this bruting process is different from the polishing of prior art, differ primarily in that wafer is not directly thinned to predetermined thickness by the polishing thinning process of the application completely, but the back side is carried out smooth process.
Then, adopt the blade that thickness is bigger that wafer rear shown in Fig. 6 after polishing is cut, obtain the back side with protuberance shown in Fig. 7, the thickness of this blade is less than the width of the stacked die 400 finally formed, and the position of cutting extends to both sides centered by wafer Cutting Road, the difference of H1 and H2 in the depth size correspondence aforementioned structure of cutting, cutting width corresponds approximately to the twice of the difference of aforementioned D1 and D2.
Then, adopt conventional cutter that the wafer shown in Fig. 7 is cut, form multiple independent stacked die 400 as shown in Figure 8, the back surface 402 of the stacked die 400 formed has first surface 421 and second surface 422, stacked die 400 structure of corresponding aforementioned stack type chip packaging structure, then base chip 300 adopts common process mode to make.
After completing the wafer cutting each stacked die 400 of formation, stacked die 400 can be packaged, encapsulation process is referred to prior art, such as: perform step S1, first by fixing on the substrate 100 to base chip 300 and conductive plate 500, and adopt the mode that routing engages base chip 300 and conductive plate 500 to be electrically connected, obtain the stacked structure with cross-section structure shown in Fig. 9；Then, perform step S2, stacked die 400 shown in first Fig. 8 is fixed on the base chip 300 shown in Fig. 9, adopt this area conventional to fix in the way of the back of the body (facetoback), it is fixed on the active surface 401 of base chip by the back surface 402 of the stacked die 400 shown in Fig. 8, and first surface 421 avoids the node of base chip 300 and wire 600, obtain the stacked structure with cross-section structure shown in Figure 10, and adopt the mode that routing combines to be connected with conductive plate 500 by the superiors' stacked die 400 shown in Figure 10；Then, repeat the above steps, set gradually each stacked die 400 of stacked die；Adopt polymeric material that base chip 300, stacked die 400, conductive plate 500 and wire 600 are packaged after completing the procedure, the stacked structure with cross-section structure shown in Fig. 4 can be obtained；Further, at substrate 100, soldered ball 800 is set away from logical on the surface of base chip 300, such as adopt wire bonder to be melted by the heating one end of gold thread and form this soldered ball 800 to the surface of substrate 100, the stack type chip packaging structure with cross-section structure shown in Fig. 5 can be obtained.
As can be seen from the above description, the application the above embodiments achieve following technique effect:
1), it is that highly different first surfaces and second surface and H1 are more than H2 by the back surface design of chip, thus the difference in height between first surface and second surface prominent on back surface can be utilized to provide routing space when encapsulation, the clearance layer that the polymeric material of prior art is arranged need not be utilized, it is to avoid the chip thermal deformation caused due to the thermal coefficient of expansion difference of different materials or the problem burst apart；
, and owing to eliminating the use of polymeric material, also reduce packaging cost, simplify encapsulation step 2).
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.All within spirit herein and principle, any amendment of making, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (10)
1. a stack type chip packaging structure, including:
Substrate (100)；
Base chip (300), is arranged on described substrate (100)；
Multiple stacked dies (400), stack gradually and are arranged on described base chip (300), and described stacked die (400) has active surface (401) and back surface (402)；
Adhesive layer (200), is arranged between described base chip (300) with described substrate (100) and between adjacent described stacked die (400), it is characterised in that
The back surface (402) of each described stacked die includes:
One or more first surfaces (421), being parallel to described active surface (401) and the distance with described active surface (401) is H1, described adhesive layer (200) is arranged on described first surface (421)；
One or more second surfaces (422), are parallel to described active surface (401) and the distance with described active surface (401) is H2, and described H1 is more than described H2.
2. stack type chip packaging structure according to claim 1, it is characterised in that the active surface (401) of described base chip (300) and the spacing of back surface (402) are H3, described H2 is equal to described H3.
3. stack type chip packaging structure according to claim 1, it is characterised in that the quantity of described stacked die (400) is more than or equal to 1.
4. stack type chip packaging structure according to claim 1, it is characterised in that described second surface (422) is and arranges around described first surface (421).
5. stack type chip packaging structure according to claim 1, it is characterized in that, the width of described back surface (402) is D1, and the inward flange of described second surface (422) and outer peripheral distance are D2, and the ratio of described D2 and described D1 is 1/5～1/3.
6. stack type chip packaging structure according to claim 1, it is characterised in that described first surface (421) is.
7. stack type chip packaging structure according to claim 1, it is characterized in that, binding agent in described adhesive layer (200) is epoxy resin or thermoplastic resin modified epoxy resin, and described thermoplastic resin is Pioloform, polyvinyl acetal, nylon, Merlon or polysulfones.
8. stack type chip packaging structure according to claim 1, it is characterised in that described stack type chip packaging structure also includes:
One or more conductive plates (500), described conductive plate (500) is arranged on described substrate (100)；
A plurality of wire (600), each described wire (600) is electrically connected described active surface (401) and described conductive plate (500) by the mode that routing combines, and is arranged on the active surface (401) relative with described second surface (422) with the node of described active surface (401).
9. stack type chip packaging structure according to claim 8, it is characterized in that, described stack type chip packaging structure also includes packing colloid (700), and described packing colloid (700) is arranged on described substrate (100) and above and wraps up described base chip (300), described stacked die (400), described adhesive layer (200), described conductive plate (500) and described wire (600).
10. stack type chip packaging structure according to claim 8, it is characterized in that, described stack type chip packaging structure also includes soldered ball (800), and described soldered ball (800) is arranged on the surface away from described base chip (300) of described substrate (100).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410789163.2A CN105789146A (en) | 2014-12-16 | 2014-12-16 | Stacked die package structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410789163.2A CN105789146A (en) | 2014-12-16 | 2014-12-16 | Stacked die package structure |
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| CN105789146A true CN105789146A (en) | 2016-07-20 |
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| CN201410789163.2A Pending CN105789146A (en) | 2014-12-16 | 2014-12-16 | Stacked die package structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010898A (en) * | 2017-11-02 | 2018-05-08 | 上海玮舟微电子科技有限公司 | A kind of chip-packaging structure |
| CN109727913A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2461149Y (en) * | 2000-12-14 | 2001-11-21 | 胜开科技股份有限公司 | Stack integrated circuit |
| CN101136379A (en) * | 2006-08-29 | 2008-03-05 | 日月光半导体制造股份有限公司 | Chip packaging construct and manufacturing method thereof |
| CN101477955A (en) * | 2008-01-04 | 2009-07-08 | 南茂科技股份有限公司 | Encapsulation structure and method for tablet reconfiguration |
| CN101621041A (en) * | 2008-07-02 | 2010-01-06 | 南茂科技股份有限公司 | Packaging structure with reconfiguration chip and method thereof |
| CN103515333A (en) * | 2012-06-25 | 2014-01-15 | 南亚科技股份有限公司 | Semiconductor package structure |
-
2014
- 2014-12-16 CN CN201410789163.2A patent/CN105789146A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2461149Y (en) * | 2000-12-14 | 2001-11-21 | 胜开科技股份有限公司 | Stack integrated circuit |
| CN101136379A (en) * | 2006-08-29 | 2008-03-05 | 日月光半导体制造股份有限公司 | Chip packaging construct and manufacturing method thereof |
| CN101477955A (en) * | 2008-01-04 | 2009-07-08 | 南茂科技股份有限公司 | Encapsulation structure and method for tablet reconfiguration |
| CN101621041A (en) * | 2008-07-02 | 2010-01-06 | 南茂科技股份有限公司 | Packaging structure with reconfiguration chip and method thereof |
| CN103515333A (en) * | 2012-06-25 | 2014-01-15 | 南亚科技股份有限公司 | Semiconductor package structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727913A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN108010898A (en) * | 2017-11-02 | 2018-05-08 | 上海玮舟微电子科技有限公司 | A kind of chip-packaging structure |
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