JPH10335680A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a planer semiconductor device to be protected against partial damage which is liable to occur to the corner of a PN junction or its vicinity and enhanced in reverse recovery characteristics. SOLUTION: A semiconductor device is equipped with a first conductivity-type first semiconductor region 1 and a second conductivity-type second semiconductor region 2 which is formed on the one main surface of the first semiconductor region 1 to form a PN junction together with the first semiconductor region 1. In this case, a second conductivity carrier absorbing region 8 of high impurity concentration which absorbs minority carriers injected into the first semiconductor region 1 from the second semiconductor region 2 is provided in the prescribed spots on the peripheral edge of the same main surface of the first semiconductor region 1 where the second semiconductor region 2 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure capable of improving imbalance of partial reverse recovery in a semiconductor region.

[0002]

Basic semiconductor structure of the Related Art Generally, relatively high breakdown voltage planar-type semiconductor diodes for power, as shown in FIG. 8, lower N impurity concentration which is the semiconductor substrate ^- the first semiconductor region 1 and a second semiconductor region 2 of P ⁺ having a high impurity concentration which is formed on one main surface of the semiconductor substrate and forms a PN junction with the semiconductor region 1. The other main surface of the semiconductor substrate includes The N ⁺ semiconductor layer 1A having a high impurity concentration is formed for the purpose of forming an ohmic contact with the electrode 3 and for forming the minimum necessary first semiconductor layer.

Further, the other electrode 4 is formed in the second semiconductor region 2. Reference numeral 5 denotes an insulating film such as a silicon dioxide film or a nitride film, and reference numeral 6 denotes a guard ring region. Reference numeral 7 denotes a channel stopper region for limiting extension of the inversion layer due to expansion of the depletion layer at the time of reverse bias. The general operation of this semiconductor diode is well known and will not be described.

However, since a power planar type semiconductor diode having such a structure is required to have a relatively large breakdown voltage, the PN junction on the substrate surface where the PN junction exists is required.
The dimensions from joining to the periphery of the board must be large,
As a result, it has been confirmed that sometimes destruction occurs near the corner of the semiconductor region 2 serving as the anode. Y. Tomomatsu and six others clarified the cause.
A paper published in IEEE in 1996, `` An analysis and impro
vement of destruction immunityduring reverse recov
ery for high voltage planer diodes under highdIrr /
dt condition ”.

According to this document, it is reported that breakdown occurs in the case of a planar semiconductor diode during a reverse recovery period from a forward bias state to a reverse bias state even when the reverse surge voltage is lower than the quiescent breakdown voltage. doing. To solve this problem, the electric field at the corner of the anode region (reference numeral 2 in FIG. 8) is reduced or
Alternatively, it is described that the current density at the corner becomes extremely high, so that the current density may be reduced.

The inventor of the present invention has found that the cause of the extremely high reverse current density at the corner portion of the anode region is that the semiconductor region 2 serving as the anode is injected into the low impurity concentration semiconductor region 1 in the semiconductor region serving as the cathode. The accumulation of holes in the low-impurity-concentration semiconductor region 1, particularly away from the semiconductor region 2, is delayed, and the elimination thereof is delayed, and the reverse recovery time of that portion is longer than that of other portions. Become. In other words, the minority carriers accumulated in the corner portion at the time of reverse bias are extruded through the PN junction or recombine with a predetermined lifetime and disappear, and the recovery is delayed more than in the central portion. It is considered that as a result of an increase in power loss, destruction occurs at the corner of the PN junction and in the vicinity thereof.

[0007]

SUMMARY OF THE INVENTION Therefore, the present invention reduces the extent to which the reverse recovery in the first low-impurity-concentration semiconductor region 1 remote from the semiconductor region 2 is delayed as compared with other portions, or reduces or reduces the extent to almost zero. The challenge is to prevent reverse recovery imbalance from occurring.

In order to solve this problem, according to the present invention, a high impurity concentration semiconductor for absorbing minority carriers injected from a second conductivity type semiconductor region into a first conductivity type low impurity concentration semiconductor region is provided. By providing the carrier absorption region at a predetermined portion of the peripheral portion of the first conductive type low impurity concentration semiconductor region, the disappearance of minority carriers at the peripheral portion of the first conductive type low impurity concentration semiconductor region can be reduced. The feature is that they are almost the same.

[0009]

Means for Solving the Problems In order to solve the above-mentioned problems, the invention according to claim 1 comprises a first semiconductor region of a first conductivity type and one main surface of the first semiconductor region. PN is formed in a part of the first semiconductor region and
In a semiconductor device having a second semiconductor region of a second conductivity type opposite to the first conductivity type forming a junction, the same semiconductor device in which the second semiconductor region exists in the first semiconductor region is provided. A carrier of a second conductivity type having a high impurity concentration for absorbing minority carriers injected from the second semiconductor region of the second conductivity type into the first semiconductor region at a predetermined portion of a peripheral portion of the surface. A semiconductor device provided with an absorption region is provided.

In order to solve the above-mentioned problem, a second aspect of the present invention is directed to the first aspect, wherein a channel stopper region of a first conductivity type is formed in the first semiconductor region. A semiconductor device comprising a carrier absorption region of a conductivity type provided outside a channel stopper region of a first conductivity type.

In order to solve the above-mentioned problem, according to a third aspect of the present invention, in the second aspect, the carrier absorption region of the second conductivity type and the channel stopper region of the first conductivity type are short-circuited. A semiconductor device is provided.

In order to solve the above-mentioned problem, a fourth aspect of the present invention is characterized in that, in the second aspect, the carrier absorption region of the second conductivity type is connected to a main electrode connected to a stable potential. The semiconductor device described above is provided.

In order to solve the above-mentioned problem, the invention according to claim 5 is the invention according to claim 2 or claim 3, wherein the channel stopper region of the first conductivity type and the second
And a carrier absorption region of the conductivity type is connected to a main electrode connected to a stable potential.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The same symbols as those shown in FIG. 8 indicate the corresponding members. FIG.
FIG. 1A is a cross-sectional perspective view for explaining a semiconductor structure, and FIG. 1B is a partially enlarged view.

An embodiment of this planar type semiconductor diode is different from the conventional one in that N ^{− having} a low impurity concentration is used.
The point is that a high P ⁺ carrier absorption region 8 which is discontinuously formed so as to enter the N ⁺ channel stopper region 7 formed on the outer peripheral portion of the semiconductor region 1 from the outer peripheral side is provided. P
⁺ Carrier absorption region 8 is formed at the same time as P ⁺ semiconductor region 2 serving as an anode region and P ⁺ guard ring region 6 are formed by diffusing a P-type impurity from one main surface side of semiconductor region 1. You. Therefore, P ⁺ carrier absorption region 8 exists on the same main surface of semiconductor region 1 where semiconductor region 2 and guard ring region 6 exist.

Next, the operation of the P ⁺ carrier absorption region 8 will be described. Before describing the operation, the fact that holes injected from the P conductivity type semiconductor region 2 into the N ⁻ semiconductor region 1 are likely to accumulate is described. Give an explanation. The holes injected from the P ⁺ semiconductor region 2 to the N ⁻ semiconductor region 1 during the forward injection are converted into the N ⁺ channel stopper region 7 serving as a barrier for the holes and the N ⁺
Since it is surrounded by the semiconductor layer 1A, holes are likely to be accumulated particularly in corner portions.

Therefore, the holes injected from the P ⁺ semiconductor region 2 into the N ⁻ semiconductor region 1 at the time of the forward bias absorb or absorb the holes closer to the P ⁺ semiconductor region 2 at the time of the reverse bias. It is easy to disappear by recombination, but P ⁺
It is presumed that the holes existing in the N ⁻ semiconductor region 1 distant from the semiconductor region 2, particularly in the four corner portions farthest away and in the vicinity thereof, are unlikely to disappear.

For this reason, if the reverse current flowing near the corner of the P ⁺ semiconductor region 2 remains until the end, and the reverse current flows even if the value of the reverse voltage is considerably large,
In particular, it is presumed that the power loss at the PN junction formed by the semiconductor regions 1 and 2 and the vicinity thereof is larger than that at other portions, and partial destruction occurs when the power loss exceeds the breakdown strength. .

In the semiconductor structure of this embodiment, a P ⁺ carrier absorption region 8 is provided on the outer peripheral portion of the N ⁻ semiconductor region 1 farthest from the P ⁺ semiconductor region 2. Since the level of the barrier to holes is small, holes near the P ⁺ carrier absorption region 8 are easily absorbed by the region 8 and the accumulation of holes during forward bias can be reduced.
Therefore, the reverse current flowing in the vicinity of the corner of the P ⁺ semiconductor region 2 does not flow until later than in other portions, and the occurrence of the phenomenon that the corner of the anode region or the vicinity thereof is easily broken is greatly reduced. it can.

Next, another embodiment of the present invention will be described with reference to FIG. 2, the same symbols as those in FIG. 1 indicate the corresponding members. This semiconductor structure is substantially different from the embodiment of FIG. 1 in that a P ⁺ carrier absorption region 8 is provided outside the N ⁺ channel stopper region 7 and away from the N ⁺ channel stopper region 7 on the entire outer peripheral portion of the N ⁻ semiconductor region 1. is there. N
^{The +} channel stopper region 7 and the P ⁺ carrier absorption region 8 operate in exactly the same manner as described above, and absorb holes near the peripheral portion distant from the P ⁺ semiconductor region 2 to quickly disappear. Thus, without any part when a reverse bias voltage is applied a reverse current concentrates, most reverse current at the same time in each area of the PN junction and the vicinity thereof disappears, the P ⁺ semiconductor region 2 is the anode region of the diode Not only can partial destruction that tends to occur at or near a corner be prevented, but the reverse recovery time can be shortened and switching characteristics can be improved.

Next, another embodiment of the present invention will be described with reference to FIG. 3, the same symbols as those in FIG. 1 indicate the corresponding members. This example N diode ^- are characterized in that by short-circuiting the N ⁺ channel stopper region 7 is formed in the semiconductor region 1 and the P ⁺ carrier absorption regions 8 short-circuit electrode 9. In this structure, N ^-
The holes absorbed from the semiconductor region 1 into the P ⁺ carrier absorption region 8 are recombined with the electrons from the N ⁺ channel stopper region 7 via the short-circuit electrode 9 to be extinguished earlier. Therefore, the effect of absorbing holes in the P ⁺ carrier absorption region 8 is improved, and the reverse current does not concentrate on any portion when a reverse bias voltage is applied. Disappears, so that partial destruction, which tends to occur at or near the corner of the P ⁺ semiconductor region 2, which is the anode region of the diode, can be prevented.

Next, in another embodiment of the present invention shown in FIG. 4, a cathode electrode 11 in which the short-circuit electrode 9 is connected to a stable potential such as a ground potential by a bonding wire 10 in the embodiment shown in FIG. It is characterized by being connected to. With such a structure, the hole absorption effect of the P ⁺ carrier absorption region 8 is further improved, and a highly reliable diode that is not partially destroyed when a bias voltage is applied can be obtained. Note that the same symbols as those in FIG. 3 indicate corresponding members.

Next, an embodiment in which the present invention is applied to an NPN-type bipolar transistor will be described with reference to FIG. N ⁻ semiconductor region 1 and N ⁺ semiconductor region 1A form a collector region, P conductivity type semiconductor region 11 is a base region,
N ⁺ semiconductor regions 12 each constitute an emitter region. The feature of this NPN bipolar transistor is that a P ⁺ carrier absorption region 8 is provided in the N ⁻ semiconductor region 1 of the collector region along the outer periphery of the region 1 outside the N ⁺ channel stopper region 7.

By providing P ⁺ carrier absorption region 8, of the holes injected from base region 11 into N ⁻ semiconductor region 1, holes existing relatively close to P ⁺ carrier absorption region 8 are P ^Since it is absorbed by the carrier absorption region 8, it is possible to prevent partial destruction that tends to occur at or near the corner of the P-conductivity type semiconductor region 11, which is the base region. Here, C denotes a collector electrode formed in the N ⁺ semiconductor region 1A, B denotes a base electrode formed in the P conductivity type semiconductor region 11, and E denotes an emitter electrode formed in the N ⁺ semiconductor region 12. The short-circuit electrode 9 for short-circuiting the N ⁺ channel stopper region 7 and the P ⁺ carrier absorption region 8 is not always necessary.

FIG. 6 shows an embodiment of the P-gate thyristor, in which the P ⁺ carrier extends along the outer periphery of the semiconductor region 1 outside the N ⁺ channel stopper region 7 in the N ⁻ semiconductor region 1 serving as the N base region. The feature is that the absorption region 8 is provided. Since the function and effect of the P ⁺ carrier absorption region 8 are the same as those described above, the description is omitted.
Reference numeral 13 denotes an anode region on which an anode electrode A is formed. 11 'is a P base region, on which a gate electrode G is formed. Reference numeral 12 'denotes a cathode region on which a cathode electrode K is formed.

Next, FIG. 7 shows an embodiment in which the present invention is applied to an IGBT. In the N ⁻ semiconductor region 1 serving as a base region, outside the N ⁺ channel stopper region 7 described above,
A feature is that a P ⁺ carrier absorption region 8 is provided along the outer periphery of the region 1. Since the function and effect of the P ⁺ carrier absorption region 8 are the same as those described above, the description is omitted.

In the above embodiment, the case where the N-conductivity type semiconductor substrate is used has been described. However, the same effect can be obtained when the P-conductivity type semiconductor substrate is used. The N conductivity type semiconductor region of the in each case Example with change in a semiconductor region of the P conductivity type, change the semiconductor region of the P conductivity type semiconductor region of N conductivity type, P ^- outer peripheral portion of the semiconductor region By absorbing electrons in the vicinity of the N ⁺ carrier absorption region formed as described above, the same effect as described above can be obtained. Although all the embodiments described above have described a semiconductor device for electric power, particularly for a high withstand voltage, the present invention can be similarly applied to a device having a relatively low withstand voltage without a guard ring region and a channel stopper region, Similar effects can be obtained.

[0028]

As described above, according to the present invention, P
By providing the ⁺ carrier absorption region or the N ⁺ carrier absorption region along the four corners or the peripheral portion of the N ^- semiconductor region or the P ^- semiconductor region, it tends to occur at the corner of the PN junction and in the vicinity thereof when a reverse bias is applied. It is possible to prevent the concentration of the reverse current, or the partial destruction due to the reverse current flowing until late compared to other portions.

Further, since the reverse recovery characteristic can be improved, a power semiconductor diode suitable for high-frequency operation can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a first embodiment of a diode according to the present invention.

FIG. 2 is a diagram for explaining a second embodiment of the diode according to the present invention.

FIG. 3 is a diagram for explaining a third embodiment of the diode according to the present invention.

FIG. 4 is a diagram for explaining a fourth embodiment of the diode according to the present invention.

FIG. 5 is a diagram for explaining an embodiment of a bipolar transistor according to the present invention.

FIG. 6 is a diagram for explaining an embodiment of a thyristor according to the present invention.

FIG. 7 is a diagram for explaining an embodiment of the IGBT according to the present invention.

FIG. 8 is a diagram illustrating a conventional planar semiconductor diode.

[Explanation of symbols]

1. Semiconductor region of first conductivity type, 2. Semiconductor region of second conductivity type, 3, 4, electrode, 5, insulating film 6, guard ring region, 7, channel stopper region 8 ..Carrier absorption area 9-.Short-circuit electrodes

Claims (5)

[Claims] 1. A PN junction is formed between a first semiconductor region of a first conductivity type and a portion of one main surface of the first semiconductor region to form a PN junction between the first semiconductor region and the first semiconductor region. A semiconductor device having a second semiconductor region of a second conductivity type opposite to the first conductivity type, wherein a peripheral portion of the same main surface in the first semiconductor region where the second semiconductor region exists At a predetermined location, a high-impurity-concentration second-conductivity-type carrier-absorbing region for absorbing minority carriers injected from the second-conductivity-type second semiconductor region into the first semiconductor region is provided. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein a channel stopper region of a first conductivity type is formed in the first semiconductor region, and a carrier absorption region of a second conductivity type is formed in the first semiconductor region. A semiconductor device provided outside a channel stopper region. 3. The semiconductor device according to claim 2, wherein the carrier absorption region of the second conductivity type and the channel stopper region of the first conductivity type are short-circuited. 4. The semiconductor device according to claim 2, wherein the carrier absorption region of the second conductivity type is connected to a main electrode connected to a stable potential. 5. The semiconductor device according to claim 2, wherein the channel stopper region of the first conductivity type and the carrier absorption region of the second conductivity type are connected to a main electrode connected to a stable potential. A semiconductor device characterized by the above-mentioned.