JPH03286545A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent insulation failure from being introduced to a market and enable product quality to be improved by allowing an insulation region to be independent from an internal element in a semiconductor device with the insulation region and by providing an opening at one part for achieving electrical connection with an outside. CONSTITUTION:A peripheral insulation region 12 consists of a p<+> buried boron 3 and a p<+> insulation boron 5 for isolating an internal element from an insulation region for checking insulation isolation region 11. With the isolation region for checking insulation isolation region 11, a field oxide film 8 is etched and opening is provided using the photolithography for achieving electrical contact from outside and a pad 9 is formed simultaneously with wiring. Insulation isolation is judged by short-circuiting or open-circuiting by measuring I-V characteristic between the pad 9 and a p-type semiconductor substrate 1. Also, when the size of the pad 9 is set to approximately 120mum where a needle of a probe card contacts, it is possible to check insulation isolation for each chip at an electrical test process of the wafer since a p-type semiconductor substrate 1 is a bonding pad which corresponds to at least a power supply terminal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

The conventional insulation isolation check is as shown in Fig. 3. After base PR, a probe is applied to adjacent n epitaxial layers 4 through adjacent base PR openings 7 formed in oxidized [6], and the curve is ■-V characteristics were measured with a tracer to check whether there was insulation separation between the p+ buried boron 3 and the P+ insulating boron 5. In the figure, 1 is a P-type semiconductor substrate, 2 is an n-type semiconductor substrate, and 2 is an n-type semiconductor substrate. Contains antimony. Also, to check the isolation on the wafer after the diffusion process is completed, the third
Since it is necessary to create a state similar to that shown in the figure, in order to eliminate the influence of other elements connected to the epitaxial layer 4, the wiring was cut and checked using the method described above.

[Problem to be solved by the invention]

With this conventional semiconductor device, when analyzing defects in wafers after diffusion or products after assembly, it is not possible to measure directly adjacent epitaxial regions, so it is very time-consuming to check whether they are isolated. It takes.

Also, check the insulation isolation during the manufacturing process using the base PR.
Since a sample of several chips per lot is checked, and individual chips cannot be measured in the wafer aerometric testing process, there is a problem in that products without insulation separation are released onto the market.

An object of the present invention is to provide a semiconductor device that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having an insulating region, the insulating region being independent from an internal element, and having an opening in at least one location to connect to the outside. It is possible to electrically connect with.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(Example 1) FIG. 1(a) is a vertical cross-sectional view showing Example 1 of the present invention, and
FIG. 1(b) is a sectional view taken along the line AA' in FIG. 1(a).

In the figure, 1 is a ρ type semiconductor substrate, 3 is a ρ1 buried poron, 4 is an n-epitaxial layer, 5 is a ρ'' insulating boron, 8 is a field oxide film, 9 is a pad, and 10 is a passivation film. The region 12 is composed of ρ" embedded boron 3 and p+ insulating boron 5 to isolate the internal elements and the insulation region 11 for insulation separation check, and the insulation region 11 for insulation separation check can be electrically contacted from the outside. Using photolithography technology, the field oxide film 8 is
A hole is provided by etching, and a pad 9 is formed at the same time as wiring. IN! The possibility of edge separation is determined by measuring the r-v characteristics between the pad 9 and the p-type semiconductor substrate l, and determining whether there is a short circuit or an oven. In addition, if the size of the pad 9 is set to about 120 μm, which the needle of the probe card hits, the p-type semiconductor substrate 1 normally serves as a bonding pad corresponding to the lowest power supply terminal, so the chip can be used in the electrical testing process of the wafer. You can check the insulation isolation every time.

(Example 2) FIG. 2 is a sectional view showing a second embodiment of the present invention.

In this embodiment, the insulation region for insulation separation check consists of an insulation region 13 for insulation separation check in the X direction and an insulation region 14 for insulation separation check in the Y direction.

Insulation defects such as misalignment can be detected in both the Y direction. At this time, the short side of the p+ buried boron and ρ" insulating boron in the insulating region 13 for the X-direction insulation isolation check and the insulating region 14 for the Y-direction insulation check has the minimum dimension of the internal pattern of the p+ buried boron 10 μm, ρ “Insulating boron 8μ
Similarly, if m is 10 μm for p′ buried boron and 8 μm for p+ insulating boron.

〔Effect of the invention〕

As explained above, in the present invention, the openings are provided in the insulating area so that they can be electrically connected to the outside, so it is very easy to determine whether or not the insulation has been isolated even after the diffusion process is completed on the wafer. Furthermore, since the quality of insulation separation can be determined for each chip in the electrical testing process of the wafer, defective insulation will not be leaked to the market, and the quality of the product will be improved.

[Brief explanation of drawings]

FIG. 1(a) is a vertical cross-sectional view showing Embodiment 1 of the present invention.
FIG. 1B is a cross-sectional view taken along the line A-A' in FIG. 1A, FIG. 2 is a cross-sectional view showing a second embodiment of the present invention, and FIG. 3 is a cross-sectional view showing a conventional example. 1...p-type semiconductor substrate 2...n+buried antimony 3...ρ"buried boron 4...n epitaxial 5...p" insulating poron 6...oxide film 7...base PR opening portion 8...Field oxide film 9...Pad 10...Passivation film 11...Insulating region for insulation isolation check 12...Surrounding insulating region

Claims (1)

[Claims] (1) A semiconductor device having an insulating region, where the insulating region is independent from internal elements and has an opening in at least one location to enable electrical connection with the outside. Characteristic semiconductor devices.