JPH0262947B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a test method for semiconductor devices that enables simultaneous measurement of multiple semiconductor devices in a wafer state (hereinafter referred to as parallel wafer test).

[Prior art]

A conventional parallel wafer test is shown in FIG.

FIG. 1a is a plan view of the wafer 1, and FIG. 1b is a partially enlarged sectional view taken along line A--A in FIG. 1a.

In FIG. 1, 1 is a wafer, 2 is a P-type substrate,
3 is an N-type diffusion layer, 4 is a silicon oxide film, 5 is an aluminum wiring layer, and 6a, 6b, 6c (hereinafter collectively referred to as 6. The same applies to other symbols) is the first integrated circuit. fixed probes for measuring the elements; 7a, 7b, 7c are fixed probes for measuring the second integrated circuit element; 8a, 8b, 8c are fixed probes for measuring the third integrated circuit element;
9a, 9b, and 9c are fixed probes for measuring the fourth integrated circuit element. FIG. 1b shows the principle structure of each of the measurement fixed probes 6 to 9 and the wafer 1.
shows only three pins each. In an actual integrated circuit element, the integrated circuit element is constructed by combining multiple layers such as the N-type diffusion layer 3, silicon oxide film 4, and aluminum wiring layer 5 shown in FIG. 1B.

Next, the test operation will be explained.

Generally, when measuring one integrated circuit element, the fixed measuring probe only comes into contact with it alone, but the
As shown in FIG. b, when measuring four integrated circuit elements, the fixed measuring probes 6 to 9 come into contact with each other at the same time.

In FIG. 1, the integrated circuit element is Parallel wafer testing is performed. Therefore, during parallel wafer testing, the fixed probe 6a for measurement of the first integrated circuit element is connected to the aluminum wiring layer 5.
When the P-type substrate 2 is electrically connected to the P-type substrate 2 via the
The wafer 1 being measured by each fixed measurement probe 7 to 9 changes depending on the voltage applied to the wafer 1.
In some cases, the measurement of the integrated circuit element in the peripheral portion of the chip may not be performed properly.

Conventional parallel wafer testing is performed using the method described above, which has the drawback that integrated circuit elements near the wafer periphery that should be judged as ``good'' may be mistakenly judged as ``defective.'' be.

[Summary of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method, and it covers the surface of abnormal integrated circuit elements around the wafer with an insulating film so that parallel wafer tests can be performed around the wafer. The test was carried out after the test was completed. Hereinafter, this invention will be explained with reference to the drawings.

[Embodiments of the invention]

FIG. 2 shows an embodiment of the present invention, FIG. 2a is a plan view of a wafer 11 of the present invention, and FIG.
FIG. 2 is a partially enlarged view taken along line BB of

In FIGS. 2a and 2b, 11 indicates a wafer, and 12 indicates a glass coat film.

As shown in FIGS. 2a and 2b, by covering the surface of the abnormal integrated circuit element around the wafer 11 with the glass coating film 12, the fixed probe 6a for measurement of the first integrated circuit element is connected to the aluminum wiring layer 5. Electrically insulated. Therefore, the voltage applied to the fixed measurement probe 6a during the parallel wafer test has less influence on the P-type substrate 2, so that the parallel wafer test around the wafer 11 can be performed normally.

Furthermore, covering the surface of abnormal integrated circuit elements around the wafer 11 with the glass coat film 12 can be easily done by changing the glass coat etching mask.

In the above embodiment, the glass coat film 12 was used, but an electrical insulator such as a nitride coat film may be used.

Further, the P type substrate 2 and the N type diffusion layer 3 may be an N type substrate and a P type diffusion layer.

〔Effect of the invention〕

As explained above, the present invention electrically insulates the abnormal integrated circuit elements around the wafer from the probe during parallel wafer testing by covering the surface of the abnormal integrated circuit elements around the wafer with an insulating film. Loss of integrated circuit elements due to erroneous measurements during peripheral parallel wafer testing can be eliminated. Further, by performing a parallel wafer test, there is an advantage that the test cost can be lower than when measuring one integrated circuit element.

[Brief explanation of drawings]

Figures 1a and 1b are block diagrams of a conventional parallel wafer test. 1 is a block diagram of a parallel wafer test according to an embodiment of the present invention; FIG. 1A is a plan view of the wafer of the present invention, and FIG. In the figure, 2 is a P-type substrate, 3 is an N-type diffusion layer, 4 is a silicon oxide film, 5 is an aluminum wiring layer, 6 (6
a, 6b, 6c) are fixed probes for measuring the first integrated circuit element, 7 (7a, 7b, 7c) are fixed probes for measuring the second integrated circuit element, 8
(8a, 8b, 8c) are fixed probes for measuring the third integrated circuit element; 9 (9a, 9b, 9c);
1 is a fixed probe for measuring the fourth integrated circuit element, 11 is a wafer, and 12 is a glass coating film. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a method for testing a semiconductor device in which a large number of integrated circuit elements are simultaneously tested in a wafer state using probes in contact with each of them, after covering the surface of the abnormal integrated circuit element around the wafer with an insulating film,
A method for testing a semiconductor device, characterized by performing a test.