JPH08340028A - Testing method of semiconductor element - Google Patents

Abstract

PURPOSE: To make electric connection with a semiconductor element sure in a high temperature thermostatic chamber, without using a ceramic package, by overlapping a first wafer carrying first pads corresponding to semiconductor elements and a second wafer carrying second pads, and connecting the first pads with the second pads. CONSTITUTION: A wafer 3 for wiring carries the following: pads 23, pads 24 for outer connection which are formed in the vicinity of an orientation flat, and leading-out wirings 25 which connect the pads 23 with the pads 24 for outer connection. The pads 23 of the wafer 3 for wiring are formed so as to correspond to pads 1 of all semiconductor elements on a sample wafer 2. A bump 4 is formed on the pad 1 of the sample wafer 2. The wafer 3 formed in this manner is so overlapped on the sample wafer 2 that the orientation flats coincide with each other, and the wafers are compression-bonded. Thereby the semiconductor elements of the sample wafer 2 are electrically connected with the pad 24s for outer connection, via the pads 1, the bumps 4, the pads 23 and the leading-out wirings 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device testing method.

[0002]

2. Description of the Related Art In the case of semiconductor elements such as ICs, reliability such as TDDB (Time Dependent Dielectric Breakdown) evaluation for examining the dielectric breakdown voltage of an oxide film used for the semiconductor element and EM (Electro Migration) evaluation of metal wiring It is necessary to perform an evaluation test. These evaluation tests are usually carried out by applying a current or voltage for a long time of about 1 month to 2 months in a state in which the sample semiconductor element is stored in a constant temperature bath at about 200 ° C. Therefore, these evaluation tests are not performed in a wafer state, but are performed after the wafer is diced and incorporated into a ceramic package or the like.

[0003]

However, since these evaluation tests use expensive ceramic packages,
There is a problem in that the cost increases for evaluating a large number of semiconductor elements.

In order to carry out these evaluation tests in a wafer state before dicing in a short time, 20 semiconductor devices are used.
It is necessary to store in a constant temperature bath at about 0 ° C for evaluation.
In this case, since the probe card, which has a probe needle for probing on the printed circuit board and is used for electrical connection with the semiconductor element, does not have heat resistance, an evaluation test is performed in a constant temperature bath at about 200 ° C. I could hardly do that. Even if the evaluation can be performed at a temperature of 200 ° C., the probe needle is displaced due to the stress generated due to the difference in the coefficient of thermal expansion between the wafer and the printed circuit board, and the semiconductor element is not aligned with the semiconductor element. The electric connection was sometimes lost.

Further, in this case, since the probe card is used, it is difficult to make electrical connection with all the semiconductor elements formed on the wafer, and a large number of semiconductor elements cannot be evaluated simultaneously. It was

Therefore, an object of the present invention is to reliably make electrical connection with a semiconductor element even in a constant temperature bath at about 200 ° C. without using an expensive ceramic package, and to evaluate the TDDB of the semiconductor element. It is an object of the present invention to provide a semiconductor element test method capable of simultaneously evaluating a large amount of EM evaluation.

[0007]

In order to achieve the above object, a semiconductor element testing method according to the present invention is a semiconductor element testing method for a semiconductor element formed on a first wafer. The first wafer on which the pad is formed and the second wafer on which the second pad is formed are overlapped to connect the first pad and the second pad to each other. The semiconductor device is tested by inputting an electric signal from the outside to the pad.

In one aspect of the present invention, a conductive member is interposed between the first pad and the second pad.

In one aspect of the present invention, an electric signal is externally input to the second pad through a lead wire formed from the second pad to the peripheral portion of the second wafer.

[0010]

The semiconductor device can be tested in a wafer state without dicing the wafer, so that it can be performed without using an expensive ceramic package.
In addition, unlike a conventional probe card, since a printed circuit board is not used, stress caused by a difference in coefficient of thermal expansion does not occur even in a constant temperature bath at about 200 ° C., and a reliable electric connection with a semiconductor element is made. TD of semiconductor device
It becomes possible to simultaneously perform a large amount of DB evaluation and EM evaluation.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on an embodiment with reference to the drawings.

FIG. 1A is a schematic view of a sample wafer 2 on which pads 1 of a plurality of semiconductor elements are formed.
(B) is a schematic view of a wiring wafer 3 on which metal wirings and the like described later are formed. 2 is a sectional view showing a manufacturing process for forming the wiring wafer 3 as shown in FIG.

First, the step of forming metal wiring or the like on the wiring wafer 3 will be described. First, FIG. 2 (a)
As shown in FIG. 5, the metal wiring film 22 is formed on the wiring wafer 3 in the same process as that for forming the metal wiring necessary for forming a semiconductor element. The metal wiring film 22 may be formed by any method such as a vapor deposition method or a CVD method. The film thickness is also not particularly limited, but is preferably 1 μm or more in consideration of the resistance value of the wiring formed later.

Next, as shown in FIG. 2B, the metal wiring film 22 is patterned by selective etching, so that the pad 23 and the vicinity of the orientation flat are formed on the wiring wafer 3. The external connection pad 24 formed on the substrate and the lead wire 25 connecting the pad 23 and the external connection pad 24 are formed (FIG. 1).
(B)). This patterning is performed so that the pad 23 and the pad 1 face each other when the wiring wafer 3 and the sample wafer 2 are bonded together by aligning the orientation flats.
That is, the pad 23 and the pad 1 are patterned so as to have a mirror image relationship.

The pads 23 of the wiring wafer 3 are the pads 1 of all semiconductor elements on the sample wafer 2.
May be formed so as to correspond to, or may be formed so as to correspond to the pad 1 of any semiconductor element.

On the other hand, as shown in FIG. 4, bumps 4 made of lead or the like are formed on the pads 1 of the sample wafer 2. The bump 4 is located between the pad 23 and the pad 1 when the wiring wafer 3 and the sample wafer 2 are bonded to each other, and is necessary for electrical connection. The method of forming the bumps 4 is not particularly limited, and any method can be used as long as the bumps 4 can be formed on the pads 1. The bumps 4 may be formed at a height that allows the bumps 4 to be above the uppermost layer film of the semiconductor element.

The external connection pad 24 of the wiring wafer 3 does not come into contact with the sample wafer 2 at a portion of the edge of the sample wafer 2 in the orientation flat direction when the wiring wafer 3 and the sample wafer 2 are bonded together. Dicing and cutting.

The wiring wafer 3 and the sample wafer 2 thus formed are bonded together by aligning the orientation flats and pressure-bonded to each other, so that the semiconductor element of the sample wafer 2 passes through the pad 1, the bump 4, the pad 23 and the lead wiring 25. Electrically connected to the external connection pad 24. Therefore, the external connection pad 24 can be used to establish an electrical connection between the semiconductor element and the outside.

In this embodiment, as described above, by applying an electric signal to the external connection pad 24, an EM evaluation test or a TDDB evaluation test of the semiconductor element of the sample wafer 2 is performed in a wafer state without dicing the wafer. Therefore, it is not necessary to use an expensive ceramic package as in the past. Further, unlike the conventional probe card, since the wiring wafer 3 is used without using a printed circuit board, a stress caused by a difference in coefficient of thermal expansion does not occur even in a constant temperature bath at about 200 ° C. It is possible to establish electrical connection with the semiconductor element, and it is possible to simultaneously perform a large amount of TDDB evaluation and EM evaluation of the semiconductor element.

[0020]

As described above, according to the present invention,
20 without using expensive ceramic package
It is possible to simultaneously perform a large amount of TDDB evaluation and EM evaluation of semiconductor elements even in a constant temperature bath at about 0 ° C.

[Brief description of drawings]

FIG. 1 is a diagram showing a sample wafer 2 and a wiring wafer 3 used in an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the wiring wafer 3 of FIG.

FIG. 3 is a diagram showing a state in which bumps 4 are formed on the sample wafer 2 of FIG.

[Explanation of symbols]

 1 pad (first pad) 2 sample wafer (first wafer) 3 wiring wafer (second wafer) 4 bump 23 pad (second pad) 24 external connection pad 25 lead-out wiring

Claims (3)

[Claims] 1. A method of testing a semiconductor element formed on a first wafer, comprising: a first wafer having a first pad corresponding to the semiconductor element; and a second pad having a second pad formed thereon. The semiconductor device is tested by stacking two wafers to connect the first pad and the second pad and inputting an electric signal from the outside to the second pad. Testing method for semiconductor devices. 2. The method of testing a semiconductor device according to claim 1, wherein a conductive member is interposed between the first pad and the second pad. 3. An electric signal is externally input to the second pad through a lead wiring formed from the second pad to a peripheral portion of the second wafer. Alternatively, the semiconductor element testing method according to the item 2.