JP2002252260A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a wiring pattern utilizable for evaluating connection reliability of various types of semiconductor devices. SOLUTION: A semiconductor device formed in a square core pattern 10 includes electrode pads 11, 12 of the core pattern 10, wiring 13, 14 for connecting between the electrode pads 11, 12 lead-out electrodes 15, 16 led out from the electrode pads 11, 12, and a wiring pattern where faces provided with electrodes 11, 12, 15, 16 are laminated each other, and the electrodes 11, 12 and the wiring 13, 14 on the one face and the electrodes 11, 12 and the wiring 13, 14 on other face are connected through one path, and is constructed to be capable of connecting from the lead-out electrodes 15, 16 to the outside. Thereby, an evaluation chip and a substrate chip are made of the same mask pattern and the connection reliability can be evaluated. Moreover, the connection reliability also can be evaluated for a semiconductor of different sizes by changing a cut-size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device used for evaluating connection reliability between electrodes and a method for evaluating a semiconductor device.

[0002]

2. Description of the Related Art A chip mounted on a semiconductor device is:
The electrodes between the chips are connected by wire bonds, and exchange data with each other. However, if the chips are connected by wire bonds in this way, in recent years, with the increase in the capacity of transmission data of equipment and the increase in frequency due to high speed, data transmission during wire bonding between distant chips In some cases, data may be lost due to delays in the data and normal functions may not be realized.

Accordingly, a package having a chip-on-chip structure in which respective electrodes between chips are connected via bumps made of gold or the like is being developed. The chip-on-chip structure has a structure in which another chip is mounted on a chip mounted on a substrate, and the electrodes between these chips are connected via bumps. Since the distance between chips can be shortened compared to the conventional method where they are arranged side by side and connected by wire bonds, it is possible to respond to high speed data transmission,
Attention has been paid to a method capable of suppressing a delay in transmitting high-frequency data. Further, in the case of the chip-on-chip structure, the mounting area on the substrate can be reduced, and it is possible to cope with future high integration of a semiconductor device.

In a chip used in a semiconductor device having a chip-on-chip structure, it is important to evaluate the connection reliability between its electrodes in order to confirm the reliability as a package. In the current connectivity reliability test, two types of evaluation chip to be evaluated and a substrate chip to which the evaluation chip is connected are prepared, and the evaluation chip and the substrate chip are connected via bumps. A method is employed in which an electrode is pulled out to the outside and connected to a test device, and evaluation is performed while confirming the connection between the evaluation chip and the substrate chip.

[0005]

The evaluation chip and the substrate chip are chips formed on a wafer, and the evaluation chip is made smaller than the substrate chip so that wiring can be drawn out from the substrate chip.

FIG. 7 is a schematic diagram showing a state in which the evaluation chip and the substrate chip are connected. FIG. 7 shows only a portion where four portions are connected among the connection portions between the evaluation chip and the substrate chip.

The evaluation chip 100 includes an electrode pad 100
a, 100b, 100c, and 100d, and between each of the electrode pads, a wiring 101 is provided between 100a and 100b.
Thus, the wiring 100 connects between 100c and 100d.

On the other hand, the mating substrate chip 200 has electrode pads 200a, 200b, 200c, 200d and lead electrode pads 200e, 200f of the electrode pads 200a, 200d.
Is attached to the substrate chip 200, the evaluation chip 1
The electrode pads of the substrate chip 200 are formed at positions opposite to the electrode pads of No. 00, and have a pattern in which the electrode pads not connected to the evaluation chip are connected by wiring. That is, the wiring 201 is provided between 200b and 200c.
It is connected by.

The evaluation chip 100 and the substrate chip 2
00 is connected via a bump. Evaluation chip 100
The electrodes are drawn out from the substrate chip 200 on which the is mounted, connected to external leads, and connected to the test apparatus 300. Thereby, for example, the current flowing out of the test apparatus 300 is changed from the extraction electrode pad 200 e to the electrode pad 2.
00a, 100a, 100b, 200b, 200c, 1
A structure in which the evaluation chip 100 and the substrate chip 200 are connected by one path, in which the evaluation chip 100 returns to the test device 300 from the extraction electrode pad 200f through the order of 00c, 100d, and 200d, is formed, and the connection reliability is evaluated.

However, in the connection reliability evaluation by the above-described method, the evaluation chip and the substrate chip have different wiring patterns, and it is necessary to make each of them with a different wiring pattern, so that the mask material is required twice. Furthermore, when performing an evaluation with a different chip size, a chip of a corresponding size must be newly cut out from each wafer having a different wiring pattern by dicing. Therefore, there is a problem that the evaluation of the connection reliability between the electrodes of the semiconductor element requires cost and labor.

The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor element having a wiring pattern that can be used for evaluating the connection reliability of various types of semiconductor elements.

Still another object of the present invention is to provide a semiconductor device evaluation method for evaluating conduction between semiconductor devices.

[0013]

According to the present invention, in a semiconductor device having a square core pattern, an electrode pad, wiring for electrically connecting between the electrode pads, and a lead electrode pad drawn from the electrode pad. A core pattern having a core pattern and another core pattern, and a wiring pattern in which the electrode pad and the wiring are electrically connected to the other electrode pad and the other wiring by one path. There is provided a semiconductor device characterized by the following.

According to the above configuration, when the wiring pattern is bonded to the core pattern and another core pattern,
The wiring connecting the electrode pads of the core pattern and the wiring connecting the electrode pads of the other core pattern are formed so as to be electrically connected in one path. Furthermore, since the extraction electrode pad is extracted from the electrode pad, an external current can be input from the extraction electrode pad and output from another extraction electrode pad through one path including the electrode pad and the wiring. . As a result, an evaluation chip and a substrate chip are cut out from a wafer made of a core pattern having the same wiring pattern, produced, bonded, and connected to evaluate the connection reliability of the semiconductor element in a chip-on-chip structure. Therefore, the evaluation chip and the substrate chip can be manufactured from the same mask pattern.

Further, it is possible to cope with the evaluation of connection reliability of semiconductor elements having different sizes only by changing the size of the cut out from the wafer.

[0016]

Embodiments of the present invention will be described below in detail. The core pattern forming the evaluation chip and the substrate chip is formed by first forming an insulating film on a wafer, forming wiring on the wafer with aluminum or the like, then forming an insulating film on the wafer, and then forming an electrode pad. It is formed by opening a part of the window. Normal 1mm x 1
A core pattern of mm is formed on the entire wafer, cut into a target chip size by dicing, and used for evaluation of connection reliability.

FIG. 1 is a schematic diagram of a core pattern. The core pattern 10 is a square having a side of 1 mm, in which an electrode pad and a wiring are formed inside each of the sides 10a, 10b, 10c, and 10d, and an electrode formed near the side 10a. Pad 11 and side 10 opposite side 10a
b and the electrode pad 12 formed in the vicinity of
A wiring 13 connecting the (2n-1) th and 2nth from the side 10c of the first electrode 10;
a wiring 14 connecting the n-th and 2n + 1-th wirings and a wiring 1
3 is composed of an extraction electrode pad 15 extended to the vicinity of the electrode pad 12, and an extraction electrode pad 16 extended to the vicinity of the electrode pad 11 from the wiring 14.

Further, the electrode pad 11 and the electrode pad 12 are formed such that the n-th electrode pad from the side of the side 10c is located at the same distance from the side 10c,
0b.

A method of connecting the evaluation chip having the core pattern and the substrate chip having the above configuration will be described below. FIGS. 2A and 2B are diagrams in which a core pattern formed on a wafer is cut into a chip size. FIG. 2A shows a substrate chip, and FIG. 2B shows an evaluation chip.

The substrate chip 20 is cut out of a core pattern aggregate having a size of 4 mm × 4 mm from the aggregate of core patterns formed on the entire wafer. Evaluation chip 30 is 2 mm
A core pattern assembly having a size of 2 mm and a pattern cut out while leaving electrode pads and wiring near the boundary between core patterns adjacent to each core pattern constituting the assembly.

The cut substrate chip 20 and the evaluation chip 3
0 indicates that a gold bump is formed on the substrate chip 20 by stud bumping or plating, and the evaluation chip 3
No. 0 electrode pads are attached to each other, and connected by hot pressing at a temperature of 40 ° C. for about 30 seconds.

FIG. 3 is an explanatory diagram of the connection state of the cut chips. In FIG. 3, however, one core pattern 30a of the evaluation chip 30 and a pattern 30 including electrode pads and wiring near the boundary of the core pattern adjacent to the core pattern 30a.
b, the core pattern 20 of the substrate chip 20 opposed to the core pattern 30a and the pattern 30b of the evaluation chip 30
Only a and 20b are shown.

The cut substrate chip 20 and the evaluation chip 3
0 indicates that the evaluation chip 30 is turned upside down at the time of connection, and the core patterns 30a and 20a of the evaluation chip 30 and the substrate chip 20 are arranged so as to face each other and connected to the substrate chip 20. At this time, the pattern 30b of the evaluation chip 30 is arranged on the core pattern 20b of the substrate chip 20, and is connected via a bump.
Here, it should be noted that, between the core patterns 30a and 20a and between the pattern 30b and the core pattern 20b, in one of the patterns, there is a portion having no wiring between the electrode pads, for example, the electrode pads 32 and 33. The point between them is that a wiring is formed between the electrode pads facing each other in the other pattern, for example, between the electrode pads 23 and 24 facing between the electrode pads 32 and 33. . That is, one of the substrate chip 20 and the evaluation chip 30 made of the wiring pattern shown in FIG.
The electrode pad and the wiring formed at 0 are connected by one path.

The wiring is drawn out from the lead electrode pad 21 and the electrode pad 27 of the core pattern 20b of the substrate chip 20 to the external lead of the package by wire bonding, and is connected to the test apparatus 40. The current flowing from the test device 40 is the current flowing through the extraction electrode pad 2 of the core pattern 20b.
1 to electrode pads 22, 31, 32, 23, 24, 3
It flows in the order of 3, 34, 25, and 26, exits from the electrode pad 27, and returns to the test apparatus 40, where connection reliability is evaluated.

In FIG. 3, although an electrode pad for external input and an electrode pad for external output are provided in one core pattern, actually, wiring is routed to each core pattern and returned to the test apparatus 40. With the configuration, the position of the output electrode pad connected to the test apparatus 40 can be changed according to the purpose of connection reliability evaluation.

In the above description, the lead electrode pad 15 drawn from the wiring 13 connecting the electrode pad 11 near the side 10a is formed, and the side 10b facing the side 10a is formed.
Are formed to extend from the wiring 14 connecting the electrode pads 12 in the vicinity of the wiring, but instead of the extraction electrode pad 15, the wiring 13 and the wiring 14 are formed.
And a wiring pattern may be used in which the function of the extraction electrode pad 15 is substituted for the electrode pad 12 near the side 10b and the function of the extraction electrode pad 16 is substituted for the electrode pad 11 near the side 10a.

FIG. 4 is a schematic diagram of a core pattern having a wiring pattern for substituting the function of a lead electrode pad for another electrode pad. The core pattern 50 has a side of 1 mm
And each side 50a, 50b, 50c, 50
An electrode pad and a wiring are formed inside the area surrounded by d, an electrode pad 51 formed near the side 50a, an electrode pad 52 formed near the side 50b facing the side 50a, and an electrode pad. 2n-1 from the side of the side 50c of the pad 51
Wiring 53 connecting the nth and the 2nth, and the electrode pad 5
It is composed of a wiring 54 connecting the 2n-th and 2n + 1-th from the side of the second side 50c, and a wiring 55 connecting the wiring 53 and the wiring 54.

Further, the electrode pad 51 and the electrode pad 52 are formed such that the n-th electrode pad from the side of the side 50c is at the same distance from the side 50c,
0b.

By using the core pattern having the above structure, the number of electrode pads formed on the core pattern can be reduced and the structure of the wiring pattern can be simplified as compared with a wiring pattern in which the extraction electrode pads are drawn from the electrode pads. become. Furthermore, since the electrode pads near two opposing sides in one core pattern are connected by wiring,
By bonding the surfaces provided with the electrode pads of the core pattern, the connection reliability can be simultaneously evaluated for the electrode pads on two sides.

As described above, when bonding the surfaces having the electrode pads to each other, the core pattern connects the opposing electrode pads to each other, thereby forming one path capable of outputting an external input to the external. What is necessary is just to have the wiring pattern to be performed. In the above-described wiring pattern, in the semiconductor element having the same core pattern, the wiring pattern is such that one semiconductor element can be connected to the other semiconductor element while being vertically inverted and bonded to each other. The wiring patterns may be connected together.

FIG. 5 is a schematic view of a core pattern which can be connected in a state where the left and right sides are inverted and bonded. Core pattern 6
0 is a square having a side of 1 mm, and each side 60a, 6
An electrode pad and a wiring are formed inside the area surrounded by 0b, 60c, and 60d, and an electrode pad 61 formed near the side 60a and an electrode pad formed near the side 60b facing the side 60a. 62 and the side 60 of the electrode pad 61
Wiring 6 connecting 2n-1st and 2nth from the side of c
3, 2n-th and 2n from the side of the side 60c of the electrode pad 62.
a wiring 64 connecting the (n + 1) th wiring, and a lead electrode pad 6 drawn out from the wiring 63 to the vicinity of the electrode pad 62
5 and a lead electrode pad 66 drawn from the wiring 64 to the vicinity of the electrode pad 61.

The electrode pad 61 and the electrode pad 62 are arranged on a center line connecting the midpoint of the side 60a and the midpoint of the side 60b.
2a, electrode pads are provided symmetrically around the center line from the electrode pads 61a and 62a in the vicinity of the sides 60a and 60b, and the electrode pads 61 and 62 are formed.

The semiconductor element composed of the core pattern 60 is
If one semiconductor element is turned left and right with respect to the other semiconductor element, the surface provided with the electrode pads of one semiconductor element and the surface provided with the electrode pads of the other semiconductor element can be conducted in a bonded state. it can.

In the above description, the extraction electrode pad 65 drawn from the wiring 63 connecting the electrode pad 61 near the side 60a is formed, and the side 60b facing the side 60a is formed.
Are formed from the wiring 64 connecting the electrode pads 62 in the vicinity of the drawing, but the wiring 63 and the wiring 64 are formed instead of the drawing electrode pad 65 as shown in FIG. And a wiring pattern may be used in which the function of the extraction electrode pad 65 is substituted for the electrode pad 62 near the side 60b, and the function of the extraction electrode pad 66 is substituted for the electrode pad 61 near the side 60a. Thereby, the electrode pad 61 shown in FIG.
Compared with the core pattern 60 of the wiring pattern that draws the extraction electrode pads 65 and 66 from the core pattern 62, the number of electrode pads formed on the core pattern can be reduced, and the structure of the wiring pattern can be simplified. Furthermore, since the electrode pads near two opposing sides in one core pattern are connected by wiring, the surfaces provided with the electrode pads of the core pattern are bonded together, and the connection reliability of the two side electrode pads is simultaneously determined. Evaluation can be performed.

In the above description, an example is shown in which a wiring pattern that can be connected by inverting the core pattern upside down and a wiring pattern that can be connected by inverting the core pattern are separately implemented. Can be formed at the same time.

That is, the electrode pads formed in the vicinity of one side and in the vicinity of the side opposite to the one side have the electrode pad on the center line connecting the midpoint of the side opposite to the one side, and A core pattern is formed symmetrically with respect to the center line from the electrode pad, and the n-th electrode pad is formed at an equal distance from one side perpendicular to the side and the opposite side.

By forming such a wiring pattern, even if the core pattern is turned upside down or left and right, conduction can be achieved in a bonded state, so that a work error occurs. It becomes difficult and efficiency can be improved.

Further, also in this case, by forming a wiring pattern for substituting the function of the extraction electrode pad on the electrode pad near the side, the number of electrode pads can be reduced and the structure of the wiring pattern can be simplified. Furthermore, since the electrode pads near two opposing sides in one core pattern are connected by wiring, the surfaces provided with the electrode pads of the core pattern are bonded together, and the connection reliability of the two side electrode pads is simultaneously determined. Evaluation can be performed. If electrode pads of the same arrangement are formed not only in the vicinity of two opposing sides in one core pattern but also in the remaining two sides, the connection reliability evaluation can be performed for the electrode pads in the vicinity of four sides. Will be able to do it.

As long as the core pattern has the wiring pattern shown in the above description, the semiconductor elements alternately arranged in a state of being rotated by 90 degrees with respect to the adjacent core pattern also include:
Similar effects can be obtained.

FIG. 6 is a diagram showing a state where the core patterns rotated by 90 degrees are adjacent to each other. In the core pattern 70, electrode pads 71, 72, 73, 74 are formed near four sides, and one side and the electrode pads 71, 72 formed near the opposite side are connected by wiring. And has a wiring pattern that can be inverted vertically and horizontally. Similarly, in the core pattern 80, electrode pads 81, 82, 83, 84 are formed near four sides, and one side and the electrode pads 83, 84 formed near the opposing sides are interconnected. Connected by
In addition, it has a wiring pattern that can be inverted vertically and horizontally. The core pattern 80 has a core pattern 70 of 90.
The wiring pattern is rotated by one degree and is arranged adjacent to the core pattern 70. Core patterns 70 and 80
Is a block, and the blocks are continuously arranged to form a semiconductor element.

In the semiconductor device having the above-described configuration, for example, when the core pattern 80 is bonded to the core pattern 70 by inverting the core pattern 80 left and right, the electrode pads 71 and 81, 72 and 8 are formed.
2, 73 and 84, and 74 and 83 are respectively connected by one path. Further, electrode pads 71 and 72, 83 and 8
Since 4 is connected by wiring, connection reliability can be evaluated for electrode pads near the four sides of the core pattern.

In the case of a semiconductor device in which the core patterns 70 and 80 are formed as one block, and these blocks are continuously arranged, each core pattern constituting the semiconductor device has four core patterns.
Since the connection reliability of the electrode pads near the side can be evaluated, more reliable data can be obtained.

The cutout sizes of the substrate chip and the evaluation chip in the above description are merely examples, and the cutout size can be arbitrarily cut to a chip size necessary for evaluating the connection reliability. The connection between the evaluation chip and the substrate chip is made by gold bumps, but the material may be other than gold. Further, the bump may be formed by any method such as forming only on the evaluation chip, forming only on the substrate chip, or forming both on the evaluation chip and the substrate chip.

[0044]

As described above, according to the present invention, the core pattern of a semiconductor element is bonded to one core pattern and the other core pattern, and the electrode pad and wiring of one core pattern are connected to the other core pattern. The wiring pattern is such that the electrode pad and the wiring are electrically connected through one path, and furthermore, the electrode pad is drawn out from the electrode pad so as to be connected to the outside. As a result, an evaluation chip and a substrate chip are cut out from a wafer made of a core pattern having the same wiring pattern, produced, and then appropriately inverted and bonded for connection to evaluate the connection reliability of the chip-on-chip structure. Therefore, the evaluation chip and the substrate chip can be manufactured from the same mask pattern, the mask material used for manufacturing the semiconductor element can be reduced, and the semiconductor element can be manufactured at low cost.

Furthermore, since it is possible to cope with the connection reliability evaluation of semiconductor elements having different sizes only by changing the size of the cut out from the wafer, the versatility of the wiring pattern is high, and the cost of the connection reliability evaluation can be reduced. Efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a core pattern.

FIGS. 2A and 2B are diagrams in which a core pattern formed on a wafer is cut out to a chip size, and FIG.
(B) shows an evaluation chip.

FIG. 3 is an explanatory diagram of a connection state of a cut chip.

FIG. 4 is a schematic diagram of a core pattern having a wiring pattern that substitutes the function of a lead electrode pad for another electrode pad.

FIG. 5 is a schematic view of a core pattern that can be connected in a state where the left and right sides are inverted and bonded.

FIG. 6 is a diagram showing a state in which core patterns rotated by 90 degrees are adjacent to each other.

FIG. 7 is a schematic diagram of a state where an evaluation chip and a substrate chip are connected.

[Explanation of symbols]

10 core patterns, 10a, 10b, 10c, 10
d ... side, 11,12 ... electrode pad, 13,14 ...
Wiring, 15, 16 ... Lead electrode pads.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kazuo Nishiyama 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 4M106 AA02 AA07 AB15 AD01 AD07 AD24 AD26 BA14 CA15

Claims (4)

[Claims] 1. A semiconductor element comprising a quadrangular core pattern, a core pattern comprising: an electrode pad; a wiring for electrically connecting the electrode pads; and a lead electrode pad drawn from the electrode pad. Laminating the core pattern and another core pattern,
A wiring pattern in which the electrode pad and the wiring and the other electrode pad and the other wiring are electrically connected by one path. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a wiring pattern in which the extraction electrode pad is replaced with the electrode pad. 3. An arrangement pattern wherein the core pattern and a core pattern obtained by rotating the core pattern by 90 degrees are arranged alternately and continuously.
The semiconductor element as described in the above. 4. A method for evaluating a semiconductor device, wherein: a core pattern including: an electrode pad; a wiring for electrically connecting the electrode pads; and a lead electrode pad drawn out from the electrode pad; And other core patterns,
A wiring pattern in which the electrode pad and the wiring and the other electrode pad and the other wiring are electrically connected in one path; and using the semiconductor element having: And bonding the electrode pad to another electrode pad, connecting the lead electrode pad to an external device, and evaluating conduction between the semiconductor element and the other semiconductor element. Element evaluation method.