563220 玖、發明說明 本發明關於一種將半導體構件（1)之有缺陷（瑕疵）的 介電質選出的方法，特別是將一 MOS構件的有缺陷的電晶 體閘極選出者。 雖然本發明可用於任何半導體構件，但本發明以及其 針對的標的係就具有由二氧化矽構成的電晶體閘極或介電 質（Dielektdka)的MOS構件作說明。 一般在製造晶片時，在一些MOS構件上會造成一定之 早期故障率。因此將晶片供應到買主之前，該構件或晶片 要件檢查程序。 該M〇S構件的故障（Ausfall)主要的原因是該介電質或 閘極由於有故障的位置而帶有缺陷，而在使用時因此無功 能能力。 一般這種檢查程序在已經製做完成的構件進行，該構 件已設了端子並作了封裝。如此，在該溫度與電壓限度範 圍中該構件要作許多小時的長時作業，並將發生的故障檢 出。然而這種檢查程序是一種費成本費時的程序，因爲要 用本來的檢查裝置在已製成的構件作檢查。 因此本發明的目的主要在於提供一種將有缺陷的介電 質選出的方法，俾能花較小成本及時間實施。 在先行技術中有一些如下的方案用於解決這種問題。 在一個已製成但尙未封裝的晶片上，裝上一種輔助接線 (Hilfsverdrahtung)，經由該輔助接線將所要檢查的介電質或 閘氧化物作電接觸。在檢查之後，在製成的構件上作附加 563220 的程序將該輔助接線再除去。 上述習知的解決方案的缺點爲：該檢查程序係在已製 成的晶片上作，故只能施有限的負載（Stress)到該對應的介 電質上，此外，該構件在操作時利用施加的信號而作檢查 【本發明的優點】 與該習知之解決方案相較，具有申請專利範圍第1項 的特徵點的本發明的方法的優點在於：可在該構件的原來 的製程時已進行有缺陷介電質的選出作業。 本發明的基本構想在於：在該構件的製程時，在該已 構造化的介電質的一側上製造一檢查層，以將該介電質同 時作電接觸；藉著將一電壓施到介電質一側上的檢查層以 及施到介電質另一側上的基質以將介電質的功能能力同時 作檢查；且將該檢查層除去或構造化，以繼續進行該構件 的原來的製程。 如此可使相關的介電質的功能能力的檢查的成本及時 間減到最少，其中一晶片的所有構件可藉著施一股適當電 負載而同時檢查，也可依標的將特定的層接通並施加一股 電負載。 此外不需使用信號以作測試程序，只要平行地施加一 股電壓即足’如此要受到負載的所有材料部件就同時接通 並作檢測。 在申請專利範圍附屬項中係爲申請專利範圍第1項的 方法的有利的進一步特色與改良。 6 563220 依一較佳的進一步特點，該檢查層係藉著在本來的製 程中已存在的材料層上作「中間構造化步驟」而製造，如 此可省卻附加的析出作業（Abscheidung)。 依另一較佳的進一步特點，除了原來的製程外，將該 檢查層析出，構造化且在檢查後再拿掉。如此可依標的將 特定的可疑的介電質接通並作最終檢測。 依又一較佳的進一步特點，利用光蝕刻 (Photolithographie)及/或餓刻程序形成畦溝（Grab)而將晶片 互相分離。如此可利用一道單一程序步驟將在一基質上的 所有基片設以一檢查層，然後互相分離成互不導電的方式 〇 依再一較佳的進一步特點，在該構件的已構造化的金 屬鑛層上將檢查層構造化而製成，以同時將該介電質作電 接觸。 依還有一種較佳的進一步特點，該檢查層藉光蝕刻及 或蝕刻程序構造化，如有必要並除去。 依又有一種較佳的進一步特點，該檢查層由聚合矽 (Poly-Silizium)或聚合 5夕鍺（Poly-Silizium-Germanium)形成。 依另外一較佳的進一步特點，爲了檢查該接觸的介電 質，在一側將電壓經由一接點針施加，並在另一側直接經 由該基質或經由一個與該基質連接的裝置施加。如此可控 制檢查所需的場強度。 依此外一較佳的進一步特點，將該選出的有缺陷的介 電質或因而有瑕疵的構件作標示或修理。 563220 本發明的實施例示於圖式中並在以下說明書中詳細敘 書。 【實施方式】 第1圖顯示一個半導體構件（1)的橫剖視圖，它具有依 本發明一實施例施加的檢查層（3)。 在一基質（4)〔例如在一矽基質（4)〕上用習知方式利用 光蝕刻法在基質（4)中形成摻雜成p或η型的區域（5)，以製 造構件，例如MOS構件（1)。該電晶體閘的介電質（2)〔例 如一種閘氧化物層（2)〕同樣地用習知方式在塞質中製造。 在一般的製程中，舉例而言，下一步驟係在閘氧化物 層上形成一個構造化的聚矽層，以製造閘接觸構造。 但依本發明此實施例，在形成該構造化的聚矽層前， 在所有晶片（10)上方整個面積用習知方式析出一個檢查層 (3)。如此，所有晶片（10)都完全用該檢查層（3)〔例如一個 聚矽層（3)〕蓋住，如此所有介電質（2)都平行（並聯）地作 電接觸。 如第2圖所示，宜利用例如蝕刻程序在個別之晶片（10) 之間產生畦溝（11)，將各晶片（10)互相隔開成互不導電。 下一步係將一定電壓施到該電檢查層（3)，例如利用第 2圖所示之接點針（8)施加。藉著將一股對應的對立電壓 (Gegenspahnung，英：counter-voltage)施加到該介電質（2)下 側〔可直接施到基質（4)上或間接地施到與基質（4)連接的金 屬板（9)、盆或類似物上〕在閘氧化物（2)上產生一電場。 在材料脆弱處（例如呈故障位置之類形式者）的位置 563220 ，導電性增加，因此引起相關之介電質（2)早期故障。含有 損壞之閘層（2)的構件（1)可用這種方式在施加電壓時測量靜 止電流在製程中就將它們篩選出及辨識出。 藉著將該構件作相關的記號或將損壞修復，可使製造 的構件或晶片的故障率大大地減少。 同樣地，也可在形成畦溝（11)之前，將電壓施加到該形 成整個面積的檢查層（3)而將所有晶片同時作檢查，但藉著 形成畦溝（11)，可使有瑕疵的區域侷限在局部。 在將有瑕疵的閘氧化物⑵或構件（1)作過檢測以及可能 之標示及修復後，可將析出的檢查層（3)利用習知之蝕刻法 除去或利用相關的光蝕刻及/或蝕刻程序做成構造化層， 而在進一步的製程中進一步使用以形成半導體構件（1)。 然後用習知方式繼續進行原來的製程。 依本發明另一實施例，該檢查層（3)並非直接析出到所 要檢查的閘氧化物（2)上，而係事先以習知方式形成一構造 化的鍍金屬層，以與該MOS構件（1)的控制裝置作導電接觸 〇 在此鑛金屬層構造化後，才將一附加之構造化的檢查 層（3)整合到製程中。經由此檢查層（3)可使所有電晶體閘接 觸。在此要避免該電晶體閘直接與其他功能端子連接。 如上述’將一股電壓施加到該構造化的檢查層（3 )，以 檢查介電層（2)，其中原來的檢查過程以與上述實施例相似 的方式進行。 在檢查過程結束後，該檢查層（3)可再除去（例如利用 563220 蝕刻）。 本發明可使閘材料（例如MOS構件的閘材料）在製程 中在一定條件施加電場或電負載，以高度涵蓋率施加，可 以對構件作監視（靜止電流測量）。 如此可避免在封裝或製成的構件上的繁複之檢查過程 ，並提高檢查效率，因爲檢查程序與所製之構件的操作條 件無關。因此可得到較佳的檢查涵蓋率，因爲在檢查時所 有電晶體閘都被檢出，且電壓及溫度可配合材料需求及瑕 疵機構而最佳化。 雖然本發明利用較佳實施例作說明，但其範疇並不限 於此，且可用種種方式作變更。 【圖式簡單說明】 (一）圖式部分 第1圖係一構件的橫剖視圖，它具有本發明一實施例 施加的檢查層， 第2圖係依本發明一實施例在一晶圓基質上多個晶片 之設置的立體圖。 (一）兀件代表符號 (1) 構件 (2) 介電質 (3) 檢查層 (4) 基質 (5) 摻雜式p或η型的區域 (8) 接點針 563220 (9) (10) (11) 金屬板 晶片 畦溝563220 (1) Description of the invention The present invention relates to a method for selecting a defective (defective) dielectric of a semiconductor component (1), in particular, a person who selects a defective electrical gate of a MOS component. Although the present invention can be applied to any semiconductor device, the present invention and the target system thereof are described with a MOS device having a transistor gate or a dielectric (Dielektdka) made of silicon dioxide. Generally, when manufacturing a wafer, a certain early failure rate is caused on some MOS components. The component or wafer requirements are therefore inspected before the wafer is supplied to the buyer. The main cause of the failure of the MOS component (Ausfall) is that the dielectric or the gate is defective due to the faulty position, and is therefore incapable of function during use. Generally, this inspection procedure is performed on a component that has already been manufactured, and the component has been provided with terminals and packaged. In this way, the component has to perform many hours of long-term operation within the temperature and voltage limits, and the faults that occur are detected. However, this inspection procedure is a costly and time-consuming procedure because the inspection is performed on the manufactured components using the original inspection device. The purpose of the present invention is therefore to provide a method for selecting defective dielectrics, which can be implemented with less cost and time. There are some solutions in the prior art to solve this problem. On a fabricated but unpackaged chip, an auxiliary wiring (Hilfsverdrahtung) is mounted, and the dielectric or gate oxide to be inspected is electrically contacted via the auxiliary wiring. After inspection, a procedure of adding 563220 to the finished component is used to remove the auxiliary wiring. The disadvantage of the above-mentioned conventional solution is that the inspection procedure is performed on a wafer that has already been manufactured, so only a limited load can be applied to the corresponding dielectric. In addition, the component is used during operation. The applied signal is checked. [Advantage of the present invention] Compared with the known solution, the method of the present invention having the characteristic point of the scope of patent application No. 1 has the advantage that it can be used during the original process of the component. Select defective dielectrics. The basic idea of the present invention is: during the manufacturing process of the component, an inspection layer is manufactured on one side of the structured dielectric to make the dielectric in electrical contact at the same time; by applying a voltage to An inspection layer on one side of the dielectric and a substrate applied to the other side of the dielectric to simultaneously inspect the functional capabilities of the dielectric; and remove or construct the inspection layer to continue the original structure of the component Process. In this way, the cost and time of the inspection of the functional capabilities of related dielectric materials can be minimized. All components of a chip can be inspected at the same time by applying an appropriate electrical load, or a specific layer can be connected according to the standard And apply an electrical load. In addition, there is no need to use a signal as a test procedure, as long as a voltage is applied in parallel, it is sufficient that all material parts that are to be subjected to a load are simultaneously switched on and tested. The appended item of the patent application scope is an advantageous further feature and improvement of the method of the first patent application scope. 6 563220 According to a preferred further feature, the inspection layer is manufactured by performing an "intermediate structuring step" on a material layer that already exists in the original process, thus eliminating additional precipitation operations (Abscheidung). According to another preferred further feature, in addition to the original process, the inspection is chromatographed, structured and removed after inspection. In this way, specific suspicious dielectrics can be switched on for final detection according to the standard. According to yet another preferred feature, the wafers are separated from each other by forming a grab using a photolithographie and / or a lithography process. In this way, a single process step can be used to set all the substrates on a substrate with an inspection layer, and then separate them from each other into a non-conductive manner. According to yet another preferred further feature, the structured metal of the component The inspection layer is structured and formed on the ore layer to make electrical contact with the dielectric at the same time. According to a further preferred feature, the inspection layer is structured by photo-etching and / or etching procedures and removed if necessary. According to yet another preferred feature, the inspection layer is formed of Poly-Silizium or Poly-Silizium-Germanium. According to another preferred further feature, in order to check the contacting dielectric, a voltage is applied on one side via a contact pin and on the other side directly via the substrate or via a device connected to the substrate. This controls the field strength required for inspection. According to another preferred further feature, the selected defective dielectric or thus defective component is marked or repaired. 563220 Embodiments of the invention are shown in the drawings and are described in detail in the following description. [Embodiment] Fig. 1 shows a cross-sectional view of a semiconductor component (1) having an inspection layer (3) applied according to an embodiment of the present invention. Forming a region (5) doped into the p or n-type in the substrate (4) by photolithography in a conventional manner on a substrate (4) [eg, a silicon substrate (4)] to manufacture a component, such as MOS component (1). The dielectric substance (2) of the transistor (for example, a gate oxide layer (2)) is similarly manufactured in a plug substance in a conventional manner. In a general process, for example, the next step is to form a structured polysilicon layer on the gate oxide layer to make a gate contact structure. However, according to this embodiment of the present invention, before forming the structured polysilicon layer, an inspection layer (3) is deposited in a conventional manner over the entire area of all the wafers (10). In this way, all the wafers (10) are completely covered with the inspection layer (3) [for example, a polysilicon layer (3)], so that all the dielectrics (2) are in electrical contact in parallel (parallel). As shown in FIG. 2, it is preferable to use an etching process to generate trenches (11) between individual wafers (10), and separate the wafers (10) from each other to be non-conductive. The next step is to apply a certain voltage to the electrical inspection layer (3), for example, using a contact pin (8) shown in FIG. By applying a corresponding counter-voltage (Gegenspahnung, English: counter-voltage) to the lower side of the dielectric (2) [can be directly applied to the substrate (4) or indirectly applied to the substrate (4) Metal plate (9), pot or the like] generates an electric field on the gate oxide (2). At the location of the material where the material is weak (for example, in the form of a fault location), 563220, the conductivity is increased, thus causing the related dielectric (2) early failure. Components (1) containing damaged gates (2) can be screened and identified during the manufacturing process by measuring the static current when a voltage is applied. By marking the component or repairing the damage, the failure rate of the manufactured component or wafer can be greatly reduced. Similarly, before forming the trench (11), a voltage can be applied to the inspection layer (3) forming the entire area to inspect all the wafers at the same time, but by forming the trench (11), defects can be caused. The area is localized. After inspecting defective gate oxides or components (1), and possibly marking and repairing them, the deposited inspection layer (3) can be removed by conventional etching methods or by using related photoetching and / or etching. The program is made into a structured layer, which is further used in a further process to form a semiconductor component (1). Then continue the original process in a conventional manner. According to another embodiment of the present invention, the inspection layer (3) is not directly deposited on the gate oxide (2) to be inspected, but a structured metal plating layer is formed in advance in a conventional manner to communicate with the MOS component. (1) The control device makes conductive contact. After the ore metal layer is structured, an additional structured inspection layer (3) is integrated into the manufacturing process. Through this inspection layer (3), all transistor gates can be brought into contact. Avoid direct connection of this thyristor with other functional terminals. As described above, a voltage is applied to the structured inspection layer (3) to inspect the dielectric layer (2), wherein the original inspection process is performed in a similar manner to the above embodiment. After the inspection process is completed, the inspection layer (3) can be removed again (for example, using 563220 etching). The invention enables the gate material (such as the gate material of the MOS component) to apply an electric field or an electric load under certain conditions during the manufacturing process, and is applied at a high coverage rate, which can monitor the component (static current measurement). This can avoid the complicated inspection process on the packaged or fabricated components, and improve the inspection efficiency, because the inspection procedure is independent of the operating conditions of the fabricated components. Therefore, a better inspection coverage can be obtained, because all the thyristors are detected during the inspection, and the voltage and temperature can be optimized according to the material requirements and the defective mechanism. Although the present invention is described using the preferred embodiment, its scope is not limited thereto, and can be changed in various ways. [Brief description of the drawings] (1) Figure 1 of the schematic part is a cross-sectional view of a component, which has an inspection layer applied in an embodiment of the present invention, and Figure 2 is a wafer substrate according to an embodiment of the present invention A perspective view of the arrangement of multiple wafers. (1) Representative symbol of element (1) Component (2) Dielectric (3) Inspection layer (4) Substrate (5) Doped p or n-type region (8) Contact pin 563220 (9) (10 ) (11) Metal plate wafer trench
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