JP2011216540A - Semiconductor device and resistance measurement method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a chip layout which has a reducible circuit area while reducing trouble occurring during manufacture.SOLUTION: The semiconductor device includes a first pad 1 for current source connection, a via chain which has one end connected to the first pad 1 and the other end connected to a substrate 20 via a diffusion layer 21 of the same conductivity type as the substrate 20, and a second pad 2 and a third pad 3 for voltage measurement. The via chain includes first wiring 4 to which the first pad 1 and second pad 2 are connected, and a via or contact 6 which has one end connected to the first wiring 4 and the other end connected to the third pad and whose resistance is to be measured.

Description

  The present invention relates to a semiconductor device and a resistance measuring method, and more particularly, to a semiconductor device having a resistance value measurement pattern and a via or contact resistance measuring method using the semiconductor device.

  When forming a semiconductor integrated circuit (IC chip) on a semiconductor wafer, a so-called TEG (Test Element Group) pattern for detecting defective formation of elements on the IC chip is formed on the semiconductor wafer. .

  When manufacturing an IC chip, the formation state of each element (for example, wiring, via, diffusion layer) in the IC chip can be monitored by evaluating the electrical characteristics of the TEG. For example, via chains (also referred to as contact chains) and Kelvin patterns are known as TEGs for measuring the connection state (conduction state) of vias and contacts connecting between wirings and their resistance values.

  A technique for evaluating via resistance using a via chain is described in, for example, Japanese Patent Application Laid-Open No. 2007-305918 (see Patent Document 1). In Patent Document 1, via resistance in a via chain is evaluated by a two-terminal method.

  In the case of resistance evaluation by the two-terminal method, there is a problem that the measurement accuracy of via resistance is reduced due to the contact resistance between the probe for passing a current through the via chain and the measurement pad. In recent years, with the miniaturization of processes, the influence on the measured value due to the contact resistance described above cannot be ignored. For this reason, when measuring the via resistance with high accuracy, a four-terminal method is used in which the via resistance can be measured without being affected by the contact resistance between the probe and the measurement pad.

  FIG. 1 is a plan view showing a basic structure of a Kelvin pattern whose via resistance is measured by a four-terminal method. 2A is a cross-sectional view taken along the line A-A ′ shown in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line B-B ′ shown in FIG. 1. Via resistance measurement by the four-terminal method will be described with reference to FIGS. 1, 2A, and 2B.

  The check pattern forming the Kelvin pattern includes four pads 71 to 74 and an upper wiring 81 and a lower wiring 82 connected to the via 90 to be measured. Specifically, the pads 71, 72, 73, 74 are formed on the same wiring layer. The upper portion of the via 90 to be measured is connected to the pads 71 and 73 via the upper wiring 81, and the lower portion of the via 90 is connected to the pads 72 and 74 via the lower wiring 82.

  A measuring instrument that performs resistance measurement by the four-terminal method includes a DC current source 100, voltmeters 101 and 102, and four probes 201 to 204.

  When performing resistance measurement, the probe 201, the probe 202, the probe 203, and the probe 204 are brought into contact with the pad 71, the pad 72, the pad 73, and the pad 74, respectively. Subsequently, the current I is supplied from the probe 201 to the grounded probe 204 by the current source 100. At this time, the voltages V1 and V2 of the probe 202 and the probe 203 are measured by the voltmeters 101 and 102, respectively.

As a result, the resistance R of the via 90 is obtained by the equation (1).
R = (V2-V1) / I (1)
In the four-terminal method, the measured voltages V1 and V2 are not affected by the contact resistance between the probe 201 and the pad 71 from the current source 100, so that the minute via resistance R can be accurately measured.

  An element shape evaluation method using such a four-terminal method is described in, for example, Japanese Patent Application Laid-Open No. 10-135512 (see Patent Document 2) and Japanese Translation of PCT International Publication No. 2004-537859 (see Patent Document 3).

JP2007-305918 JP-A-10-135212 Special table 2004-537859

  When it is desired to measure a minute resistance, a total of four terminals are required, as described above, two terminals for supplying current and two terminals for measuring voltage. In this case, it is necessary to provide four pads for securing four terminals. In addition, four probes must be prepared for measuring via resistance.

  In recent years, there is an increasing demand for circuit area reduction, test efficiency improvement, and test time reduction. For this reason, it is required to reduce the number of pads and the number of probes for measuring via resistance. If the two-terminal method is used, the number of pads and the number of probes can be reduced, but there is a problem that the measurement accuracy is lowered as described above.

  From the above, there is a strong demand for a method for measuring a TEG pattern with few pads and a via resistance (contact resistance) with a small number of probes while maintaining high measurement accuracy.

  In order to solve the above problems, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention] The number / symbol used in [Form] is added. However, the added numbers and symbols should not be used to limit the technical scope of the invention described in [Claims].

  The semiconductor device according to the present invention includes a first pad (1) for connecting a current source, a diffusion layer (21 having one end connected to the first pad (1) and the other end being the same as the substrate (20). ), A via chain connected to the substrate (20) via a second electrode (2) and a third pad (3) for voltage measurement. The via chain includes a first wiring (4) to which the first pad (1) and the second pad (2) are connected, one end connected to the first wiring (4), and the other end to the third pad (3). And vias or contacts (for example, 6) to be resistance-measured. In the present invention, in the state where current flows from the first pad (1) to the substrate (20) through the via chain, the voltage value measured through the second pad (2) and the third pad (3) is used. The resistance of the resistance measurement object (for example, 6) is measured.

  The resistance measurement method according to the present invention includes a step of passing a current from the first pad (1) to the substrate (2), and a first wiring (4) provided on the first wiring (4) provided with the first pad (1). The step of measuring the first voltage (V1) of the two pads (2) and the second wiring (for example, 5) connected to the first wiring (4) through the resistance measurement target (for example, 6) Resistance measurement using the step of measuring the second voltage (V2) of the third pad (3) and the measured values of the current magnitude (I), the first voltage (V1), and the second voltage (V2). Calculating a resistance value of the object. Here, the current (I) reaches the substrate (20) from the first pad (1) via the via or contact to be measured for resistance and the diffusion layer (21) provided on the substrate (20). The diffusion layer (21) flows through the path and has the same conductivity type as the substrate.

  As described above, the present invention eliminates the need for a probe and a pad for grounding by connecting one end of the current path for resistance measurement to the substrate. Further, since the via chain is connected through the diffusion layer of the same conductivity type as that of the substrate, the resistance value in the current path becomes small. Thereby, increase of the measured voltage value can be prevented.

  Therefore, according to the present invention, it is possible to accurately measure via resistance or contact resistance with a small number of probes.

  In addition, the area of the test pattern capable of precise measurement of via resistance or contact resistance can be reduced.

FIG. 1 is a plan view showing a basic structure of a Kelvin pattern whose via resistance is measured by a four-terminal method. FIG. 2A is a cross-sectional view taken along line A-A ′ shown in FIG. 1. 2B is a cross-sectional view taken along line B-B ′ shown in FIG. 1. FIG. 3 is a plan view showing an example of the structure of the semiconductor device according to the present invention. FIG. 4 is a sectional view showing an example of the structure of the semiconductor device according to the present invention. FIG. 5 is a sectional view showing another example of the structure of the semiconductor device according to the present invention. FIG. 6 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention. FIG. 7 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention. FIG. 8 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention. FIG. 9 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention. FIG. 10 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention. FIG. 11 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention. FIG. 12 is a cross-sectional view showing a mechanism of via formation failure due to capacitive connection. FIG. 13 is a sectional view showing still another example of the structure of the semiconductor device according to the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same or similar reference numerals indicate the same, similar, or equivalent components. A semiconductor device according to the present invention (hereinafter referred to as a TEG pattern) is a check pattern that is provided on a semiconductor wafer together with an IC chip and is used for accurately measuring the resistance of vias or contacts provided on the IC chip. The TEG pattern according to the present invention may be provided in the IC chip or in an area outside the IC chip (for example, a scribe area).

  First, the structure of the TEG pattern according to the present invention will be described. FIG. 3 is a plan view showing an example of the structure of the TEG pattern according to the present invention. FIG. 4 is a sectional view showing an example of the structure of the TEG pattern according to the present invention. With reference to FIG. 3 and FIG. 4, an example of the structure of the TEG pattern and the method of measuring the via resistance according to the present invention will be described. The TEG pattern in this example is a check pattern for measuring the resistance of the vias 6 and 7 connecting the two-part wiring.

  Referring to FIGS. 3 and 4, the TEG pattern according to this example includes pads 1, 2, 3, upper wirings 4, 5, measurement target vias 6, 7, lower wirings 8, 10, via group 9, contact group 11. And a substrate 20 having a P + diffusion layer 21 and a silicide layer 22 formed in the vicinity of the surface.

  The upper wirings 4 and 5 are formed in the same second wiring layer (upper wiring layer: 2Metal) and are electrically isolated from each other by an element isolation region (not shown). The lower wirings 8 and 10 are formed in the same first wiring layer (lower wiring layer: 1 Metal) and are electrically isolated from each other by an element isolation region (not shown). The vias 6 and 7 each have a resistance R and are provided between the upper wiring layer and the lower wiring layer. The upper wiring 4 is connected to one end of the lower wiring 8 through the via 6, and one end of the upper wiring 5 is connected to the other end of the lower wiring 8 through the via 7. The other end of the upper wiring 5 is connected to the lower wiring 10 via a via group 9 provided between the second wiring layer and the first wiring layer. Further, the lower wiring 10 is connected to the substrate 20 via a contact group 11 provided between the first wiring layer and the substrate 20.

  In the boundary region on the substrate 20 to which the contact group 11 and the substrate 20 are connected, a silicide layer 22 and a diffusion layer having the same conductivity type as the substrate 20 (here, P + diffusion layer 21) are formed in order from the upper layer. It is preferable. Since the contact group 11 is connected to the substrate 20 via the silicide layer 22 and the P + diffusion layer 21, the resistance between the contact group 11 and the substrate 20 can be reduced. Thereby, the resistance on the current path for measuring the via resistance can be reduced. Note that the effect of reducing the resistance is greater when the contact group 11 and the substrate 20 are connected via the silicide layer 22, but the installation of the silicide layer 22 may be omitted.

  The pads 1, 2, 3 and the upper wirings 4, 5 are provided in the same second wiring layer. The pad 1 is connected to the upper wiring 4 and functions as a current supply pad. The pad 2 is connected to the upper wiring 4 and functions as a pad for measuring the voltage at the end of the measurement target via 6. The pad 3 is connected to the upper wiring 5 and functions as a pad for measuring the voltage at the end of the measurement target via 7.

  As described above, in the example shown in FIG. 4, a via chain in which one end is connected to the current source connection pad 1 and the other end is connected to the substrate 20 is formed. Hereinafter, not only a via chain in which wirings are connected by vias and contacts but also a contact chain in which wirings are connected only by contacts will be referred to as via chains.

  Next, a method for measuring via resistance using the TEG pattern according to the present invention will be described.

  The probes 201 to 203 are brought into contact with the pads 1 to 3, respectively. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1, the probe 202 of the voltmeter 101 is brought into contact with the pad 2, and the probe 203 of the voltmeter 102 is brought into contact with the pad 3. The current I supplied from the current source 100 to the pad 1 includes the upper wiring 4, the via 6, the lower wiring 8, the via 7, the upper wiring 5, the via group 9, the lower wiring 10, the contact group 11, the silicide layer 22, and P +. It flows through a path (via chain) that reaches the substrate 20 via the diffusion layer 21. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

While the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Assuming that the current value from the current source 100 is I, the resistance R of each of the vias 6 and 7 is expressed by the equation (2). However, the vias 6 and 7 have the same resistance value R.
R = (V1-V2) / 2I (2)

  As described above, by using the TEG pattern according to the present invention, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the via resistance with three probes.

  In the present invention, in order to reduce the resistance component between the contact group 11 and the substrate 20, the contact group and the substrate 20 are interposed via the P + diffusion layer 21 and the silicide layer 22 doped with impurities higher in concentration than the substrate 20. And connected. Thereby, the resistance of the current path from the probe 201 to the substrate 20 can be reduced, and the rise of the measurement voltages V1 and V2 can be suppressed. In addition, it is preferable to set a large number of vias in the via group 9 and a large number of contacts in the contact group 11 to reduce the resistance component in the via group 9 and the contact group 11.

  For example, if the measurement current I is small and the measurement voltages V1 and V2 are large, the probes 202 and 204 may melt and measurement may become impossible. When the current flowing through the substrate 20 is used, the measurement voltages V1 and V2 may increase due to the connection resistance with the substrate 20. However, as described above, in the present invention, since the resistance between the substrate 20 and the contact group 11 is reduced, such a problem does not occur.

  Next, a modified example of the TEG pattern shown in FIG. 4 will be described with reference to FIG. In the TEG pattern shown in FIG. 4, the via resistance measurement pad is provided in the second wiring layer. However, the present invention is not limited thereto, and the via resistance measurement pad may be provided in the first wiring layer. Referring to FIG. 5, the TEG pattern according to this example is a substrate in which lower wirings 14 and 15, measurement target contacts 16 and 17, contact group 19, and P + diffusion layer 21 and silicide layers 22 and 28 are formed in the vicinity of the surface. 20.

  The lower wirings 14 and 15 are formed in the same first wiring layer and are electrically isolated from each other by an element isolation region (not shown). Each of the contacts 16 and 17 has a resistance R and is provided between the substrate 20 and the lower wiring layer. The lower wiring 14 is connected to one end of the silicide layer 28 via the contact 16, and one end of the lower wiring 15 is connected to the other end of the silicide layer 28 via the contact 17. The other end of the lower wiring 15 is connected to the substrate 20 via a contact group 19, a silicide layer 22, and a P + diffusion layer 21 provided between the substrate 20 and the first wiring layer.

  In the boundary region on the substrate 20 to which the contact group 19 and the substrate 20 are connected, a silicide layer 22 and a diffusion layer having the same conductivity type as the substrate 20 (here, P + diffusion layer 21) are formed in order from the upper layer. It is preferable. Since the contact group 19 is connected to the substrate 20 via the silicide layer 22 and the P + diffusion layer 21, the resistance between the contact group 11 and the substrate 20 can be reduced. Thereby, the resistance on the current path for measuring the via resistance can be reduced. Note that the effect of lowering the resistance is greater when the contact group 19 and the substrate 20 are connected via the silicide layer 22, but the installation of the silicide layer 22 may be omitted.

  Pads 1, 2, 3 (not shown) are provided in the same first wiring layer as the lower wirings 14, 15. The pad 1 is connected to the lower wiring 14 and functions as a current supply pad. The pad 2 is connected to the lower wiring 14 and functions as a pad for measuring the voltage at the end of the measurement target contact 16. The pad 3 is connected to the lower wiring 15 and functions as a pad for measuring the voltage at the end of the measurement target contact 17.

  As described above, in the example shown in FIG. 5, a via chain (contact chain) in which one end is connected to the current source connection pad 1 and the other end is connected to the substrate 20 is formed.

  Next, a method for measuring via resistance using the TEG pattern in this example will be described.

  Also in the example shown in FIG. 5, the probes 201 to 203 are brought into contact with the pads 1 to 3, respectively, as described above. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1, the probe 202 of the voltmeter 101 is brought into contact with the pad 2, and the probe 203 of the voltmeter 102 is brought into contact with the pad 3. The current I supplied from the current source 100 to the pad 1 passes through the lower wiring 14, the contact 16, the silicide layer 28, the contact 17, the lower wiring 15, the contact group 19, the silicide layer 22, and the P + diffusion layer 21, It flows along the route (via chain) leading to 20. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

  Similarly to the above, while the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Assuming that the current value from the current source 100 is I, the resistance R of the contacts 16 and 17 is expressed by the following equation (2). However, the contacts 16 and 17 are assumed to have the same resistance value R.

  As described above, even when a pad is connected to the lower wiring layer, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the contact resistance with three probes.

  In the present invention, the contact group and the substrate 20 are connected through the P + diffusion layer 21 and the silicide layer 22 in order to reduce the resistance component between the contact group 19 and the substrate 20. Thereby, the resistance of the current path from the probe 201 to the substrate 20 can be reduced, and the rise of the measurement voltages V1 and V2 can be suppressed. Further, it is preferable to reduce the resistance component in the contact group 11 by setting a large number of contacts in the contact group 19.

  For example, if the measurement current I is small and the measurement voltages V1 and V2 are large, the probes 202 and 204 may melt and measurement may become impossible. When the current flowing through the substrate 20 is used, the measurement voltages V1 and V2 may increase due to the connection resistance with the substrate 20. However, as described above, in the present invention, since the resistance between the substrate 20 and the contact group 19 is reduced, such a problem does not occur.

  In the example shown in FIGS. 3 to 5, the method of measuring the via resistance or the contact resistance using the current through the resistance of two vias or contacts has been described, but the current through one via or contact is measured. Resistance measurement may be performed using this.

  FIG. 6 is a cross-sectional view showing an example of a configuration of a TEG pattern in which a measurement pad is provided in the second wiring layer and the resistance of one via can be measured. The TEG pattern shown in FIG. 6 includes the upper wirings 4 and 5, the measurement target via 6, the lower wiring 18, the via group 9, the contact group 11, and the substrate 20 on which the P + diffusion layer 21 and the silicide layer 22 are formed near the surface. To do.

  The upper wirings 4 and 5 are formed in the same second wiring layer and are electrically separated from each other by an element isolation region (not shown). The lower wiring 18 is formed in the first wiring layer. The via 6 has a resistance R and is provided between the upper wiring layer and the lower wiring layer. The upper wiring 4 is connected to one end of the lower wiring 18 through the via 6, and the upper wiring 5 is connected to the lower wiring 18 through the via group 9 provided between the second wiring layer and the first wiring layer. Connected. Further, the lower wiring 18 is connected to the substrate 20 via a contact group 11 provided between the first wiring layer and the substrate 20.

  In the boundary region on the substrate 20 to which the contact group 11 and the substrate 20 are connected, a silicide layer 22 and a diffusion layer having the same conductivity type as the substrate 20 (here, P + diffusion layer 21) are formed in order from the upper layer. It is preferable. Since the contact group 11 is connected to the substrate 20 via the silicide layer 22 and the P + diffusion layer 21, the resistance between the contact group 11 and the substrate 20 can be reduced. Thereby, the resistance on the current path for measuring the via resistance can be reduced. Note that the effect of reducing the resistance is greater when the contact group 11 and the substrate 20 are connected via the silicide layer 22, but the installation of the silicide layer 22 may be omitted.

  Pads 1, 2, 3 and upper wirings 4, 5 (not shown) are provided in the same second wiring layer. The pad 1 is connected to the upper wiring 4 and functions as a current supply pad. The pad 2 is connected to the upper wiring 4 and functions as a pad for measuring the voltage at one end of the measurement target via 6. The pad 3 is connected to the upper wiring 5 and functions as a pad for measuring the voltage at the other end of the measurement target via 6.

  As described above, in the example shown in FIG. 6, a via chain in which one end is connected to the current source connecting pad 1 and the other end is connected to the substrate 20 is formed.

  Next, a method for measuring via resistance using the TEG pattern in this example will be described.

  Also in the example illustrated in FIG. 6, the probes 201 to 203 are brought into contact with the pads 1 to 3, respectively, as described above. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1, the probe 202 of the voltmeter 101 is brought into contact with the pad 2, and the probe 203 of the voltmeter 102 is brought into contact with the pad 3. A current I supplied from the current source 100 to the pad 1 passes through the upper wiring 14, the via 6, the lower wiring 18, the contact group 11, the silicide layer 22, and the P + diffusion layer 21 to reach the substrate 20 (via chain). ). At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

While the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Since the voltage at both ends of the via 6 is V1-V2, when the current value from the current source 100 is I, the resistance R of the via 6 is expressed by the equation (3).
R = (V1-V2) / I (3)

  As described above, by using the TEG pattern according to the present invention, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the via resistance with three probes.

  Similarly to the above, since the present invention has a structure that reduces the resistance between the substrate 20 and the contact group 11, it is possible to prevent the measurement voltages V1 and V2 from increasing.

  Next, a modified example of the TEG pattern shown in FIG. 6 will be described with reference to FIG. In the TEG pattern shown in FIG. 6, the contact resistance measurement pads are provided in the second wiring layer. However, the present invention is not limited to this, and may be provided in the first wiring layer. Referring to FIG. 7, the TEG pattern according to this example includes lower wirings 14 and 15, a measurement target contact 16, a contact group 19, and a substrate 20 on which a P + diffusion layer 21 and a silicide layer 22 are formed in the vicinity of the surface.

  The lower wirings 14 and 15 are formed in the same first wiring layer and are electrically isolated from each other by an element isolation region (not shown). The contact 16 has a resistance R and is provided between the substrate 20 and the lower wiring layer. The lower wiring 14 is connected to the substrate 20 via the contact 16, the silicide layer 22, and the P + diffusion layer 21, and the lower wiring 15 includes a contact group 19 and a silicide layer provided between the substrate 20 and the first wiring layer. 22 and the P + diffusion layer 21 are connected to the substrate 20.

  Pads 1, 2, 3 (not shown) are provided in the same first wiring layer as the lower wirings 14, 15. The pad 1 is connected to the lower wiring 14 and functions as a current supply pad. The pad 2 is connected to the lower wiring 14 and functions as a pad for measuring the voltage at one end of the measurement target contact 16. The pad 3 is connected to the lower wiring 15 and functions as a pad for measuring the voltage of the silicide layer 22 (P + diffusion layer 21) to which the other end of the contact 16 is connected. Here, in order to reduce the resistance between the voltage measuring pad 3 and the other end of the contact 16, it is preferable to set a large number of contacts in the contact group 19. This improves the voltage measurement accuracy, that is, the contact resistance measurement accuracy.

  As described above, in the example shown in FIG. 7, a via chain (contact chain) in which one end is connected to the current source connection pad 1 and the other end is connected to the substrate 20 is formed.

  Next, a method for measuring contact resistance using the TEG pattern in this example will be described.

  Also in the example shown in FIG. 7, the probes 201 to 203 are brought into contact with the pads 1 to 3, respectively, as described above. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1, the probe 202 of the voltmeter 101 is brought into contact with the pad 2, and the probe 203 of the voltmeter 102 is brought into contact with the pad 3. The current I supplied from the current source 100 to the pad 1 flows through a path (via chain) reaching the substrate 20 via the lower wiring 14, the contact 16, and the P + diffusion layer 21. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

  Similarly to the above, while the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Since the voltage at both ends of the contact 16 is V1−V2, when the current value from the current source 100 is I, the resistance R of the contact 16 is expressed by the equation (3).

  As described above, even when a pad is connected to the lower wiring layer, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the contact resistance with three probes.

  In the present invention, one end of the current path is connected to the substrate 20 so that measurement by the four-terminal method can be performed with three terminals (three probes). As a result, it is possible to reduce measurement efficiency and measurement cost when performing precise measurement of via resistance and contact resistance. Further, according to the present invention, the number of pads can be reduced, so that the area of the TEG pattern (test pattern) is reduced.

  In addition, since the connection resistance between the substrate and the contact is reduced by the connection via the P + diffusion layer or the silicide layer, the measurement voltage is lowered, and the measurement failure accompanying the increase in the measurement voltage can be prevented. Furthermore, by providing a plurality of vias and contacts on the current path in parallel, measurement failure due to contact failure can be prevented. That is, according to the present invention, it is possible to measure via resistance and contact resistance with high accuracy while reducing the measurement yield. In addition, since the current value for measurement is stable, measurement variation for each TEG pattern in the semiconductor wafer can be reduced.

  It is preferable that a capacitor for reducing noise with respect to the wiring is connected to the wiring to which the via to be measured is connected. For example, as shown in FIG. 8, vias 6 and 7 to be measured are connected, and a MOS (metal oxide semiconductor) capacitor 50 having one end grounded is connected to the lower wiring 8 which is a current path at the time of resistance measurement. Is done. FIG. 8 is a diagram showing a configuration example of a TEG pattern in which a MOS capacitor 50 is added to the TEG pattern shown in FIG.

  Referring to FIG. 8, lower wiring 8 is connected to MOS capacitor 50 via contact 49. The MOS capacitor 50 includes an oxide film 52 and a polysilicon gate 51 that are stacked in order from the lower layer on a P well 54 on the substrate 20. The P well 54 immediately below the oxide film 52 and the polysilicon gate 51 is surrounded by an element isolation region 53 (STI). Lower wiring 8 is connected to polysilicon gate 51 through contact 49. Other configurations are the same as those in FIG.

  When measuring the via resistance using the TEG pattern shown in FIG. 8, the probes 201 to 203 are brought into contact with the pads 1 to 3, respectively, as in FIG. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1 (upper wiring 4), the probe 202 of the voltmeter 101 is brought into contact with the pad 2 (upper wiring 4), and the probe of the voltmeter 102 is first contacted. 203 is brought into contact with the pad 3 (upper wiring 5). The current I supplied from the current source 100 to the pad 1 includes the upper wiring 4, the via 6, the lower wiring 8, the via 7, the upper wiring 5, the via group 9, the lower wiring 10, the contact group 11, the silicide layer 22, and the P + diffusion. It flows through a path (via chain) to the substrate 20 via the layer 21 and the P well 46. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

  While the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Assuming that the current value from the current source 100 is I, the resistance R of each of the vias 6 and 7 is expressed by the equation (2).

  As described above, by using the TEG pattern according to the present invention, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the via resistance with three probes.

  In the example shown in FIG. 8, the vias 6 and 7 to be measured are connected, and one end (polysilicon gate 51) of the MOS capacitor 50 is connected to the lower wiring 8 serving as a current path for resistance measurement. Since the other end of the MOS capacitor 50 is grounded via the P-well 46, noise with respect to the current I flowing through the lower wiring 8 can be reduced by the MOS capacitor 50. Thereby, resistance measurement with higher accuracy becomes possible.

  In the example shown in FIG. 8, the first via that connects the first wiring layer and the second wiring layer is the object of resistance measurement, but the present invention is not limited to this, and the second via that connects the second wiring layer and the third wiring layer. May be measured.

  FIG. 9 is a diagram showing an example of a structure of a TEG pattern in which the second via (vias 36 and 37) is a measurement target and a MOS capacitor is connected to the lower wiring.

  Referring to FIG. 9, the TEG pattern according to this example includes third wirings 34 and 35, measurement target vias 36 and 37, via group 39, second wirings 38 and 40, via groups 41 and 47, first wiring 42, 48, a contact group 43, and a substrate 20 on which a P + diffusion layer 45 and a silicide layer 44 are formed in the vicinity of the surface.

  The third wirings 34 and 35 are formed in the same third wiring layer (3Metal) and are electrically isolated from each other by an element isolation region (not shown). The first wirings 38 and 40 are formed in the same second wiring layer (2Metal) and are electrically isolated from each other by an element isolation region (not shown). Further, the first wirings 41 and 48 are formed in the same first wiring layer (1Metal) and are electrically isolated from each other by an element isolation region (not shown). Each of the vias 36 and 37 has a resistance R and is provided between the third wiring layer and the second wiring layer. The third wiring 34 is connected to one end of the second wiring 38 through the via 36, and one end of the third wiring 35 is connected to the other end of the second wiring 38 through the via 37. The other end of the third wiring 35 is connected to the second wiring 40 via a via group 39 provided between the third wiring layer and the second wiring layer. Further, the second wiring 40 is connected to the first wiring 42 via a via group 41 provided between the first wiring layer and the second wiring. The first wiring 42 is connected to the substrate 20 via a contact group 43 provided between the first wiring layer and the substrate 20.

  In the boundary region on the substrate 20 to which the contact group 43 and the substrate 20 are connected, a silicide layer 44 and a diffusion layer having the same conductivity type as the substrate 20 (here, P + diffusion layer 45) are formed in order from the upper layer. It is preferable. Here, the P + diffusion layer 45 is formed on the P well 41 formed on the substrate 20. Since the contact group 43 is connected to the substrate 20 via the silicide layer 44 and the P + diffusion layer 45, the resistance between the contact group 43 and the substrate 20 can be reduced. Thereby, the resistance on the current path for measuring the via resistance can be reduced. Note that the resistance reduction effect is greater when the contact group 43 and the substrate 20 are connected via the silicide layer 44, but the silicide layer 44 may be omitted.

  Referring to FIG. 9, the second wiring 38 is connected to the MOS capacitor 50 through the via group 47, the first wiring 48 and the contact 49. The MOS capacitor 50 includes an oxide film 52 and a polysilicon gate 51 that are stacked in order from the lower layer on a P well 54 on the substrate 20. The P well 54 immediately below the oxide film 52 and the polysilicon gate 51 is surrounded by an element isolation region 53 (STI). Lower wiring 8 is connected to polysilicon gate 51 through contact 49.

  When the via resistance is measured using the TEG pattern shown in FIG. 9, the probes 201 to 203 are brought into contact with the pads 1 to 3 provided in the third wiring layer, respectively. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1 (third wiring 34), the probe 202 of the voltmeter 101 is brought into contact with the pad 2 (third wiring 34), and the voltmeter 102 The probe 203 is brought into contact with the pad 3 (third wiring 35). The current I supplied from the current source 100 to the pad 1 includes the third wiring 34, the via 36, the second wiring 38, the via 37, the third wiring 35, the via group 39, the second wiring 40, the via group 41, and the first wiring. It flows through a path (via chain) to the substrate 20 via the wiring 42, the contact group 43, the silicide layer 44, the P + diffusion layer 21 and the P well 46. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

  While the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Assuming that the current value from the current source 100 is I, the resistance R of each of the vias 6 and 7 is expressed by the equation (2).

  As described above, by using the TEG pattern according to the present invention, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the via resistance with three probes.

  In the example shown in FIG. 9, the vias 36 and 37 to be measured are connected, and one end (polysilicon gate 51) of the MOS capacitor 50 is connected to the second wiring 38 serving as a current path for resistance measurement. . Since the other end of the MOS capacitor 50 is grounded via the P-well 46, noise with respect to the current I flowing through the second wiring 38 can be reduced by the MOS capacitor 50. Thereby, resistance measurement with higher accuracy becomes possible.

  Next, in the TEG pattern shown in FIG. 8, a TEG pattern for measuring via resistance using a pad connected to an upper layer (third wiring layer: 3 metal) of the upper wiring layer (second wiring layer: 2 metal). The structure will be described with reference to FIG.

  When using a pad connected to the third wiring layer, a via resistance measurement via chain including the contacts 6 and 7 is preferably formed so as to pass through the third wiring layer via a plurality of vias. . Specifically, the pads 1 and 2 (not shown) for the short hands 201 and 202 are connected to the third wiring 65 formed in the third wiring layer. A pad 3 (not shown) for the short hand 203 is connected to a third wiring 67 formed in the third wiring layer. The third wiring 65 is connected to the upper layer wiring (second wiring) 4 through the via group 66. On the other hand, the third wiring 67 is connected to the via 7 via the via group 68 and the second wiring 70 formed in the second wiring layer, and is connected to the upper wiring (second wiring) 5 via the via group 69. Connected. Here, in the second wiring layer, the second wiring 5 and the second wiring 70 are electrically separated. As a result, one end of the via 7 is grounded via the third wiring 67. That is, the current path (via chain) for measuring the resistance of the vias 6 and 7 is grounded via the third wiring 67.

  In the example shown in FIG. 10, one end of the MOS capacitor 50 is connected to the substrate 20 and thus grounded, and the other end (polysilicon gate 51) is connected to the first wiring 8 and the second wiring 70. Thereby, the MOS capacitor 50 is charged in the step of forming the second wiring layer (2metal). As a result, a formation defect may occur in a part of the via group 68 due to the positive charge supplied to the second wiring.

  However, by setting a large number of vias constituting the via group 68, the amount of decrease in resistance measurement accuracy due to poor formation of vias can be reduced. Further, the second wiring 70 and the second wiring 5 are separated in the same layer and are electrically connected via the third wiring 67. In this case, since the area of the second wiring and the third wiring facing each other can be made smaller than the case where the second wiring 70 and the second wiring 5 are integrated, the size of the parasitic capacitance therebetween is also small. it can. As a result, the measurement accuracy of via resistance can be improved.

  In the example shown in FIGS. 8 to 10, the configuration in which the MOS capacitor is connected to the lower wiring is described. However, the present invention is not limited to this, and a PIP (polysilicon insulator polysilicon) capacitor may be connected. For example, as shown in FIG. 11, the vias 6 and 7 to be measured are connected, and are provided below the lower wiring layer between the lower wiring 8 and the upper wiring 5 which are current paths at the time of resistance measurement. The specified PIP capacity 60 is connected. FIG. 11 is a diagram showing a configuration example of a TEG pattern in which a PIP capacity 60 is added to the TEG pattern shown in FIG.

  Referring to FIG. 11, lower wiring 8 is connected to one end of PIP capacitor 60 through contact 49. The other end of the PIP capacitor 60 is connected to the upper wiring 5 via a contact 56, a lower wiring 55 and a via group 54. The PIP capacitor 60 includes an element isolation region 64 (STI), a polysilicon layer 63, an oxide film 62, and a polysilicon layer 61, which are sequentially stacked on a P well 64 on the substrate 20 from the lower layer. The lower wiring 55 is provided in the first wiring layer, is connected to the upper wiring 5 through the via group 54, and is connected to the polysilicon layer 63 through the contact 56. Other configurations are the same as those in FIG.

  When the via resistance is measured using the TEG pattern shown in FIG. 11, the probes 201 to 203 are brought into contact with the pads 1 to 3, respectively, as in FIG. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1 (upper wiring 4), the probe 202 of the voltmeter 101 is brought into contact with the pad 2 (upper wiring 4), and the probe of the voltmeter 102 is first contacted. 203 is brought into contact with the pad 3 (upper wiring 5). The current I supplied from the current source 100 to the pad 1 includes the upper wiring 4, the via 6, the lower wiring 8, the via 7, the upper wiring 5, the via group 9, the lower wiring 10, the contact group 11, the silicide layer 22, and the P + diffusion. It flows through a path (via chain) to the substrate 20 via the layer 21 and the P well 46. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

  While the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Assuming that the current value from the current source 100 is I, the resistance R of each of the vias 6 and 7 is expressed by the equation (2).

  As described above, by using the TEG pattern according to the present invention, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the via resistance with three probes.

  In the example shown in FIG. 11, the vias 6 and 7 to be measured are connected, and one end (polysilicon layer 61) of the PIP capacitor 60 is connected to the lower wiring 8 serving as a current path for resistance measurement. The other end (polysilicon layer 63) of the PIP capacitor 60 is grounded by being connected to the substrate 20 via the lower wiring 55 and the upper wiring 5. For this reason, the noise with respect to the electric current I which flows through the lower wiring 8 can be reduced by the PIP capacitor | condenser 60, and a more accurate resistance measurement is attained.

  In the example shown in FIG. 11, one end (polysilicon layer 63) of the PIP capacitor 60 is grounded via the lower wiring 55 and the upper wiring 5. At this time, the lower wiring 55 is electrically separated in the same layer as the grounded lower wiring 10. That is, one end (polysilicon layer 63) of the PIP capacitor 60 is grounded via the upper wiring 5. Thereby, in the process of forming the lower wiring layer (1 metal), both ends (polysilicon layers 61 and 62) of the PIP capacitor 60 connected to the lower wirings 8 and 55 are at the same potential, and the charging operation to the PIP capacitor 60 is performed. Can be prevented.

  On the other hand, as shown in FIG. 12, one end (polysilicon layer 61) of the PIP capacitor 60 is connected to the lower wiring 8, and the other end (polysilicon layer 63) is connected to the grounded lower wiring 10. In this case, in the process of forming the lower wiring layer (1 metal), the PIP capacitor 60 is charged by the applied voltage when the lower wiring 8 is formed. In this case, in the first via formation process, the formation of the vias 7 and 6 occurs due to the supply of electric charge from the charged PIP capacitor 60. According to the structure shown in this example, charging to the PIP capacitor 60 as described above can be prevented, so that formation failure of vias can be prevented.

  In the example shown in FIG. 11, the first via that connects the first wiring layer and the second wiring layer is the object of resistance measurement. However, the present invention is not limited to this, and the second via that connects the second wiring layer and the third wiring layer. May be measured.

  FIG. 13 is a diagram illustrating an example of a structure of a TEG pattern in which the second via (vias 36 and 37) is a measurement target and a PIP capacitor is connected to the lower wiring.

  Referring to FIG. 13, the TEG pattern according to this example includes third wirings 34 and 35, measurement target vias 36 and 37, via group 39, second wirings 38 and 40, via groups 41 and 47, first wiring 42, 48, a contact group 43, and a substrate 20 on which a P + diffusion layer 45 and a silicide layer 44 are formed in the vicinity of the surface.

  The third wirings 34 and 35 are formed in the same third wiring layer (3Metal) and are electrically isolated from each other by an element isolation region (not shown). The first wirings 38 and 40 are formed in the same second wiring layer (2Metal) and are electrically isolated from each other by an element isolation region (not shown). Further, the first wirings 41 and 48 are formed in the same first wiring layer (1Metal) and are electrically isolated from each other by an element isolation region (not shown). Each of the vias 36 and 37 has a resistance R and is provided between the third wiring layer and the second wiring layer. The third wiring 34 is connected to one end of the second wiring 38 through the via 36, and one end of the third wiring 35 is connected to the other end of the second wiring 38 through the via 37. The other end of the third wiring 35 is connected to the second wiring 40 via a via group 39 provided between the third wiring layer and the second wiring layer. Further, the second wiring 40 is connected to the first wiring 42 via a via group 41 provided between the first wiring layer and the second wiring. The first wiring 42 is connected to the substrate 20 via a contact group 43 provided between the first wiring layer and the substrate 20.

  In the boundary region on the substrate 20 to which the contact group 43 and the substrate 20 are connected, a silicide layer 44 and a diffusion layer having the same conductivity type as the substrate 20 (here, P + diffusion layer 45) are formed in order from the upper layer. It is preferable. Here, the P + diffusion layer 45 is formed on the P well 41 formed on the substrate 20. Since the contact group 43 is connected to the substrate 20 via the silicide layer 44 and the P + diffusion layer 45, the resistance between the contact group 43 and the substrate 20 can be reduced. Thereby, the resistance on the current path for measuring the via resistance can be reduced. Note that the resistance reduction effect is greater when the contact group 43 and the substrate 20 are connected via the silicide layer 44, but the silicide layer 44 may be omitted.

  Referring to FIG. 13, second wiring 38 is connected to one end of PIP capacitor 60 through contact 49. The other end of the PIP capacitor 60 is connected to the second wiring 35 through the contact 56, the first wiring 55, and the via group 54. The PIP capacitor 60 includes an element isolation region 64 (STI), a polysilicon layer 63, an oxide film 62, and a polysilicon layer 61, which are sequentially stacked on a P well 64 on the substrate 20 from the lower layer. The first wiring 55 is provided in the first wiring layer, connected to the second wiring 35 through the via group 54, and connected to the polysilicon layer 63 through the contact 56.

  When measuring the via resistance using the TEG pattern shown in FIG. 13, the probes 201 to 203 are brought into contact with the pads 1 to 3 provided in the third wiring layer, respectively. Specifically, first, the probe 201 of the current source 100 is brought into contact with the pad 1 (third wiring 34), the probe 202 of the voltmeter 101 is brought into contact with the pad 2 (third wiring 34), and the voltmeter 102 The probe 203 is brought into contact with the pad 3 (third wiring 35). The current I supplied from the current source 100 to the pad 1 includes the third wiring 34, the via 36, the second wiring 38, the via 37, the third wiring 35, the via group 39, the second wiring 40, the via group 41, and the first wiring. It flows through a path (via chain) to the substrate 20 via the wiring 42, the contact group 43, the silicide layer 44, the P + diffusion layer 21 and the P well 46. At this time, since the substrate 20 is grounded, a pad and a probe for grounding are not required as in the prior art.

  While the current is supplied from the probe 201, the voltages V1 and V2 of the pads 2 and 3 are measured via the probes 202 and 203. Assuming that the current value from the current source 100 is I, the resistance R of each of the vias 6 and 7 is expressed by the equation (2).

  As described above, by using the TEG pattern according to the present invention, resistance measurement by the four-probe method can be performed with three probes. That is, according to the present invention, it is possible to accurately measure the via resistance with three probes.

  In the example shown in FIG. 13, the vias 36 and 37 to be measured are connected, and one end (polysilicon layer 61) of the PIP capacitor 60 is connected to the second wiring 38 serving as a current path for resistance measurement. . The other end (polysilicon layer 63) of the PIP capacitor 60 is grounded by being connected to the substrate 20 via the first wiring 55 and the second wiring 40. For this reason, noise with respect to the current I flowing through the second wiring 38 can be reduced by the PIP capacitor 60, and resistance measurement with higher accuracy can be performed.

  One end (polysilicon layer 63) of the PIP capacitor 60 is grounded via the first wiring 55 and the second wiring 40. At this time, the first wiring 55 is electrically separated in the same layer as the grounded first wiring 42. That is, one end (polysilicon layer 63) of the PIP capacitor 60 is grounded via the second wiring 40. Thereby, in the process of forming the first wiring layer (1 metal), both ends (polysilicon layers 61 and 62) of the PIP capacitor 60 connected to the first wirings 48 and 55 have the same potential, Charging operation can be prevented. Accordingly, even in this example, the formation failure of the via as described above can be prevented.

  Various elements are formed on the chip, and it is preferable that a TEG pattern having a shape corresponding to each element is formed on the chip. The example shown in FIGS. 8 to 13 can be formed as a TEG pattern corresponding to an element having a wiring with a capacitor.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. . In this embodiment, the measurement of the via resistance has been described in detail, but it goes without saying that the present invention can also be applied to the measurement of contact resistance and wiring resistance. In addition, although a via and a contact were distinguished and demonstrated as the above-mentioned resistance measurement object, it is substantially the same as a component which connects between wiring.

1-3: Pads 101, 102: Voltmeter 100: Current source 201-203: Probe 4, 5: Upper wiring 8, 10, 14, 15, 18: Lower wiring 6, 7, 37, 38: Via 9: Via group 11, 19: Contact group 16, 17: Contact 20: Substrate 21: P + diffusion layer 22: Silicide layer 50: MOS capacitor 60: PIP capacitor

Claims (10)

A first pad for connecting a current source;
A via chain having one end connected to the first pad and the other end connected to the substrate via a diffusion layer of the same conductivity type as the substrate;
A second pad and a third pad for voltage measurement,
The via chain is
A first wiring to which the first pad and the second pad are connected;
One end is connected to the first wiring, and the other end is connected to the third pad.
In a state where a current flows from the first pad to the substrate through the via chain, the resistance of the resistance measurement target is measured by a voltage value measured through the second pad and the third pad. Semiconductor device. The semiconductor device according to claim 1,
The via chain has one end connected to the first wiring, the other end connected to a second wiring provided in a lower layer of the first wiring, and one end connected to the second wiring. A second via connected to the third wiring provided on the same layer as the first wiring, and a plurality of contacts connecting the third wiring and the substrate via the diffusion layer And
The third pad is connected to the third wiring;
In a state where a current flows from the first pad to the substrate through the via chain, a voltage value measured through the second pad and the third pad is used to determine the first via and the second via. A semiconductor device whose resistance is measured. The semiconductor device according to claim 2,
A semiconductor device further comprising a capacitive element having one end connected to the second wiring and the other end grounded. The semiconductor device according to claim 3.
The capacitor element is a metal oxide semiconductor (MOS) capacitor including an oxide film formed on the substrate and a polysilicon layer connected to the second wiring. The semiconductor device according to claim 3.
The capacitive element is provided below the second wiring, and has one end connected to the third wiring through a fourth wiring electrically separated from the second wiring in the same wiring layer, and the other end A semiconductor device having a PIP (polysilicon insulator polysilicon) capacitance connected to the second wiring. The semiconductor device according to any one of claims 2 to 5,
The second wiring is formed by a silicide layer provided on the substrate. The semiconductor device according to claim 1,
The via chain has one end connected to the first wiring and the other end connected to a second wiring provided in a lower layer of the first wiring and the first via via the diffusion layer. A plurality of contacts for connecting two wirings and the substrate;
The third pad is connected to the second wiring through a plurality of vias,
When a current flows from the first pad to the substrate through the via chain, the resistance of the first via is measured by a voltage value measured through the second pad and the third pad. Semiconductor device. The semiconductor device according to claim 7,
The second wiring is formed by a silicide layer provided on the substrate. The semiconductor device according to any one of claims 2 to 8,
The contact is connected to the substrate via a silicide layer provided on the diffusion layer. Passing a current from the first pad to the substrate;
The current flows through a path from the first pad to the substrate via a via or contact to be measured for resistance and a diffusion layer provided on the substrate.
The diffusion layer has the same conductivity type as the substrate,
Measuring a first voltage of a second pad provided on the first wiring provided with the first pad;
Measuring a second voltage of a third pad provided on a second wiring connected to the first wiring via the resistance measurement object;
A resistance measurement method comprising: calculating a resistance value of the resistance measurement object using measured values of the magnitude of the current, the first voltage, and the second voltage.

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