JPS6148927A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate inspection of articles to be inspected using a tester and so forth by allowing electrical detection of an effective channel length, a gate length and difference in alignment between its gate mask and its diffusion mask from resistances of its diffusion layer and its gate material of a same MOS-type transistor. CONSTITUTION:A measuring pattern is provided, which has current conduction electrodes 10 and 11 and voltage measuring terminals 17 and 18 for measuring voltage drops across both terminals of the electrodes disposed at respective both ends of a source diffusion region 26, a drain diffusion region 27 and a gate material member 24 constituting a MOS transistor. A measuring pattern is, also, provided, which has current conduction terminals 30 and 31 and voltage measuring terminals 33 and 34 disposed at both ends of a diffusion region all over the surface 37 formed by introducing the same diffusion seed with the same area as the MOS transistor all over its surface. Electrode patterns for measuring layer resistance are provided, extending them to the gate material member 24 and the diffusion layer all over the surface 37.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a method for evaluating the characteristics of MOS transistors formed as individual semiconductor elements or MOS transistors built into an MO5 type large-scale integrated circuit (LSI). The present invention relates to a semiconductor device having additional means.

Conventional Structures and Problems The miniaturization of large-scale integrated circuits has progressed, and Mo8 transistors having gate lengths of 2 to 3 μm or less have been integrated. As the gate length becomes shorter, a short channel effect occurs, making it difficult to set the threshold voltage.

In order to maintain a high manufacturing yield in such large-scale integrated circuits, it is necessary to maintain the gate length dimension after all manufacturing steps, the effective channel length after subtracting the lateral diffusion spread of the source/ton-in diffusion layer, the gate mask and diffusion. It is necessary to understand misalignment with the area mask.

FIG. 1 shows the principle of a conventional example in which the effective channel length is determined from the characteristics of a Mo5 transistor. The explanation of Figure 1 is given in the literature by JiG, J, CHE/RN et al.
ELli:CTR0N DEv Engineering CE LETTER5
VOL, EDL-1, Shiri 9 1980).

From the IV characteristics in the linear region of the MoS transistor, the drain current Id and drain resistance R0 are as follows.

Here, d drain source current vd drain source voltage v9 dual gate source voltage vt: gate threshold voltage μ: Mobility of carrier in channel Every time COx: Gate oxide film capacitance Le: Effective channel length Wo: Effective channel width Rc: Channel resistance It is.

Furthermore, the drain resistance RT measured from W,:WM-ΔWL,==Ly-ΔLR=R,+Ro! 1 is Rm = R, 10A (LM - ΔL) Person = (μCox Wa (Vg -Vt -
Base v(1)11-'...Equation (1) where WM: Channel width on mask LM: -7
, < channel length ΔW = WM −Wo ΔL2LM −L.

Re: external resistance It is.

Effective channel length. In order to obtain , use the relationship in equation (1). Measured drain resistance Rm and channel/channel length on mask 1. The relationship with M is the drain resistance Rm measured during the proboscis. The slopes of the straight line t, b, and a are
It can be changed arbitrarily by changing the gate-source voltage vq in equation (1).

When the slope is changed as shown in a, b, and c, and the drain-source voltage Vd is constant, the point (ΔLp ``e ) is found as an intersection point. Once ΔL is found, the effective channel length Lθ is determined by the dimension LM on the mask. It can be obtained from Le=LM-ΔL.

As described above, according to the conventional method, the effective channel length Le
must be determined indirectly from several transistor characteristics. Therefore, it is not easy to automate measurements using a tester or the like during the manufacturing process.

Further, as a more direct measurement method than this method, there is a method using scanning electron microscopy.

With this method, the diffusion layer and gate length dimensions can be directly and accurately measured, but the sample must be deconcentrated for measurement.

In addition, prior to measurement, it is necessary to accurately locate a specific location on the sample and then perform etching on this area. It is difficult to do. As described above, the conventional measurement method has a problem that makes it difficult to adopt it in the production of semiconductor devices.

Furthermore, in the conventional method, it has been impossible to detect the gate length dimension and the misalignment between the gate mask and the mask of the diffusion region from the same transistor.

OBJECTS OF THE INVENTION An object of the present invention is to electrically detect the effective channel length, gate length dimension, and misalignment between the gate mask and the diffusion mask from the resistance of the diffusion layer and the resistance of the gate material of the same MO3 type transistor. The present invention provides a semiconductor device that can be easily tested using an inspection device such as a tester.

Structure of the Invention The semiconductor device of the present invention electrically measures the effective channel length, gate length, and misalignment between the gate mask and the diffusion region mask in the same MO5 transistor. source diffusion region,
A measurement pattern with a current-carrying electrode and a voltage measurement terminal for measuring the voltage drop that occurs between both ends of the drain diffusion region and the gate material, and a measurement pattern with the same area and the same pattern. A measurement pattern with current carrying terminals and voltage measurement terminals attached to both ends of the diffusion region of the diffusion species, that is, the diffusion region in which the source/drain diffusion layer is formed all over the bottom of the gate part, and the gate 7-17 for measuring the material and layer resistance of the diffusion layer. It is composed of a Van da Pauw pattern.

DESCRIPTION OF EMBODIMENTS FIGS. 2(&) and 2(b) are a pattern plan view and a side sectional view of a main part of a semiconductor device for explaining the principle of the dimension measuring method of the present invention. Two defined regions 2 and 3 having the same shape with a length W and widths D' and LD, respectively, are formed on a semiconductor substrate 1, separated by a thick fused film at the periphery. Area 3
A gate oxide film is formed on and a gate material 4 having the length of the gate is arranged. Then, in the region 2, a diffusion layer 5 is directly formed, and in the region 3, a self-aligned leta-source T-drain diffusion layer 6, 7, respectively. When the source and drain diffusion layers 6.7 are self-lined using only the gate material 4, laterally inward expanding portions 8 of the diffusion layers are formed on both sides with a length Δl/2.

Therefore, the effective channel length LE in this case is L E:L −Δ β
On the other hand, the distance L between both ends of the source and drain/diffusion layers 6 and 7 is expressed by (2)
D is the width LD of the diffusion layer 5 when the diffusion layer is formed on the entire surface
Since it is equivalent to ', LD': LD is reached. The diffusion layer width of the source and drain diffusion layers 6 and 7 is L
If l and L2, then effective channel length LE is LE==LD
-(Ll +L2) =LD'-(L1+L2) ......(3
), and the effective channel length is LD', Lj,
Calculations can be made by measuring the width of each diffusion layer of L2. These are the layer resistance Rs of the diffusion layer, the resistance value R(n) at both ends of each diffusion layer 5, 6.7, and the diffusion layer length W to L(n) = Rs W / R(n)
--Represented by (4). However, n is the diffusion layer 5
, 6.7.

Next, the mask misalignment between region 3 and gate 4, ΔM, is ΔM=L1-L2 It can be derived from

The gate length is determined by the resistance value at both ends of gate 4 and gate 4.
It is determined from the sheet resistance Rs using equation (4).

Next, an example of a pattern actually implemented based on the above principle will be explained using FIG. 3.

Region 3 and gate 4 in the principle diagram of FIG. 2 correspond to region 25 and gate 24 in FIG. 3.

Region 2 in the principle diagram of FIG. 2 corresponds to region 37 in FIG. 3. 8 - The widths of the region 37 and the region 37 are made equal in the mask, and LD1=LD2
shall be.

10.11, 1, and 18 are electrodes attached to the gate material 24, and are used to determine the sheet resistance R8° of the gate material 24. "FISG: Constant current vR applied between electrodes 10.11
AG: When the voltage is measured between the electrodes 17 and 18, the layer resistance Rsc of the gate material 24 is π.

Similarly, 30, 31, 33, 34 are electrodes attached to the diffusion region 37, and the layer resistance R of the diffusion layers 38, 26°27
50, and "RAD: Electrode 30
, 31, a constant current v0. : If the measured voltage is between 33 and 34, the diffusion layer resistance R0 reaches π.

Electrodes 1.1, '16,19, 2.3 are gate material 2
4, and the gate length L of the gate material 24
It is used to electrically determine , and is an engineering method. L: Electrode 1
1. Constant current v, L applied between electrodes 19 and 23: Voltage W3 measured between electrodes 19 and 23: Gate material 24
The gate length is LG= Rs, x W3 x IGL/V, L-0-
It is expressed as (6).

The electrodes 31, 32, 35, 36 are electrodes attached to the diffusion region 37, and are used to determine the diffusion layer width LD of the diffusion layer 38. DL: constant voltage applied between the electrodes 31, 32 Current vDL
: Voltage W2 measured between electrodes 35.36: Electrodes 35.36.
If 36 is the distance between the electrodes that are in direct contact with the diffusion region 37, then the diffusion layer width LD of the diffusion layer 38 is L D = R
, Dx W2 X IDL/VDL.

The electrodes 12, 13, 14, and 15 are electrodes attached to one diffusion layer 27 in the region 25, and are used to determine the diffusion layer width L1 of the diffusion layer 27, and "+o, +: electrode 1
Constant current vDX applied between 2.16 and : electrodes 13.1
Voltage W1 measured between the electrodes 13 and 14 is the distance between the electrodes where they are in direct contact with the diffusion layer 27, then the diffusion H width L1 of the diffusion layer 27 is L 1 '' R
2OX W I X IDI, + / VDL.

It is expressed as

The electrodes 20, 21, 22, 15 are electrodes attached to the other diffusion layer 26 in the region 26, and the diffusion layer @ of the diffusion layer 26 is
This is for finding L2, so I,2: Electrode 2
Constant current vILL□ applied between 0.15: electrodes 21, 2
Voltage W1 measured between 2: the distance between the electrodes 21 and 22 in direct contact with the diffusion layer 26, the diffusion layer width L2 of the diffusion layer 26 is L 2 = R
It is expressed as sD X W 1 X Xot, 2 / VDL2, and the effective channel length LX is L
+L2) = Rs D X (W2 X I(I L / vob
w"+ X 101.+/ V'o!, + -Wl X
IDI, 2/VDL2) (6).

The mask misalignment ΔM between the region 26 and the gate 24 is as follows: ΔM==L1-L2=WIX("+st,+/vt+t,+-"
It can be expressed as DL2/vIIL2:)・−(7).

As mentioned above, in the same transistor structure, the gate length, effective channel length LE, and misalignment ΔM between the diffusion region mask and the gate mask are (6), respectively.
It can be seen that it can be expressed by equations (6) and (7).

As described in detail, the measurements of the effective channel length, gate length, and diffusion/gate mask misalignment according to the present invention are performed in the same structure as the MOS transistor.

The obtained value has a more direct meaning.

Moreover, since it can be electrically expressed using a simpler equation, it is possible to automatically perform a large number of inspections of semiconductor manufacturing process conditions. That is, regarding the derivation of the effective channel length, it is possible to obtain the effective channel length using a simple method without having to prepare a number of mask design values as in the conventional equation (1). Furthermore, it is unprecedented that not only the effective channel length but also the mask misalignment and gate length measurements can be derived from patterns of the same structure. Furthermore, since this method is a non-destructive method, it has the advantage of imposing restrictions on the measurement sample.

[Brief explanation of drawings]

Figure 1 shows the effective channel length of a MOS transistor.
Figures 2 (2L) and (b), which are diagrams for explaining the conventional measurement method for determining dimensions from an S transistor, are schematic diagrams of a MOS transistor structure shown to illustrate the principle of the dimension measurement method of the present invention. A plan view and a sectional view, and FIG. 3 is a plan view showing a pattern structure and an electrode structure that enable the dimension measuring method of the present invention. 1... Semiconductor substrate, 2, 3, 25, 3...
...area% 't 6rte, 2te, 26.38...
... Diffusion layer, 4.24 ... Gate material, 8.
... Laterally expanding portion of the diffusion layer, 10, 11.1
7.18...Foundation and pow pattern electrode for determining layer resistance of gate material, 11.16, 19, 2
3... Electrode for gate length measurement, j 2 to 15
, 20 P-22, 31, 32゜35.36...
・Electrode for measuring the width of the diffusion layer, 30° 31.33.34...
... Fan, de, and bo electrodes for measuring diffusion layer resistance. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure L Mask 2 channel length M Figure 2 Figure 3

Claims (1)

[Claims] A measurement method in which current-carrying electrodes are attached to both ends of each of the source diffusion region, drain diffusion region, and gate material that constitute a MOS transistor, and voltage measurement terminals are attached to measure the voltage drop that occurs between the two ends. a measurement pattern having the same area as the MOS transistor and having a current carrying terminal and a voltage measuring terminal attached to both ends of an entire diffusion region formed by introducing the same diffusion species over the entire surface; A semiconductor device including electrode patterns for layer resistance measurement extending to the gate material portion and the entire diffusion region.