JP2000111617A - Multichip module and test method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MCM having a structure capable of reliably specifying a failure chip in a multichip module(MCM) and specifying a position of a failure place, and a test method therefor. SOLUTION: In an MCM M1 by highly densely mounting plural bare chips on a multichip board having a thin film wiring layer, supply means P1 to P4 are arranged to individually supply a power source to the whole bare chips on the multichip board. In this MCM M1, a test is performed by successively repeating a procedure of supplying the power source to only a testing object bare chip among plural bare chips and of not supplying the power source to the other bare chips by changing the testing object bare chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a configuration for accurately performing a test such as a standby chip measurement, an in-circuit test, and a leak measurement necessary for detecting a defective chip, and checking whether a conductor wiring pattern is open. The present invention relates to a multi-chip module (MCM) and a test method thereof.

[0002]

2. Description of the Related Art An LSI or VLSI package includes a normal package having one chip. Semiconductor circuit devices connected by printed wiring using a plurality of normal packages have been known for a long time. In such a semiconductor circuit device using a normal package (hereinafter, referred to as a normal package circuit), there is a problem that a signal delay due to a wiring distance between chips is large, and high speed operation is hindered.
In order to improve this, in recent years, the development of a multichip module in which a thin film wiring layer is formed on a base substrate and a plurality of bare chips are connected to increase the density has been rapidly progressing. The present invention relates to this multi-chip module.
In a normal package circuit, a chip package to be used is one whose normal chip has been tested and whose non-defective product is guaranteed. Therefore, testing of the chip itself,
For example, a standby current measurement is not usually required in a package circuit. On the other hand, in a multi-chip module, the bare chip to be mounted is generally not guaranteed to be good. Therefore, for example, a standby current measurement useful for determining the quality of a mounted bare chip is essential. As described above, the normal package circuit and the multi-chip module have different aspects, so that the multi-chip module has a specific problem different from that of the normal package circuit. The prior art and its problems will be described in more detail below.

Conventionally, in a normal package mounted on a printed circuit board, in an in-circuit test on the printed circuit board, a resistance element or the like is added in order to perform component isolation (for example, Japanese Patent Application Laid-Open No. 3-213).
000 publication). In a conventional package mounted on a printed circuit board, a control signal is connected to a component under test from another component on the same board as a conventional technique which is improved so that the addition of the above-described resistance element or the like is not required. A method has been proposed in which a separate power supply is provided to logically cut off this control signal by providing a separate power supply source for a component under test that cannot be logically separated in the case where the component is logically separated (for example, Japanese Unexamined Patent Publication No.
159728).

[0004] Compared with the above-mentioned normal package circuit, a DC test and a function test similar to those of the above-described normal package circuit are performed on the multi-chip module, and a test data when a failure inside the chip is determined to be defective by the test. Is analyzed to identify the faulty chip. Generally, a multi-chip module substrate has a power supply plane layer inside and supplies each bare chip as a common power supply. Therefore, in the standby current measurement, the total current value of each bare chip is obtained, and good / bad judgment is made.

[0005]

The conventional example of a normal package mounted on a printed circuit board (Japanese Unexamined Patent Publication No. 9-159)
728), as illustrated in FIG.
When power is supplied only from the power supply source P12, the package components PKG1 and PKG2 can operate, and the package components PKG3 and PKG4 do not operate. Therefore, although physically connected, the package components PKG3 and PKG4 are logically separated, so that the package components PKG1 and PKG2 are separated from the package component PKG.
3. A test for comparing expected values using test data without being affected by PKG4 can be reliably performed. The same operation as described above is performed when power is supplied only from the power supply source P34. However, two measured values of the power supply source P12 and the power supply source P34 are obtained as the standby current measured values. When a failure value indicating a failure is returned, both of the two power supply sources P12 and P34 have two measured values. Since power is supplied to the chip components, it cannot be determined which chip component is defective. Subsequently, even if the insert kit test is performed, the use test data does not access the failed part, and the failure detection rate is insufficient, and the input / output voltage levels (VIL, VIH, V0L, VO) during the in-circuit test
In the case of a failure that does not affect H), it is not possible to specify a failed chip with respect to the fail value detected by the standby current measurement.

The normal package mounted on the printed circuit board is basically guaranteed to be non-defective. That is, the purpose of performing the in-circuit test is mainly to detect a mounting defect. Generally, a test point is provided on a printed circuit board, and a prober dedicated to the package under test is used.
Perform an in-circuit test with the package pins directly accessible. Therefore, a defective package can be directly detected. That is, here the DC measurement has no significant significance.

On the other hand, in a multi-chip module, unlike a normal package mounted on the printed circuit board, a DC test is an important test item. The reasons are as follows. KGB (Known Good Die)
There is a case where bare chips are not guaranteed.
For this reason, a standby current measurement for detecting a failure inside the bare chip with a high probability is essential. 2. In addition to the demand for smaller packages, the number of bonding wires is generally large. For this reason, there is a high possibility that the wire portion is defective (open / short). Therefore, a resistive short between pins that cannot be detected by the function test (input leak, HI
Z leak measurement).

However, when the wiring and the measurement system in the multi-chip module board are configured in a structure in which a plurality of chips use a single power supply as in the related art, it is not possible to specify the faulty chip only by measuring the standby current. In addition to being possible, the tester may not detect a failed multi-chip module to determine pass / fail (PASS / FAIL) based on the total standby current value of a plurality of chips. The standby current measurement is a method of measuring a power / voltage leak value and determining a failure of a CMOS device in a state where all parts such as input / output pins, internal logic, and memory are not operated. FIG. 7 shows two chip components C.
A conventional example in which the standby currents of C1 and C2 are measured by one power supply source 5 will be described. PASS value of each chip component is 10μ
A and the combined PASS value is 20 μA or less,
If the value obtained from the current measuring device 4 is 25 μA, a defective result can be obtained, but since the individual standby current of the chip C1 or C2 cannot be measured, it is not known which chip is defective. Further, the value obtained from the current measuring device 4 is 1
When 8 μA is set, it is determined that the multi-chip module is a non-defective product, but the standby current from the chip C1 is 2 μA.
At A, when the standby current of the chip C2 is 16 μA, the chip C2 as a single chip exceeds 10 μA, and thus is defective. However, since the standby current of each chip is not measured, this individual failure cannot be detected.

[0009] Further, it is difficult to specify a defective portion even in an inter-pin resistive short-circuit test and a pin-by-pin leak test of a net having a plurality of pins (pads) in a substrate of a multi-chip module. The inter-pin resistive short-circuit test and the inter-pin single leak test are to apply a voltage to floating pins of the input buffer and the tri-state buffer to measure a leak current. At this time, a test pattern is applied to all the remaining pins in order to detect a resistive short between the pins. The measurement of the leak current is sequentially performed for each pin.

FIG. 9 shows a conventional example of a multi-chip module in which a single power supply 15 performs a leak test on a net having a plurality of pins. The leak measurement is performed in the order of the pin number 12. At this time, outer leads (not shown)
If the pin of the bare chip corresponds to the pin of the bare chip, the faulty pin becomes clear. However, when connected to the input pins 1 of the bare chips C1 and C2 as in the case of the net 10, the faulty pin cannot be specified. That is, PA of each net
If the SS value is 2 μA or less and the value obtained from the current measuring device 13 is 5 μA, a defective result can be obtained, but it is not known which pin of the chip C1 or C2 is defective. The same applies to the net 11 configured to input the output from the output pin 2 of the chip C1 in the multichip module to the input pin 1 of the chip C2 in the multichip module.

In general, a multi-chip module requires a large number of leads and requires test terminals. However, it is sufficient if there is enough room for installing test terminals. Need to be changed. This leads to an increase in cost and package size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art in testing a multichip module. That is, an object of the present invention is to provide a multi-chip module having a structure capable of reliably specifying a faulty chip in a multi-chip module and specifying a position of a faulty part. It is another object of the present invention to provide an outer lead structure capable of securing a substantial number of terminals even when the number of outer leads is insufficient. or,
It is an object of the present invention to provide a test method capable of individually determining the quality of each chip mounted on the multichip module.

[0013]

Means for Solving the Problems The present invention (claim 1) provides:
In a multi-chip module in which a plurality of bare chips are mounted on a substrate, a supply unit for individually supplying power to all bare chips on the substrate is provided. According to a second aspect of the present invention, in the multi-chip module, one side is connected to a terminal of each bare chip, and the other side has a lead frame having leads connected to outer leads, and at least one outer lead has a plurality of leads. The plurality of leads are connected to terminals of different bare chips, each of which is configured as one pin assembled via an insulating layer.

The test method of the present invention (claim 3) is a test method of a multi-chip module provided with a supply means for individually supplying power to a plurality of bare chips mounted on a substrate, Among these, the procedure of supplying power to only the bare chip under test and stopping the supply of power to the other bare chips is sequentially repeated by changing the bare chip under test, and the test is performed.
Preferably, when the number of power supplies to be connected at the time of the test is smaller than the number of bare chips, the connection destination is switched using a switch switching mechanism, and the power supply is connected only to the bare chips under test.

[0015]

According to the present invention (claim 1), the multi-chip module has a configuration in which supply means for individually supplying power to a plurality of bare chips mounted on a substrate is provided. During the test, the power supply source corresponding to each bare chip can be individually connected to the bare chip in the measurement system, and power can be supplied only to the bare chip under test, so standby current measurement, leak measurement, in-circuit test All other tests can be performed without being affected by other chips. Further, since the measurement is performed on the bare chip alone, it is not necessary to consider the operation of the entire multi-chip module, and the test program and the jig manufacturing time can be reduced. In various tests, it is possible to reliably specify the faulty chip in the multi-chip module and the position of the faulty part.

In a configuration having an individual power supply for each bare chip, the outer leads of the multi-chip module require the same number of chips as the number of chips. ), A plurality of leads are assembled to one pin of the outer lead via an insulating layer to form a single pin, and the plurality of leads are connected to terminals of another bare chip, for example, a bare chip shown in FIG. Power lead P of C3
N3 and the power supply lead PN4 of the bare chip C4 are wired at adjacent pad positions on the same side of the substrate K1 of the multi-chip module, and the lead frames of each other are placed vertically on the same outer lead position with the insulator Z1 interposed therebetween. By doing so, the number of pins can be reduced. When a multi-chip module is mounted on a motherboard used in an actual machine, a plurality of leads PN3 and PN4 naturally short-circuit due to the solder H1, so that there is no problem in mounting reliability. Preferably, when the number of power supply sources is insufficient for the total number of chips in the multi-chip module,
By providing a switch in the measurement system and sequentially switching the power supply destination and using the power supply, the test according to the present invention can be performed even if only one power supply source is provided. In addition, since a configuration for power supply switching is provided in the measurement system, it is possible to prevent an increase in the size of the multi-chip module and a decrease in reliability, thereby simplifying the measurement procedure.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structural Example 1 of Multichip Module) An embodiment of a semiconductor integrated circuit using a multichip module according to the present invention will be described. FIG. 1 is a diagram showing an outline of an electrical wiring connection relationship of the multichip module of the embodiment, and FIG. 2 is a diagram showing an image of a power supply path of the multichip module and a configuration inside the substrate of the multichip module. . As shown in FIG. 1 and FIG. 2, the multi-chip module module M1 of this embodiment
Four bare chips C1 to C4 are mounted in a multi-chip module substrate K1 having a thin-film multilayer wiring layer, and are connected at a high density by the thin-film multilayer wiring layers.

All the conductor wiring patterns of the thin film wiring layer in the substrate K1 are connected to signal input / output pads provided on the periphery of the substrate K1, and each pad is connected to an outer lead R2 via a lead frame R1. ing. Nodes N1 to N9 formed by the outer leads R2 are used for observing the operation state of the bare chip and the wiring at the time of testing the multichip module. Node N1, N
2, N5 are nodes for signals for input operation only, nodes N3 and N4 are nodes for signal output operations only, and N6 to N9.
Is a node having a bidirectional attribute capable of inputting and outputting signals.
At this time, the node having the bidirectional attribute, for example, N6 has the bidirectional attribute by a combination of the output of the bare chip C1 and the input of the bare chip C3. The power supply unit in the substrate K1 is individually provided for each chip as a power supply plane VP1 to VP4 or a power supply mesh in any thin film wiring layer. FIG.
In FIG. 22 and FIG. 22, the power supply path is drawn with a thick line,
The power supply section of each chip is connected to an independent and separate pad so that power can be individually supplied to each chip, and the power supply pad is connected to the lead frame R as in the case of the signal.
1 is connected to the outer lead R2. In testing the multi-chip module, the power supply sources P1 to P4 for each chip are connected to the outer lead R2 via independent paths PN1 to PN4, and furthermore, the lead frame R1
And the power plane P via the power pad of each bare chip
The structure connected to 1 to VP4 enables individual and independent power supply to each bare chip.

In the substrate K1, a conductor wiring pattern dedicated to each chip with respect to a power supply source, a power supply inner layer connection via hole,
An independent power supply line is connected from the measurement system to the power supply pad of the chip by using the power supply inner layer division area or the like. According to this configuration example, the multi-chip module is configured for all bare chips on the multi-chip substrate.
Since the multi-chip module has a configuration in which a power supply unit for individually supplying power is provided, a power supply source corresponding to each bare chip is individually connected to the bare chip in the measurement system, and only the bare chip to be tested is connected. Since the power can be supplied to the power supply, the standby current measurement, leak measurement, in-circuit test, and all other tests can be performed without being affected by other chips. Further, since the measurement is performed on the bare chip alone, it is not necessary to consider the operation of the entire multi-chip module, and the test program and the jig manufacturing time can be reduced. In various tests, it is possible to reliably specify the faulty chip in the multi-chip module and the position of the faulty part.

(Structural Example 2 of Multi-Chip Module) The outer leads of the multi-chip module of the above-described structural example 1 must be provided with a necessary number of power supply types by the number of chips. At this time, it is sufficient if there is enough room for the necessary number of power supplies for the number of outer leads (number of pins), but if the number of pins is insufficient, the multi-chip module package needs to be changed. This leads to an increase in cost and package size. In order to solve this problem, in the present configuration example 2, a quad flat package (QFP) configuration as shown in FIG. 3 is employed and the structure of the outer leads is devised. The power supply lead PN3 of the chip C3 and the power supply lead PN4 of the chip C4 are wired at adjacent pad positions on the same side of the substrate K1, and the respective leads are placed vertically with the same outer lead position sandwiching the insulator Z1. With this lead frame configuration, only one power supply pin is required, and the number of pins of the multichip module can be reduced. The power supply during the test is performed by probing the pins PB3 and PB4 above and below the pins, respectively.

When mounting a multi-chip module on a motherboard used in an actual machine, naturally the upper and lower leads PN are used.
3. Since the PN4 is short-circuited by the solder H1, there is no problem in mounting reliability. In addition, the lead frame structure can be used not only as a power supply pin but also as a lead frame for general signals. In this case, since the nodes are the same when mounted on a board, logically, test pins that are not used in actual operation are generally targeted.

In the configuration example 2, two outer leads are vertically stacked with the insulator Z1 interposed therebetween, but one outer lead is slit in the longitudinal direction to form a bifurcated state. The structure may be changed to a structure in which an insulator is interposed. Further, as shown in FIG. 4, the four leads A, B, C, and D are put together via an insulator Z to form one outer lead, and the outer lead is bent at the end to be surface-mounted. It can also be structured. According to this structure, the outer leads for testing are the same as having four pins. On the other hand, during mounting, the four leads are electrically and mechanically connected to one outer lead by solder bonding. Become. Therefore, even when there is no room for the outer lead installation space and the number of outer leads for individual power supply cannot be secured with a normal outer lead, the outer lead structure described above can be used.
It is possible to secure individual power supply terminals for testing.

Further, as shown in FIG. 5, a terminal structure of a lead insertion type can be adopted. In this case, the two leads A and B are superimposed on each other with the insulator interposed therebetween, are bent downward, and have a tapered end so as to be easily inserted into the wiring hole.

(Test Method of Multi-Chip Module) FIG. 4 shows a test method of a multi-chip module for testing a multi-chip module package having a structure in which power can be individually supplied as shown in FIGS. It is a flowchart which shows the example of a procedure of. The bare chips C1, C2, C3, and C4 mounted on the multichip module are sequentially inspected one by one. Therefore, the power supply path is connected to the power supply sources P1, P2, P3, and P4 for measurement independently of the remaining bare chips for each bare chip.

First, a test start bare chip is set up (step S1). That is, the power supply source corresponding to one bare chip to be tested is turned on, and the power supply sources of the other test bare chips are turned off. For example, when the first chip to be tested is the chip C1, only the power supply source P1 connected exclusively to the chip C1 is activated, power is supplied from the power supply path PN1, and the chip C1 is tested according to the procedure shown in FIG. You. After the setup of the starting chip, a contact check between the inspection target bare chip and the measurement system is performed (step S2). If the contact is normal, the static power consumption of the bare chip to be inspected, so-called standby current, is measured (step S3).
The standby current measurement was performed as shown in FIG.
Alternatively, a voltage is applied from the voltage supply source 8 to the power supply unit VDD1 or VDD2 of C2, and the current flowing to the chip is measured by the current measuring device 6 accordingly. The power consumption is calculated from the applied voltage and the measured value of the current.

If the standby current is normal, a leak measurement is performed next (step S4). As shown in FIG. 10, the leakage current was measured by using the switches 16 and 17
To supply power from the dedicated power supply source 18 to the bare chip under test, for example, only C1. Then, in a state where a test pattern for applying a voltage suitable for the function of each pin is applied to all the outer leads for signals of the bare chip under test to which power is supplied, a voltage (VIL) of a predetermined level is applied to the pin from the voltage source 21. , VIH, VO
L, VOH) and the resulting current is measured by a current measuring device 2
Measure with 0. The measurement of the leak current is sequentially performed on all the input pins 1 in the order of the bin number 12 of the pin 1. The test items for this leak measurement are commercially available LS
Items that can be measured with I or a board tester shall be implemented.

As a result of the standby current measurement in step S3, if the standby current is not normal, the subsequent test of the bare chip C1, ie, the leak measurement (step S4), the in-circuit test (step S5) is not performed, and the next test is performed. The test chip is prepared for test (step S6). At this time, if the standby current is abnormally large, the test can be stopped, so that destruction due to generation of an abnormal current to the measurement system and the chip to be measured can be prevented. Next, if the result of the leak measurement (Step S4) indicates normal, an in-circuit test (Step S5) is performed. In the in-circuit test, test data is applied from an input pin, and pass / fail is determined by comparing the obtained output data with expected value data prepared in advance. If there is a leak abnormality in the leak measurement, the in-circuit test S5 is not performed, and the test preparation of the next untested chip is performed (step S6). If the in-circuit test also passes, the chip C1 becomes a non-defective product, and the test is continued in the order of the chip C2, the chip C3, and the chip C4.

According to the embodiment of the test method of the present invention described above, a power supply is applied to each chip individually, and a standby current measurement and a leak measurement are performed. Can be identified. At the time of the identification, it is not necessary to perform a failure analysis such as a destructive inspection as in the related art. Therefore, the test time can be reduced. In addition, since it is only necessary to apply power to each chip and determine the failure of the chip, a test program for determining the failure can be simplified, and the time required to create the program can be reduced. Further, it is easy to detect multiple failures in which a plurality of chips have failed. Since power is not applied to the other chips in the test of a certain chip, it is not necessary to be aware of the chip control signals from the other chips when determining a failure, and the standardization of the in-circuit test method is facilitated. Even for signal lines connected to a plurality of input / output pins of different chips, since the signal is valid only for the chip under test, the leak of the input / output pins of the specific chip can be measured.

In the test method of the above embodiment, the power supply sources P1, P2, P3, and P4 for measurement are provided corresponding to each of the four chips in the multi-chip module. FIG. 11 shows a configuration in which only one power supply source P1 can be provided for four chips in M1. The power supply switches SW1 to SW4 for four chips are installed in the measurement system, and the switch group S
The test is performed by switching W1 to SW4 in order to apply power to the chip under test.

[0030]

According to the present invention (claim 1), the multi-chip module has a configuration in which a supply means for individually supplying power to all bare chips is provided. Can individually connect the power supply source to the bare chip and supply power only to the bare chip under test, and reliably identify the faulty chip in the multi-chip module and specify the position of the faulty location be able to. According to the present invention (claim 2), a structure is provided in which one outer lead has a function as a plurality of terminals at the time of a test, so that input / output of a power supply or a general signal can be performed with a smaller number of outer leads, that is, a smaller number of pins. Can serve.

According to the present invention (claim 3), the multi-chip module to be tested has a supply means for individually supplying power to all bare chips, and the power supply sources are individually connected to the bare chips. Therefore, various necessary tests can be performed without being affected by other chips. Further, since the measurement is performed on the bare chip alone, it is not necessary to consider the operation of the entire multi-chip module, and the test program and the jig manufacturing time can be reduced.
Further, it is possible to reliably specify the faulty chip in the multi-chip module and the position of the faulty part.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of individualizing a power supply of a multichip module substrate of the present invention.

FIG. 2 is an image diagram showing a power supply division structure of the multi-chip module according to the present invention.

FIG. 3 is a diagram for explaining an example of a lead structure in which one lead (one pin) carries two nodes.

FIG. 4 is a view showing an example of a surface-mounted split lead structure in which one lead carries four nodes.

FIG. 5 is a diagram showing an example of a lead insertion type split lead structure in which one lead carries two nodes. The figure which shows an example of the procedure of a test.

FIG. 6 is a flowchart showing an example of a procedure of a test method of the multichip module of the present invention.

FIG. 7 is a diagram for explaining measurement of standby current of a conventional multichip module.

FIG. 8 is a diagram for explaining measurement of a standby current of the multichip module of the present invention.

FIG. 9 is a view for explaining measurement of a single net (pin) leak current of a conventional multichip module.

FIG. 10 is a view for explaining measurement of a single net (pin) leak current of the multichip module of the present invention.

FIG. 11 is a diagram for explaining a test method of the multi-chip module when the number of power supply sources of the measurement system is smaller than the number of chips.

FIG. 12 is a diagram showing a conventional power supply division configuration in a normal package mounted on a printed circuit board.

FIG. 13 is an image diagram showing a power supply division structure in a conventional example of the normal package of FIG. 12;

[Explanation of symbols]

P1 to P4, P12, P34 ... Power supply source. M1 ... Multi-chip module. M2: Printed circuit board. PN1
PN4, PN12, PN34: Paths from the power supply source to the chip in the multi-chip module. C1 to C4: chips in a multichip module. N1 to N8: input / output terminals from outside each chip and general signals in the board. K1 ... substrate. R1 ... lead frame. R2: External lead. Z1 ...
Insulator. PB3, PB4 ... Power supply probe. H1 solder, 1 input pin, 2 output pin, 3 internal circuit, 4,
6, 7, 13, 20 ... current measuring device, 5, 8, 9, 14,
15, 18, 19 ... power supply source, 10, 11 ... net,
12 bin number, 16, 17 switch.

Continued on the front page F-term (reference) 2G003 AA00 AB02 AB05 AB18 AH01 AH04 AH05 AH10 2G032 AA00 AB02 AC03 AD01 AD08 AE14 AK01 AL05 4M106 AA02 AA04 BA14 CA04 CA15 CA70 5F038 BE09 CA10 DT02 DT05 DT10 EZ07 EZ20

Claims (3)

[Claims] 1. A multi-chip module in which a plurality of bare chips are mounted on a substrate, wherein a supply means for individually supplying power to all bare chips on the substrate is provided. 2. One end is connected to a terminal of each bare chip,
The other has a lead frame having a lead connected to the outer lead, at least one outer lead is configured as one pin by collecting a plurality of leads via an insulating layer, and the plurality of leads are The multi-chip module according to claim 1, wherein the multi-chip module is connected to a terminal of another bare chip. 3. A method for testing a multi-chip module, comprising: a supply unit for individually supplying power to a plurality of bare chips mounted on a substrate, wherein a plurality of bare chips are to be tested. A test method for a multi-chip module, comprising: repeating a procedure of supplying power and stopping the supply of power to other bare chips, changing the bare chip under test, and performing a test.