JPH06249906A - Dummy chip for test of terminal connection - Google Patents

Abstract

PURPOSE:To detect an open defect in a terminal and to perfectly detect a short- circuit defect between adjacent terminals in the verification of a packaging process for a semiconductor device. CONSTITUTION:Electrode pads 2 on adjacent sides of a semiconductor substrate 1 are wired by a plurality of short-circuit patterns 11 which become parallel to one out of diagonal lines on the semiconductor substrate 1, short-circuit pairs for the electrode pads 2 which are not adjacent are formed on the semiconductor substrate 1 by a plurality of interconnections which are not crossed with each other. One pair of electrode pads 2 which have been connected by the short-circuit patterns 11 are not adjacent. When the leakage of a current between lead terminals for an arbitray short-circuit pair and residual lead terminals is confirmed sequentially after a packaging operation, it is possible to perfectly detect a short-circuit defect between all adjacent terminals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dummy chip for a terminal connection test used for optimizing a packaging process in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor device, bonding is performed by bonding lead terminals to a plurality of electrode pads formed on a substrate of a semiconductor chip, and if necessary, the semiconductor chip and the lead terminals are resin-sealed. Do molding.

In order to optimize the process conditions in packaging such as bonding and molding, a dummy chip has been used to test the electrical connectivity between the electrode pad and the lead terminal. The dummy chip for the terminal connection test is, for example, as shown in FIG. 9, one in which adjacent electrode pads 2 on each side of the semiconductor substrate 1 are connected by a short circuit pattern 3.

In the process of the terminal connection test, the lead pads 5 are bonded to the electrode pads 2 on the semiconductor substrate 1 of the dummy chip by the signal lead-out intervening portions 4 (for example, bonding wires or TAB inner leads). Further, after performing molding with the sealing resin 6, in order to evaluate the electrical connectivity between the electrode pad 2 on the semiconductor substrate 1 and the lead terminal 5, first, an arbitrary short-circuit pair connected by the short-circuit pattern 3 is connected. The open defect is inspected by sequentially confirming the continuity between the lead terminals 5 and further confirming that the leak current does not flow between the lead terminals 5 of any short-circuit pair and the remaining lead terminals 5. I was inspecting for short circuits.

[0005]

By the way, in a packaging process such as bonding or molding, adhesion of conductive foreign matter, misalignment between the electrode pad and the signal lead-out intervening portion or between the lead terminals, and signal lead-out intervening. Most of the short circuit defects caused by deformation of parts, penetration of moisture and ions, growth of whiskers, etc.
It occurs between adjacent terminals or terminals in the vicinity thereof.

However, in the conventional dummy chip as described above, open defects of all terminals can be completely detected by sequentially confirming the continuity between the lead terminals 5 of the short-circuited pairs connected by the short-circuit pattern 3. Since the adjacent electrode pads 2 are connected in advance by the short-circuit pattern 3, there is a problem that a short-circuit defect between these adjacent terminals cannot be detected.

As the pitch of the electrode pads becomes narrower as the semiconductor device becomes highly integrated, the rate of occurrence of the above-mentioned short circuit defect in the packaging tends to remarkably increase, and it is extremely difficult to completely detect this. Has become important.

Therefore, the present invention has been made in view of the above circumstances, and in verification of a packaging process of a semiconductor device, it is possible to completely detect not only a defective opening of a terminal but also a defective short circuit between adjacent terminals. It is intended to provide a dummy chip for a possible terminal connection test.

[0009]

In order to solve the above problems, the present invention has a plurality of electrode pads on a semiconductor substrate and tests the electrical connectivity of lead terminals bonded to these electrode pads. A dummy chip for a terminal connection test is provided with a plurality of short-circuit patterns which are respectively wired between a pair of non-adjacent electrode pads on the semiconductor substrate and do not intersect each other.

[0010]

According to the present invention constructed as described above, after the dummy chip is packaged such as the bonding of the lead terminal and the molding with the molding resin, the open defect is not connected to the arbitrary pattern by the short circuit pattern. By sequentially checking whether or not a current flows from one lead terminal of the short-circuited pair to the other lead terminal, it is possible to detect like the prior art. For short-circuit failure, apply a predetermined voltage between the lead terminals of any one set of short-circuit pairs and fix all other lead terminals to the ground potential or another reference potential to sequentially leak current. It can be detected by checking. That is, since the pair of electrode pads short-circuited by the short-circuit pattern are not adjacent to each other, it is possible to completely detect the short-circuit failure between all the adjacent terminals.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a dummy chip for a terminal connection test according to the present invention will be described below with reference to FIGS.

First, FIGS. 1 and 2 show a first embodiment. FIG. 1 shows an example of a dummy chip having a square shape.
FIG. 2 shows an example in which the QFP type packaging is applied to the dummy chip of FIG. As shown in FIG. 1, with respect to the adjacent sides of the semiconductor substrate 1, the electrode pads 2 on the respective sides are wired by a plurality of short-circuit patterns 11 that are parallel to one of the diagonal lines of the semiconductor substrate 1. A short-circuited pair of non-adjacent electrode pads 2 is formed on the semiconductor substrate 1 by a plurality of wirings that do not intersect each other.

The materials and dimensions of the semiconductor substrate 1 and the electrode pads 2 are the same as those of the actual semiconductor device intended for production. The short-circuit pattern 11 uses, for example, aluminum wiring, but if the wiring material of the short-circuit pattern 11 is the same as that of the electrode pad 2, it can be formed by a single metallizing process such as vacuum deposition or sputtering. In addition, it is desirable to appropriately add the electrode pad 2 and the lead terminal so that the electrode pad 2 on which the short circuit pattern 11 is not wired cannot be left over.

Using the dummy chip configured as described above, as shown in FIG. 2, the electrode pad 2 on the semiconductor substrate 1 is formed.
Then, the lead terminal 5 is bonded by the signal lead-out intervening portion 4 (for example, a bonding wire or a TAB inner lead), and further, molding is performed by the sealing resin 6 or the like, and packaging similar to an actual semiconductor device is performed. Give.

After that, a terminal connection test is carried out. Regarding the open failure, one lead terminal 5 to the other lead terminal 5 of an arbitrary short-circuit pair connected by the short-circuit pattern 11 is connected.
By checking sequentially whether the current flows to
Detection is possible as in the prior art. For short-circuit failure, a predetermined voltage is applied between the lead terminals 5 of any one set of short-circuit pairs, and all the other lead terminals 5 are fixed to the ground potential or another reference potential to generate a potential difference. Then, the leakage can be detected by sequentially checking the leakage of current. That is, since the pair of electrode pads 2 short-circuited by the short-circuit pattern 11 are not adjacent to each other, it is possible to completely detect a short-circuit defect between all adjacent terminals.

Next, FIG. 3 shows a second embodiment, in the case where the rectangular QFP type dummy chip, that is, the number of electrode pads 2 on the long side and the short side of the semiconductor substrate 1 is different. Here is an example. The short circuit pattern 11 is formed in parallel between the electrode pads 2 on the long side and the short side adjacent to the semiconductor substrate 1, and the short circuit pattern 12 is formed in parallel between the electrode pads 2 remaining on the opposite long sides. ing. As a result, even if the number of electrode pads 2 on the long side differs from the number of electrode pads 2 on the short side, the pair of short-circuit patterns 11 that are not adjacent to each other are short-circuited.
And 12 can be connected.

According to the first and second embodiments described above,
Since the plurality of short-circuit patterns 11 and 12 are all substantially parallel, the design and formation of the short-circuit patterns 11 and 12 are extremely easy.

Next, FIG. 4 shows a third embodiment, which is an example of a square QFP type dummy chip. Approximately half of the electrode pads 2 on each side of the semiconductor substrate 1 are connected to the electrode pads 2 on adjacent sides by a parallel short circuit pattern 11.

Next, FIG. 5 shows a fourth embodiment, which is an example of a rectangular QFP type dummy chip. Approximately half each of the electrode pads 2 on the short side of the semiconductor substrate 1 is connected to the electrode pads 2 on the adjacent long sides by a parallel short-circuit pattern 11, and the electrode pads 2 remaining on the opposite long sides are connected to each other. , Are connected by parallel short-circuit patterns 12.

According to the third and fourth embodiments described above,
The distance between the plurality of short-circuit patterns 11 and 12 can be made as short as possible.

Next, FIG. 6 shows a fifth embodiment, which is an example in which the electrode pads 2 are formed on a pair of opposite sides of a DIP type dummy chip, that is, the semiconductor substrate 1. is there. In this case, the electrode pads 2 on the opposite sides
By connecting the parallel short-circuit patterns 12 to each other, the pair of electrode pads 2 which are not adjacent to each other can be easily connected to each other regardless of whether the semiconductor substrate 1 is square or rectangular.

Next, FIG. 7 shows a sixth embodiment, which is an example in which the SIP type dummy chip, that is, the electrode pad 2 is formed only on one side of the semiconductor substrate 1. The electrode pads 2 which are not adjacent to each other are connected to each other by a plurality of short-circuit patterns 13 in the inner portion of the semiconductor substrate 1.
At least one set of electrode pads 2 is connected by the short-circuit pattern 14 at the outer edge portion of the semiconductor substrate 1. This short-circuit pattern 14 portion is insulated from the lead terminals joined to the electrode pads 2 between them. May be provided, or if the short-circuit pattern 13 that intersects is insulated, wiring may be provided inside the semiconductor substrate 1.

Next, FIG. 8 shows a seventh embodiment. In the same SIP type dummy chip as described above, a plurality of electrode pads 2 which are not adjacent to each other are formed in the inner portion and the outer edge portion on the semiconductor substrate 1. The short circuit patterns 13 and 14 are alternately connected. Particularly, according to this example, the distance between the plurality of short-circuit patterns 13 and 14 can be made as short as possible.

The embodiments of the present invention have been described above.
The present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, the short-circuit pattern can be variously modified in addition to the embodiment, and various short-circuit patterns may be arbitrarily combined.

[0025]

As described above, according to the present invention,
By wiring a pair of non-adjacent electrode pads on the semiconductor substrate with a plurality of short-circuit patterns that do not intersect with each other, in the verification of the packaging process such as bonding and molding, not to mention all open defects of all terminals, It is possible to completely detect a short circuit defect between adjacent terminals. Therefore, the verification of the packaging process can be performed with extremely high accuracy, and the high integration of the semiconductor device can be further promoted.

If a pair of electrode pads that are not adjacent to each other, particularly an electrode pad on one side and an electrode pad on another side, are connected by a short circuit pattern, the lead terminals of the short circuit pair can be sufficiently separated. In the test process, it is possible to prevent accidental contact between the lead terminals of the short-circuited pair.

[Brief description of drawings]

FIG. 1 is a perspective view of a dummy chip according to a first exemplary embodiment of the present invention.

FIG. 2 is a perspective view of a packaged dummy chip of the first embodiment.

FIG. 3 is a perspective view of a dummy chip according to a second exemplary embodiment of the present invention.

FIG. 4 is a perspective view of a dummy chip according to a third exemplary embodiment of the present invention.

FIG. 5 is a perspective view of a dummy chip according to a fourth exemplary embodiment of the present invention.

FIG. 6 is a perspective view of a dummy chip according to a fifth embodiment of the present invention.

FIG. 7 is a plan view of a main part of a dummy chip according to a sixth embodiment of the present invention.

FIG. 8 is a plan view of a main portion of a dummy chip according to a seventh embodiment of the present invention.

FIG. 9 is a perspective view of a conventional dummy chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Electrode pad 4 Interposition part for signal extraction 5 Lead terminal 6 Sealing resin 11, 12, 13, 14 Short-circuit pattern

Claims (5)

[Claims] 1. A dummy chip for terminal connection test, comprising a plurality of electrode pads on a semiconductor substrate, for testing the electrical connectivity of lead terminals joined to these electrode pads. A dummy chip for a terminal connection test, which has a plurality of short-circuit patterns which are respectively wired between a pair of non-adjacent electrode pads and do not intersect each other. 2. The dummy chip for a terminal connection test according to claim 1, wherein the plurality of short-circuit patterns are formed in parallel between electrode pads on adjacent sides of the semiconductor substrate. 3. The dummy chip for a terminal connection test according to claim 1, wherein the plurality of short-circuit patterns are formed in parallel between electrode pads on opposite sides of the semiconductor substrate. 4. The plurality of short-circuit patterns are formed in parallel between electrode pads on adjacent sides of the semiconductor substrate and between electrode pads on opposite sides of the semiconductor substrate. Dummy chip for terminal connection test. 5. The dummy chip for a terminal connection test according to claim 1, wherein the plurality of short circuit patterns are formed between electrode pads on one side of the semiconductor substrate.