JPH04365347A - Element structure for monitor apparatus in semiconductor chip - Google Patents

Abstract

PURPOSE:To reduce an occupying area in a pattern region of a test element group by introducing a multilayer structure for test elements, electrodes used as input and output terminals thereof and wirings for connecting these terminals. CONSTITUTION:An arrangement structure of a monitor apparatus 10 in a pattern region 3 of a test element group is formed into a multilayer structure by providing aluminium pads 19 as the input and output terminals on the surface of the pattern region 3 and sequentially providing polysilicon wirings 18 and test transistors 14 in the side of lower layer. Therefore, the area occupied by polysilicon wirings 18 and test transistors 14 in the pattern region 3 of test element group can be effectively saved. Thereby, the pattern region 3 of test element group can be microminiaturized and reduced in size to such an area as is required for arrangement on each aluminium pad 19.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an element structure for a monitoring device in a semiconductor chip on a semiconductor wafer, and more specifically, in manufacturing a semiconductor device, the electrical characteristics of each semiconductor element in a semiconductor chip are individually monitored. Test element group (Test
Element Group (hereinafter referred to as TEG)
This invention relates to an improvement in the element structure for a monitor device formed within the pattern area of the invention.

0002

[Prior Art] Generally, in the manufacture of semiconductor devices,
As shown in FIGS. 5 and 6, in order to monitor the electrical characteristics of each semiconductor element formed in each semiconductor chip 2 on a semiconductor wafer 1, each semiconductor element is It is a normal practice to arrange a TEG pattern region 3 for each chip 2 and to incorporate an element structure for a monitor device into the TEG pattern region 3.
A plurality of sets of pattern regions 3 are simultaneously formed on the semiconductor wafer 1.

[0003]The configuration of the element structure for the monitor device incorporated in this TEG pattern area 3 consists of a test element, each electrode serving as its input/output section, in this case an aluminum pad, and their interconnection. It is known as a collection of configurations made up of each wiring to be connected, in this case aluminum wiring.

FIG. 7 shows an outline of a TEG pattern area in a conventional semiconductor wafer of this type, and FIG. 8 shows an arrangement of one element for a monitor device within the TEG pattern area.

The conventional T shown in FIGS. 7 and 8
In the structure of the EG pattern area, the TEG pattern area 3 is formed corresponding to each semiconductor chip 2, as mentioned above, and one of the reasons for this is that the TEG pattern area 3 is formed corresponding to each semiconductor chip 2.
This is because exposure is now performed using a stepper when forming the pattern region 3, and with the increase in wafer diameter, it has become necessary to have in-plane distribution of electrical properties within the wafer. .

In each figure of the conventional example, the reference numeral 21 indicates a test element for monitoring the electrical characteristics of each element formed in the semiconductor chip 2. In this case, 3 It is a transistor having a terminal. Further, reference numerals 22 denote aluminum pads that are connected to the test transistor 21 by aluminum wiring 23 and serve as electrodes, and each of these aluminum pads 22 is connected to a terminal of an evaluation device, a so-called tester (not shown). Connected detection needle 2
4 can be brought into contact. In this case,
The area of the TEG pattern region 3 is approximately 8,000 μm x 5,000, although it varies depending on the product type.
μm, and the area of each aluminum pad 22 is at least 100 μm × 100 μm.
It is set to a certain size.

[0007] Therefore, the evaluation of the electrical characteristics of the test transistor 21 using the TEG pattern region 3 having the above configuration is performed by evaluating the individual aluminum pads 22 connected to the test transistor 21. With the detection needles 24 electrically connected by contacting them, signals from the tester, such as voltage and current, are applied to the test transistor 21 through each detection needle 24, and the test at this time is performed. This is done by monitoring the state of the transistor 21 on the tester side.

[0008]

As described above, each semiconductor chip 2 and one set of TEG pattern regions 3 corresponding thereto are formed simultaneously on the semiconductor wafer 1. In order to maximize the number of individual semiconductor chips 2 formed on one semiconductor wafer 1, it is desirable to reduce the area of the TEG pattern region 3 as much as possible.

However, in the conventional case with the above configuration, the form of the TEG pattern area 3 corresponding to each individual semiconductor chip 2 is different from that of the test transistor 21, its input and output, as is clear from FIG. Each of the aluminum pads 22 serving as a section and each of the aluminum wirings 23 that connect these to each other are arranged in the same plane, and, for example, each aluminum pad 2
Regarding 2, since it is necessary to make each detection needle 24 of the tester contact each other as mentioned above, the area is limited to a certain extent (minimum 100 μm).
m × 100 μm), and each aluminum wiring 23 also requires a required area when considering its current conduction resistivity, etc., and as a result,
It is extremely difficult to miniaturize and further reduce the area occupied by these devices, and there is a problem in that it is impossible to increase the number of chips per wafer.

The present invention was made to solve these conventional problems, and its purpose is to reduce the TEG pattern area and increase the number of chips per wafer. An object of the present invention is to provide an element structure for a monitor device in a semiconductor chip of this type.

[0011]

[Means for Solving the Problems] In order to achieve the above object, an element structure for a monitor device in a semiconductor chip according to the present invention is provided in a TEG pattern area and serves as a test element, its input and output parts. Each electrode and each wiring interconnecting these electrodes are formed in a multilayer structure.

That is, the present invention arranges a plurality of sets of semiconductor chips and pattern regions of test element groups on a semiconductor wafer, and determines the electrical characteristics of each semiconductor element formed in the semiconductor chip by using the pattern regions. The test element formed inside, each electrode that becomes its input and output part,
In a device capable of monitoring using a monitor device constituted by each of the wirings connecting these mutually, the arrangement structure of the monitor device within the pattern area includes at least each of the input and output parts. This is an element structure for a monitor device in a semiconductor chip, characterized in that it has a multilayer structure in which electrodes are disposed on the surface of a region, and each wiring and a test element are sequentially disposed on the lower layer side.

[0013]

[Operation] Therefore, in the present invention, a test element, its input and output, is provided within the pattern area of the test element group and is used to monitor the electrical characteristics of each semiconductor element formed in the semiconductor chip. Each electrode,
and a monitoring device using each of the wirings connecting these mutually, at least each electrode as an input and output part is arranged on the surface of the area, and each wiring and the test element are arranged sequentially on the lower layer side. Since the multi-layered structure is formed, it is possible to save the occupied surface area within the pattern area, and furthermore, to reduce its size.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the structure of an element for a monitor device in a semiconductor chip according to the present invention will be described in detail below with reference to FIGS. 1 to 4.

FIG. 1 is a planar pattern diagram showing an outline of a TEG pattern area to which a monitor device element structure is applied in the semiconductor chip of this embodiment, and FIG. 2 is an arrangement configuration of one test element within the same TEG pattern area. FIG. 3 is an explanatory plan view showing an enlarged view of FIG.
-A and BB line sections each schematically showing a schematic configuration. In each figure of these embodiments, the same reference numerals as in each figure of the conventional example indicate the same or corresponding parts.

In the case of the embodiment configurations shown in FIGS. 1 to 4, the TEG pattern region 3 described above includes a p-type single crystal silicon substrate 11, a first interlayer insulating film 12 such as SiO2, and BPSG or the like. second interlayer insulating film 13 of
The monitor device 10 has a multilayer structure on each of these layers 11, 12, and 13, and is highly integrated as follows.

That is, first, on the p-type single crystal silicon substrate 11, a test element, in this case,
Gate electrode 15 via a gate oxide film according to a known structure,
A test transistor 14 (corresponding to the conventional test transistor 21) consisting of n+ type source/drain regions 16 and 17 is then formed on the first interlayer insulating film 12. transistor 1
Each wiring taken out through a contact hole from each part of 4, in this case each polysilicon wiring 18
(corresponding to each conventional aluminum wiring 23) is formed respectively on the second interlayer insulating film 13, in other words,
On the surface of the TEG pattern region 3, each electrode, in this case each aluminum pad 19, is connected to each polysilicon wiring 18 through a through hole.
The aluminum pads 22 (corresponding to the conventional aluminum pads 22) are formed respectively.

In other words, in this embodiment, the monitor device 10 within the pattern area 3
As an arrangement structure, at least each aluminum pad 19 as the input and output portion is arranged on the surface of the region, and each polysilicon wiring 18 and the test transistor 1 are arranged on the surface of the region.
4 are sequentially arranged on the lower layer side, and each of these structures can be manufactured extremely easily at the same time and by the same means as a conventional semiconductor device having a multilayer structure. .

The monitor device 10 according to this embodiment
Also, in exactly the same way as in the conventional case described above, TEG
The electrical characteristics of the test transistor 11 can be evaluated using the pattern area 3 by bringing each detection needle 24 into contact with each aluminum pad 19 connected to the test transistor 11. In the electrically connected state, signals from the tester, such as voltage and current, are passed through each detection needle 24 to the test transistor 11.
This can be easily done by applying the voltage to the test transistor 11 and monitoring the state of the test transistor 11 at this time on the tester side.

Therefore, in the case of the configuration of this embodiment, by making the monitor device 10 a multilayer structure with high integration, T
Each polysilicon wiring 18 within the EG pattern area 3
, and the corresponding area occupied by the test transistor 14 can be effectively saved, and ultimately the TEG pattern region 3 can be miniaturized and reduced to the area required for arranging each aluminum pad 19. It is. Incidentally, according to the experiments conducted by the present inventor, it was confirmed that in this example, the area of the TEG pattern region 3 can be reduced to approximately 2/3 or less when compared with a conventional example with the same number of elements. Obtained.

[0021]

[Effects of the Invention] As described above in detail through the examples,
According to this invention, a plurality of sets of semiconductor chips and a pattern area of a test element group are arranged on a semiconductor wafer, and the electrical characteristics of each semiconductor element formed in the semiconductor chip are formed in the pattern area. In a device capable of monitoring using a monitoring device consisting of a test element to be tested, electrodes serving as its input and output parts, and wiring connecting these to each other, monitoring within a pattern area is possible. Regarding the layout structure of the device, it is possible to achieve high integration by arranging each wiring and test element sequentially on the lower layer while at least each electrode as an input and output part is arranged on the surface of the area. Unlike the conventional structure in which these elements are arranged in the same plane, the area occupied in the pattern area can be effectively reduced, and ultimately,
This makes it possible to miniaturize and reduce the pattern area to the area required for arranging each electrode, and as a result, it has the excellent advantage of increasing the number of chips per wafer.

[Brief explanation of drawings]

FIG. 1 is a planar pattern diagram showing an outline of a TEG pattern region to which a monitor device element structure is applied in a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is an explanatory plan view showing an enlarged arrangement of one monitor device element structure within the TEG pattern region of the same as above.

FIG. 3 is a cross-sectional view schematically showing a general configuration taken along line A-A in FIG. 2;

FIG. 4 is a cross-sectional view schematically showing the general configuration along line BB in FIG. 2;

FIG. 5 is a planar pattern diagram showing the arrangement of a plurality of sets of semiconductor chips and TEG pattern regions on a general semiconductor wafer.

FIG. 6 is an explanatory plan view showing an enlarged view of the combined arrangement of the individual semiconductor chips and TEG pattern regions.

FIG. 7 is a planar pattern diagram showing an outline of a TEG pattern region to which a monitor device element structure is applied in a conventional semiconductor chip.

FIG. 8 is an explanatory plan view showing an enlarged layout of one monitor device element structure within the TEG pattern region as described above.

[Explanation of symbols]

1 Semiconductor wafer 2 Semiconductor chip 3 TEG pattern area (test element group pattern area) 10 Monitor device 11 P-type single crystal silicon substrate 12 First interlayer insulating film 13 Second interlayer insulating film 14 Test transistor ( Test element) 15
Gate electrodes 16, 17 n+ type source/drain region 18
Polysilicon wiring (wiring) 19 Aluminum pad (electrode)

Claims (1)

[Claims] Claim 1: A plurality of sets of semiconductor chips and a pattern area of a test element group are arranged on a semiconductor wafer, and the electrical characteristics of each semiconductor element formed in the semiconductor chip are measured within the pattern area. In a device that can be monitored by a monitor device consisting of a test element formed in the pattern area, each electrode that serves as its input and output portion, and each wiring that connects these to each other, The arrangement structure of the monitor device has a multilayer structure in which at least each electrode as the input and output section is arranged on the surface of the area, and each wiring and the test element are sequentially arranged on the lower layer side. An element structure for a monitor device in a semiconductor chip, characterized by: