JPH0888282A - Semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the reduction in the area of a product chip and to easily detect a defective step in a semiconductor device which contains a process failure detector of multilayer metal wirings. CONSTITUTION: Three types of memory cells formed up to a first layer, the first to a second layer and the first layer to a third layer are contained as test patterns 6 in the empty region 5 of the product chip of a three-layer metal wiring structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device containing a process defect detection circuit.

[0002]

2. Description of the Related Art As semiconductor devices become finer and more highly integrated, the process is becoming more and more complicated year by year, and failure analysis by identifying the manufacturing process that causes the failure is important and takes a huge amount of time. It's very difficult. Further, this tendency is more remarkable in the random logic device having no regularity in the pattern as compared with various memory devices.

Conventionally, a test pattern for detecting a process defect is mounted on a semiconductor device, and the mounting method has adopted the following three methods. First, a process monitor wafer is included in a lot together with a production wafer. Secondly, some points in the wafer are replaced with product chips and test patterns are inserted. Third, a region is provided at the end of the product chip adjacent to the scribe line for dicing, and a test pattern is put therein. However, the above-mentioned first method cannot cope with the single-wafer processing, and the productivity is lowered because one wafer is spent on the monitor. Further, in the second and third methods,
There is a problem that the number of product chips that can be mounted on the wafer is reduced by the area used for the test pattern.

FIG. 3 is a plan view showing a chip structure of a conventional semiconductor device for a gate array, in which a test pattern for process defect detection is mounted by the third mounting method. In the figure, 1 is the basic gate
Array cell, 2 is a scribe line for dicing,
Reference numeral 3 is an input / output circuit area arranged in the peripheral portion of the chip, and 4 is a test pattern for process defect detection.

[0005]

As shown in the drawing, the conventional test pattern 4 is arranged for each chip on the scribe line 2 for dicing or at the end of the chip and adjacent to the scribe line 2. Therefore, the area for the test pattern 4 must be secured, which hinders high-density integration. Further, in order to suppress the area of the test pattern 4 to a minute one, the scale is insufficient for detecting a process defect. further,
Since the test pattern 4 is formed in the area where the basic gate array cell 1 is not formed, the underlying state differs from the circuit actually used as a product (hereinafter referred to as the product circuit), and the reliability of process defect detection is high. However, there is a problem in that

By the way, in a circuit arranged in a chip, when the number of input / output signals increases as in recent years, the chip size is determined by the number of pads because it is necessary to arrange a large number of pads in the peripheral portion, and an empty area is formed in the chip. Occurs. Also, in the gate array of random logic products,
Since the basic gate array cells are regularly formed and arranged in advance on the entire surface in a column unit, and a desired logic circuit is wired and formed by CAD, a circuit configuration is determined by the wiring, and a portion which is not wired, That is, an empty area is created.

The present invention aims to solve the above-mentioned conventional problems by paying attention to these empty areas, and makes it possible to easily analyze process defects and reduce the area used for product chips. It is an object of the present invention to obtain a highly reliable semiconductor device having a built-in test pattern for detecting a process defect with high reliability.

[0008]

A semiconductor device according to claim 1 of the present invention has a memory cell as a process defect detection circuit built in an empty area in a product chip.

A semiconductor device according to a second aspect of the present invention has a memory cell incorporated as a process defect detection circuit in an empty area of an area where a basic gate array cell is formed in a product chip.

A semiconductor device according to a third aspect of the present invention has an input / output buffer or a boundary scan campus register as a process defect detection circuit built in an empty area in a product chip.

In a semiconductor device according to a fourth aspect of the present invention, in a product chip having a multi-layer metal wiring structure consisting of n layers, a process defect detection circuit in which the first layer metal wiring to the kth layer metal wiring are formed, = 1, 2, ..., N for n types.

According to a fifth aspect of the present invention, in a semiconductor device, the process defect detection circuit formed from the first layer metal wiring to the kth layer metal wiring is formed with the same process margin as that of the product circuit. There are two types, that is, only the above-mentioned k-th layer metal wiring forming process which is the upper metal wiring is formed with a process margin larger than that of the product circuit.

In a semiconductor device according to a sixth aspect of the present invention, any one of a plurality of contact holes depending on the difference in the underlying condition of the process defect detection circuit formed up to the first layer metal wiring is the same as the product circuit. In the process margin, others are formed with a process margin larger than that of the product circuit, and such process defect detection circuits are provided as many as desired combinations of the contact holes.

[0014]

In the semiconductor device according to the present invention, since the process defect detection circuit is built in the empty area in the product chip, it is not necessary to separately provide a region for the process defect detection circuit, and the area used for the product chip can be reduced. Absent.
Further, since the memory cell is used, the defective memory cell can be specified from the position of the defective bit at the time of the wafer test, so that the process defect can be easily detected.

Further, since the process defect detection circuit is built in the empty area where the basic gate array cells are formed, the process defect detection circuit can be formed faithfully to the formation environment of the product circuit, and the reliability of the process defect detection is improved. improves.

Further, since the input / output buffer or the boundary scan path register is built in the empty area of the product chip as a process defect detection circuit, even if the empty area is small and the memory cell cannot be formed, the occupied area is small. By using the output buffer or the boundary scan register, it is possible to have an effective process defect detection circuit in the product chip.

Further, according to the present invention, in a product chip having a multi-layer metal wiring structure consisting of n layers, the first layer, the first layer to the second layer ,. Since n types of process defect detection circuits each having a wiring are formed, the defective metal wiring can be identified by evaluating each process defect detection circuit, and the defective process can be detected.

Since only the uppermost metal wiring forming step of the process defect detection circuit formed from the first layer metal wiring to the kth layer metal wiring is formed with a process margin larger than that of the product circuit, When the k-th layer metal wiring becomes defective, the k-th layer metal wiring forming step has a large process margin and cannot be made defective. Therefore, the defect in the connection hole forming step can be identified. Therefore, it is possible to detect the process defect by separating the metal wiring forming process and the connection hole forming process. Here, the process margin is a margin including a design dimensional margin and fluctuations in process equipment and all materials used in the process.

Further, since one of the plurality of types of contact holes is formed with the same process margin as the product circuit and the other is formed with a large process margin, it is possible to specify the defect by the type of contact hole.

[0020]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. Note that the description of the same parts as those of the conventional one will be appropriately omitted. 1 is a plan view showing a chip structure of a semiconductor device according to a first embodiment of the present invention for a gate array. In the figure, 1 to 3 are the same as the conventional ones, 5 is an empty area generated after the wiring process by CAD, and 6 is a test pattern as a process defect detection circuit formed in the empty area 5 of the product chip. This test pattern 6 is formed on the base on which the basic gate array cell 1 is formed in the empty area 5 where wiring as a product circuit is not provided, and whether the metal wiring of each layer of the multilayer metal wiring is good or not is checked. It is a memory circuit for evaluation.

If the product circuit of the memory circuit formed by the test pattern 6 is, for example, three-layer metal wiring,
A first memory cell formed up to the first layer metal wiring;
It is composed of three types of memory cells, that is, a second memory cell formed from the layer metal wiring to the second layer metal wiring and a third memory cell formed from the first layer metal wiring to the third layer metal wiring. The three types of memory cells may be independent three memories, or one type of memory may allow the three types of memory cells to be identified by addresses. In the latter case, the circuit commonly used by the three types of memory cells has a pattern with a large process margin.

The test pattern 6 as described above is formed,
By performing a wafer test, the metal wiring of each layer of the multilayer metal wiring is evaluated. In this case, the evaluation includes whether the contact hole such as a contact hole or a via hole is surely opened, and whether the metal wiring is broken or short-circuited. Here, showing the relationship between the connection hole and the metal wiring, the first-layer metal wiring is formed so as to fill the contact hole, and the second-layer metal wiring is formed thereon so as to fill the first via hole. A third layer metal wiring is formed thereon so as to fill the second via hole. That is, for example, if the second layer metal wiring is defective, it can be seen that the first via hole forming step or the second layer metal wiring forming step is defective. Correspondence between the evaluation of each memory cell and the evaluation of the metal wiring of each layer,
The results are shown in Table 1 below.

[0023]

[Table 1]

As shown in Table 1 above, for example, the first and second
When all the third memory cells are defective I, it is understood that at least the first-layer metal wiring is defective, that is, the contact hole forming step or the first-layer metal wiring forming step is considered to be defective. Also, for example, the first
In the case of III in which the second memory cell is good and the third memory cell is bad, it is found that the first and second layer metal wirings are good and the third layer metal wiring is bad, that is, the second It is considered that there is a defect in the via hole forming process or the third layer metal wiring forming process. In this way, the defective metal wiring can be specified by the evaluation of the first to third memory cells, and the defective process can be identified. The operation test of each memory cell of the test pattern 6 may be performed by switching an existing pad used for a product chip with a switch or the like. Although pads may be separately arranged, they are not limited to the peripheral portion of the chip because they are unrelated to the product circuit.

As described above, since the test pattern 6 is formed in the vacant region 5 on the base on which the basic gate array cell 1 is formed, it is not necessary to separately provide a region for the test pattern 6 and it is used for a product chip. Does not reduce the area. Moreover, since the product circuit and the underlying state are the same, the test pattern 6 can be formed faithfully in the environment in which the product circuit is formed, and the reliability of process defect detection is improved. Further, since the memory circuit is used for the test pattern 6, the defective memory cell can be easily specified from the position of the defective bit in the wafer test, and the test pattern 6 can be easily evaluated at the wafer test stage. Furthermore, for product circuits with three-layer metal wiring, up to the first layer, the second layer, the third layer
Since the test pattern 6 is composed of the three types of memory cells in which the metal wirings up to the layers are respectively formed, it is possible to reliably identify the defective metal wiring.

Example 2. Next, in the above-mentioned Example 1,
A case will be described below in which a step of forming a contact hole such as a contact hole or a via hole and a step of forming a metal wiring formed by burying this connection hole are separated to detect defects. In the first memory cell formed using the first layer metal wiring forming step, the memory cell A formed with the same process margin as the product circuit, and the contact hole forming step with the same process margin as the product circuit, the first layer metal In the wiring forming process, two types of memory cells, that is, the memory cell B formed with a larger process margin than the product circuit are formed. Table 2 below shows the correspondence between the evaluation of the first memory cell consisting of the two types A and B and the defective process in the wafer test.

[0027]

[Table 2]

As shown in Table 2 above, for example, when the memory cell A and the memory cell B are defective I, at least the contact hole forming step has a defect. Further, for example, only the memory cell A is defective II
In the case of, it can be seen that the contact hole forming process is good and the first layer metal wiring forming process is defective.

When the memory cells of A and B types are formed for each of the first to third memory cells in the first embodiment, the connecting hole forming step and the metal wiring forming step of all layers of the three-layer metal wiring are formed. And can be separated to detect defects.
In this case, the memory cell B is formed by enlarging the process margin of the metal wiring forming process of the final layer for the evaluation of the contact hole.

Example 3. Next, a case will be described in which the type of contact hole is separated and the defect is detected when the defect is detected in the contact hole forming step in the second embodiment.
Some contact holes are formed on the gate electrode, the N ⁺ type diffusion layer, or the P ⁺ type diffusion layer, and their shapes are slightly different depending on the thickness of the interlayer insulating film and the underlying conditions. It is a thing. Therefore, the occurrence of defects is not the same, and which kind of contact hole is defective is identified as follows.

In the memory cell B of the first memory cell of the test pattern 6 in the second embodiment, of the contact hole on the gate electrode, the contact hole on the N ⁺ type diffusion layer, or the contact hole on the P ⁺ type diffusion layer, Only the contact hole of interest has the same process margin as the product circuit, and the other contact holes and the first layer metal wiring are formed with a larger process margin than the product circuit. That is, the memory cell B is composed of three types of memory cells focusing on each of the three types of contact holes. Thus, when a defect is detected in any of the above-mentioned three types of memory cells in the wafer test, it can be seen that the contact hole of the type focused on by the defective memory cell is defective. In this way, defects can be detected by separating the types of contact holes.

Example 4. In the first to third embodiments, the test pattern 6 uses the memory circuit including a plurality of types of memory cells. However, in the case where the memory circuit cannot be formed due to space limitations, the input / output buffers existing in all devices, or A logic circuit including a transistor, and a boundary scan path register for testing an assembled chip on a mounted board may be used.
Since these I / O buffers and boundary scan campus registers occupy a smaller area than memory cells, it is possible to construct an effective test pattern 6 even in a small area.

FIG. 2 is a schematic diagram showing the internal structure of the chip. In FIG. 2A, 7 is an input buffer, 8 is an output buffer, 9 is a random logic circuit, and 10 is a switch control circuit. A partially enlarged view of the random logic circuit 9 is shown in FIG. 2B. In FIG. 2B, 11 is a boundary scan path register, and 12 is an internal logic circuit.

In the fourth embodiment as well, the test pattern is formed in a vacant area in the chip, and like the first to third embodiments, a plurality of types of input / output buffers having different use steps or process margins in the multilayer metal wiring ( Alternatively, a boundary scan campus register) is formed, and switches are switched by the switch control circuit 10 to perform an operation test of each input / output buffer (or boundary scan campus register).

[0035]

As described above, according to the present invention, since the process defect detection circuit is built in the empty area in the product chip, the area used for the product chip is not reduced. Further, since the memory cell is used as the process defect detection circuit, the defect can be easily detected at the wafer test stage.

Further, since the process defect detection circuit is built in the empty area in which the basic gate array cells are formed, the process circuit is made faithful to the production environment of the product circuit and the reliability of process defect detection is improved.

Further, since the input / output buffer or the boundary scan register is used as the process defect detecting circuit, an effective process defect detecting circuit can be built in the product chip even if the free area is small.

Further, according to the present invention, in the multi-layer metal wiring structure consisting of n layers, the process defect detection circuit formed from the first layer metal wiring to the kth layer metal wiring is k = 1,
Since it has n kinds of 2, ..., N, the defective metal wiring can be easily specified and the defective process can be detected.

In addition, the process defect detection circuit formed from the first layer metal wiring to the kth layer metal wiring is formed with the same process margin as the product circuit, and the kth layer metal wiring formation process is larger than the product circuit. Since there are two types, one formed with the process margin, the metal wiring forming process and the connection hole forming process can be separated to detect the process defect.

Further, any one of the plurality of types of contact holes is formed with the same process margin as the product circuit and the other is formed with a large process margin, so that the contact holes can be separated according to the type and defect detection can be performed.

[Brief description of drawings]

FIG. 1 is a plan view showing a chip configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an internal configuration of a chip.

FIG. 3 is a plan view showing a chip configuration of a conventional semiconductor device.

[Explanation of symbols]

1 basic gate array cell, 5 free areas, 6 test pattern as process defect detection circuit, 7 input buffer, 8 output buffer, 11 boundary scan campus register.

Claims (6)

[Claims] 1. A semiconductor device comprising a memory cell as a process defect detection circuit built in an empty area of a product chip. 2. A semiconductor device comprising a memory cell as a process defect detection circuit built in an empty area of an area where a basic gate array cell is formed in a product chip. 3. A semiconductor device comprising an input / output buffer or a boundary scan path register as a process defect detection circuit built in an empty area in a product chip. 4. In a product chip having a multi-layered metal wiring structure composed of n layers, a process defect detection circuit in which the first layer metal wiring to the kth layer metal wiring are formed is k = 1, 2, ...
, N for n kinds.
4. The semiconductor device according to any one of 3 to 3. 5. The process defect detection circuit formed from the first layer metal wiring to the kth layer metal wiring, all of which are formed with the same process margin as the product circuit, and the kth layer which is the uppermost metal wiring. 5. The semiconductor device according to claim 4, wherein there are two types, that is, only the metal wiring forming step is formed with a process margin larger than that of the product circuit. 6. A process defect detection circuit having a first layer metal wiring formed therein, one of a plurality of contact holes having different types of base holes having the same process margin as the product circuit and the other having a larger process margin than the product circuit. 5. The semiconductor device according to claim 4, wherein the semiconductor device is formed with a process margin, and the process defect detection circuits are provided in the desired number of combinations of the contact holes.