JP2005056993A - Semiconductor device and method of testing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To analyze presence or non-presence of failure in each wiring layer with a process failure analysis utilizing an SRAM circuit for a semiconductor device including the wiring layers of four or more layers. <P>SOLUTION: A semiconductor chip 10 includes a product integrated circuit 11, and a first SRAM circuit 12 and a second SRAM circuit 13 which are used for process failure detection. The product integrated circuit 11 has the desired function and a wiring layer formed of six layers. The first SRAM circuit 12 realizes the SRAM function with the SRAM cell and the wiring formed on the first to third wirings in the lower layer side among the wiring layers formed of six layers. The second SRAM circuit 13 realizes the SRAM function with the SRAM cell and the wirings formed in the fourth to sixth wirings in the upper layer side among the wiring layers of six layers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a test method thereof, and more particularly to a semiconductor device and a test method thereof capable of specifying a defective portion by failure analysis using an SRAM circuit.

  Semiconductor devices are increasingly miniaturized and highly integrated, and the manufacturing process is also complicated. For this reason, in testing semiconductor devices, it is important not only to test the quality of chips, but also to perform defect analysis to identify which manufacturing process is defective among various manufacturing processes of semiconductor devices. It has become. In order to enable such process failure analysis, a semiconductor device is provided with a process failure detection circuit that makes it possible to analyze at which stage of the manufacturing process the failure is.

  FIG. 4 is a plan view showing a general semiconductor device having an SRAM circuit as a process failure detection circuit. In this example, in each chip 20 formed on the wafer, an SRAM circuit 22 used for process failure analysis is formed adjacent to the product integrated circuit 21. The product integrated circuit 23 is formed with a circuit for realizing a desired function, and has three wiring layers. The SRAM circuit 22 is arranged to identify a defective portion of the wiring layer of the product integrated circuit 23, and includes a C-MOS structure SRAM cell and three wiring layers formed thereon. . In manufacturing the chip 20, the product integrated circuit 21 and the SRAM circuit 22 are formed by the same manufacturing process.

  When the SRAM circuit 22 includes a defective portion, if a test pattern is given from the tester to the SRAM circuit 22, the SRAM circuit 22 outputs defective data. By analyzing the defect data, the cause of the failure of the SRAM circuit 22 can be specified, and the defective portion of the SRAM circuit 22, that is, the defect manufacturing process can be specified. As described above, since the product integrated circuit 21 and the SRAM circuit 22 are formed by the same manufacturing process, by knowing which of the three wiring layers of the SRAM circuit 22 is defective, the product integrated circuit It is possible to know which of the 21 three wiring layers is defective.

As another technique related to a semiconductor device that enables process failure analysis, there is a technique described in Patent Document 1, for example. In Patent Document 1, a semiconductor device incorporates a memory cell as a process failure detection circuit in an empty area of a product chip on which a basic gate array cell is formed. In Patent Document 1, when a semiconductor device has a plurality of wiring layers, a memory cell is arranged corresponding to each wiring layer, and the operation of each memory cell is tested to determine which wiring layer is defective. It can be determined whether it is occurring in
JP-A-8-88282

  In the semiconductor device shown in FIG. 4, when both the product integrated circuit 21 and the SRAM circuit 22 are configured by three wiring layers, the operation of the SRAM circuit 22 is analyzed as described above to analyze the three layers. It is possible to easily determine which of the wiring layers is defective. However, since the SRAM circuit 22 is composed of three wiring layers, if the product integrated circuit 21 has four or more wiring layers, each of the four or more wiring layers of the product integrated circuit 21 is defective. There is a problem that the presence or absence cannot be easily determined. In addition, the technique described in Patent Document 1 has a problem that a large number of memory cells are required because the number of memory cells corresponding to the number of wiring layers is arranged.

  The present invention relates to a semiconductor device having four or more wiring layers, in which it is not necessary to arrange memory cells in each layer, and a semiconductor device that can analyze the presence or absence of defects in each wiring layer by process failure analysis using an SRAM circuit. Another object of the present invention is to provide a test method for a semiconductor device.

  In order to achieve the above object, a semiconductor device of the present invention includes a product integrated circuit having a k layer (where k ≧ 4) wiring layer and having a predetermined function, and three wirings among the k layer wiring layers. A first SRAM circuit in which an SRAM function is realized by three wiring layers formed in the same layer as each other and an SRAM cell, and three wirings of the first SRAM circuit among the k wiring layers A second SRAM circuit that realizes an SRAM function by three wiring layers each including at least one layer different from the layers, three wiring layers formed in the same layer, and the SRAM cell are formed on a common substrate. It is formed.

  In the semiconductor device of the present invention, the three-layer wiring that realizes the SRAM function of the first and second SRAM circuits is wired to at least one different layer, so that both the first and second SRAM circuits are connected. By applying a bitmap analysis that can identify (estimate) which of the three layers of wiring that realizes the SRAM function is defective, which layer of the four or more layers of the product integrated circuit It is possible to specify whether or not is defective.

  The semiconductor device of the present invention preferably includes m SRAM circuits (where m is a maximum integer not exceeding (1 + k / 3)) including the first and second SRAM circuits. In this case, the bitmap analysis is applied to each SRAM circuit by configuring each SRAM circuit so that each of the k wiring layers is wired with the SRAM function by any one of the SRAM circuits. The presence or absence of defects in all layers of the product integrated circuit can be specified.

  A test method for a semiconductor device according to the present invention is a method for testing the semiconductor device according to the present invention, wherein a defect portion of the product integrated circuit is estimated by a failure analysis of the SRAM circuit.

  In the semiconductor device testing method of the present invention, the failure of the product integrated circuit is determined by identifying which of the three layers of wiring that realizes the SRAM function of each SRAM circuit is defective by analyzing the failure of the SRAM circuit. Since the location can be estimated, the defective location of the product integrated circuit can be easily identified as compared with the conventional test method in which the memory cell is arranged corresponding to each layer.

  The method for testing a semiconductor device according to the present invention includes a product integrated circuit having k layers (provided that k ≧ 4) and having a predetermined function, and each of the three wiring layers among the k wiring layers. A first SRAM circuit in which an SRAM function is realized by the three wiring layers and the SRAM cell formed in the first and second k layers, and a layer different from the three wiring layers of the first SRAM circuit. A second SRAM circuit that realizes an SRAM function by three wiring layers each including at least one, three wiring layers formed in the same layer, and an SRAM cell, by a common manufacturing process; And a failure location of the product integrated circuit is estimated by failure analysis of the second SRAM circuit.

  According to the semiconductor device test method of the semiconductor device of the present invention, it is estimated (specified) which layer of the three-layer wiring that realizes the SRAM function of each SRAM circuit is defective by failure analysis of the SRAM circuit. Thus, since the defective part of the product integrated circuit can be estimated, the defective part of the product integrated circuit can be easily identified as compared with the conventional test method in which the memory cell is arranged corresponding to each layer. The product integrated circuit and the first and second SRAM circuits can be formed on the same substrate cut out from the wafer, or can be formed separately on the same wafer. Alternatively, wafers can be formed separately in the same manufacturing process lot.

  In the semiconductor device of the present invention, since the three layers of wiring that realize the SRAM function of the first and second SRAM circuits are wired in at least one different layer, both of the first and second SRAM circuits are provided. By defect analysis, it is possible to identify which layer is defective among the four or more wiring layers of the product integrated circuit, and it is easy to identify a defective portion of the semiconductor device. Further, in the semiconductor device testing method of the present invention, the failure location of the product integrated circuit can be estimated by the failure analysis of the SRAM circuit, so that it is simpler than the conventional testing method in which memory cells are arranged corresponding to each layer. In addition, it is possible to identify defective parts of the product integrated circuit.

  Hereinafter, with reference to the drawings, the present invention will be described in more detail based on exemplary embodiments of the present invention. 1A is a plan view of a wafer on which a semiconductor chip of a semiconductor device according to a first embodiment of the present invention is formed, and FIG. 1B is a plan view of one of the semiconductor chips shown in FIG. The figure is enlarged. As shown in FIG. 2A, a plurality of semiconductor chips 10 are formed on the wafer 100. As shown in FIG. 2B, each semiconductor chip 10 formed on the wafer 100 includes a product integrated circuit 11 having a desired function, a first SRAM circuit 12 and a second SRAM circuit 13 used for process failure analysis. With.

  The product integrated circuit 11, the first SRAM circuit 12, and the second SRAM circuit 13 each have six wiring layers. Since these are formed on the same wafer 100 through the same wafer process, defects occurring in the wafer process also occur with the same probability in each manufacturing process.

  FIG. 2 shows a partial cross section of the first SRAM circuit 12 and the second SRAM circuit 13 of FIG. The first SRAM circuit 12 includes an SRAM cell having a C-MOS structure, and includes a first wiring layer M1 to a third wiring layer M3, a via (1Via, 2Via), and a wiring constituted by a contact C0. Function is realized. In the fourth wiring layer M4 to the sixth wiring layer M6 of the first SRAM circuit 12, wirings not directly related to the SRAM function are wired. In the first SRAM circuit 12, for example, a wiring for connecting the transistors of the SRAM cell is formed in the first wiring layer M1, a word line is formed in the second wiring layer M2, and a digit line is formed in the third wiring layer M3. Is formed.

  Similar to the first SRAM circuit 12, the second SRAM circuit 13 includes an SRAM cell having a C-MOS structure, and is configured by a fourth wiring layer M4 to a sixth wiring layer M6 and a via (3Via to 5Via) thereon. The SRAM function is realized by the wiring. The first wiring layer M1 to the third wiring layer M3, the vias (1 Via, 2 Via), and the contact C0 of the second SRAM circuit 13 are formed with a directly upper via and a dot-like wiring. In the first SRAM circuit 12, the wiring of the SRAM function constituted by the first wiring layer M1 to the third wiring layer M3, the vias (1Via, 2Via), and the contact C0 is connected to the fourth wiring layer M4 to the sixth wiring layer M6, And lift to vias (2 Via 3 to 5 Via). In the second SRAM circuit 13, for example, wiring that connects the transistors of the SRAM cell is formed in the fourth wiring layer M4, a word line is formed in the fifth wiring layer M5, and a digit line is formed in the sixth wiring layer M6. It is formed.

  In the failure analysis of the semiconductor chip 10, the bitmap analysis applied to the failure analysis of the memory product is applied to the first SRAM circuit 12 and the second SRAM circuit 13. In general, since an SRAM circuit has three wiring layers, it is possible to identify which of the three wiring layers constituting the SRAM function is defective by applying bitmap analysis to the SRAM circuit. can do.

  At the time of the test, a test pattern is given from the tester to the first SRAM circuit 12. When the first SRAM circuit 12 includes a defective portion, the first SRAM circuit 12 outputs defective data for the test pattern. From this failure data, it is possible to narrow down whether the failure mode of the first SRAM circuit 12 is one of the four failure modes of single bit failure, pair bit failure, digit failure, and word failure. By specifying the failure mode, it can be estimated in which layer the failure of the first SRAM circuit 12 occurs.

  If the failure mode of the first SRAM circuit 12 is a single bit failure, an SRAM cell field abnormality, gate abnormality, contact C0 abnormality, or first wiring layer M1 abnormality is estimated. If the failure mode is a pair bit failure, an SRAM cell field abnormality, gate abnormality, or via abnormality is estimated. If the failure mode is a digit failure, an abnormality in the third wiring layer M3 to which the digit line is wired is estimated, and if the failure mode is a word failure, an abnormality in the second wiring layer M2 to which the word line is routed. Is estimated.

  By identifying (estimating) the defective portion as described above, from the failure analysis using the first SRAM circuit 12, the first wiring layer M1 to the third wiring layer M3, via (1Via, 2Via) on the lower layer side. And which part of the contact C0 is a defective part. Similarly to the first SRAM circuit 12, the second SRAM circuit 13 is provided with a test pattern from the tester to identify a defective portion. However, the second SRAM circuit 13 has the SRAM function wirings from the fourth wiring layer M4 to the fourth wiring layer M4. Since it is constituted by 6 wiring layers M6 and vias (3Via to 5Via), from the failure analysis using the second SRAM circuit 13, if the operation of the first SRAM circuit 12 is normal, the fourth wiring on the upper layer side It can be seen which portions of the layers M4 to M6 and the vias (3Via to 5Via) are defective portions.

  In the failure analysis by the bitmap analysis, it is possible to estimate which layer is defective according to the failure mode, so that the defective portion can be quickly identified. However, bitmap analysis is a failure analysis method specialized for SRAM circuits, and since SRAM circuits are composed of three wiring layers, conventionally, the semiconductor chip to be analyzed has four or more wiring layers. In some cases, it was impossible to identify the presence or absence of defects in each wiring layer by applying bitmap analysis. In the present embodiment, the SRAM function of the first SRAM circuit 12 is configured by three layers on the lower layer side of the six wiring layers, and the SRAM function of the second SRAM circuit 13 is configured by three layers on the upper layer side. Therefore, by applying the bitmap analysis to both the first SRAM circuit 12 and the second SRAM circuit 13, it is possible to easily specify the presence or absence of defects in each wiring layer among the six wiring layers of the semiconductor chip 10. Can do.

  FIG. 3A shows a wafer on which a semiconductor chip of a semiconductor device according to the second embodiment of the present invention is formed as a plan view, and FIG. 3B shows one of the semiconductor chips shown in FIG. The figure is enlarged. As shown in FIG. 5A, a plurality of monitor semiconductor chips 10a used for process failure analysis are formed on the monitor wafer 100a. The monitor wafer 100a is included in a lot together with the wafer on which the product integrated circuit 11 (FIG. 1B) is formed, and is manufactured by the same manufacturing process as the wafer on which the product integrated circuit 11 is formed. Each monitor semiconductor chip 10a has a first SRAM circuit 12 and a second SRAM circuit 13 similar to those formed in the semiconductor chip 10 of the first embodiment.

  In the first embodiment, the product integrated circuit 11 and the first SRAM circuit 12 and the second SRAM circuit 13 as process failure detection circuits are formed on each semiconductor chip 10. However, as in the present embodiment, Only the first SRAM circuit 12 and the second SRAM circuit 13 may be formed on the monitor semiconductor chip 10a. In this case, by applying a bitmap analysis to the monitor semiconductor chip 10a to identify the defective portion, the product integrated circuit 11 having six wiring layers formed by the same process as the monitor semiconductor chip 10a. It is possible to identify a defective portion that is considered to occur in a semiconductor chip including the above.

  Note that the wiring layers of the analysis target semiconductor chip are not limited to six layers. When the number of wiring layers of the semiconductor chip to be analyzed is k (k ≧ 4), SRAM circuits having k wiring layers are arranged by an integer m not exceeding (1 + k / 3), and each wiring of the k layer is arranged. By configuring each SRAM circuit so that each layer is wired for the SRAM function by any one of the SRAM circuits, the presence or absence of a defect in each wiring layer is specified by applying bitmap analysis. Is possible. For example, when the number of wiring layers k is 7, three SRAM circuits are arranged, the SRAM function of the first SRAM circuit is configured by the first to third wiring layers, and the SRAM function of the second SRAM circuit. Is configured with the fourth to sixth wiring layers, the SRAM function of the third SRAM circuit is configured with the fifth to seventh wiring layers, and bitmap analysis is provided to each of the three SRAM circuits, thereby providing seven layers. It can be specified in which of the wiring layers the defect has occurred.

  In the second embodiment, the monitor semiconductor chip 10a used for process failure analysis is arranged on the monitor wafer 100a. Instead, the product integrated circuit 11 (FIG. 1) is provided on the same wafer. You may form the semiconductor chip which does not have a process failure detection circuit, and the semiconductor chip 10a of 2nd Embodiment. In this case, by applying the bitmap analysis to the monitor semiconductor chip 10a, it is possible to identify a defective portion of the product integrated circuit 11 on the same wafer. FIG. 2 shows an example in which the three-layer wiring for realizing the SRAM function of the SRAM circuit is formed by three continuous layers. However, the three-layer wiring for realizing the SRAM function is formed by three continuous layers. For example, the wiring layer may not be formed in every other layer.

  Although the present invention has been described based on the preferred embodiment, the semiconductor device and the test method of the present invention are not limited to the above embodiment, and various configurations are possible from the above embodiment. Those modified and changed as described above are also included in the scope of the present invention.

FIG. 1A is a plan view showing a wafer on which a semiconductor chip of the semiconductor device according to the first embodiment of the present invention is formed, and FIG. 1B is one of the semiconductor chips shown in FIG. FIG. FIG. 2 is a cross-sectional view showing a partial cross section of a first SRAM circuit 12 and a second SRAM circuit 13 in FIG. 1. FIG. 3A is a plan view showing a wafer on which a semiconductor chip of a semiconductor device according to the second embodiment of the present invention is formed, and FIG. 3B is one of the semiconductor chips shown in FIG. FIG. The top view which shows the general semiconductor device which has an SRAM circuit as a process defect detection circuit.

Explanation of symbols

11: Product integrated circuit 12: First SRAM circuit 13: Second SRAM circuit 10: Semiconductor chip 100: Wafers M1 to M6: Wiring layers 1Via to 5Via: Via

Claims (4)

  Product integrated circuit having k layers (where k ≧ 4) and having a predetermined function, three wiring layers formed in the same layer as the k wiring layers, and SRAM A first SRAM circuit in which an SRAM function is realized by a cell; and three wiring layers including at least one of the k wiring layers different from the three wiring layers of the first SRAM circuit; A semiconductor device characterized in that a second SRAM circuit that realizes an SRAM function is formed on a common substrate by three wiring layers and SRAM cells formed in the same layer.   2. The semiconductor device according to claim 1, comprising m (where m is a maximum integer not exceeding (1 + k / 3)) SRAM circuits including the first and second SRAM circuits. A method for testing a semiconductor device according to claim 1 or 2,
A test method for a semiconductor device, wherein a defective portion of the product integrated circuit is estimated by failure analysis of the SRAM circuit. Product integrated circuit having k layers (where k ≧ 4) and having a predetermined function, three wiring layers formed in the same layer as the k wiring layers, and SRAM A first SRAM circuit in which an SRAM function is realized by a cell; and three wiring layers including at least one of the k wiring layers different from the three wiring layers of the first SRAM circuit; A second SRAM circuit in which the SRAM function is realized by three wiring layers and SRAM cells formed in the same layer, respectively, is formed by a common manufacturing process,
A test method for a semiconductor device, wherein a defect portion of the product integrated circuit is estimated by defect analysis of the first and second SRAM circuits.

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