JP6702955B2 - Opportunistic for IC test structures and/or e-beam target pads into areas that would be used for filler cells, tap cells, decap cells, scribe lines and/or dummy fills and product IC chips containing them. Placement - Google Patents

Description

Cross-reference of related applications

This application claims priority from US Patent Application No. 14303578 filed on June 12, 2014, which is assigned to US Patent Application No. 14303578 filed on February 25, 2014. No. 14/190040, which is a continuation-in-part application of US Pat. No. 14/190040, which is a continuation-in-part application of US patent application Ser. This application also claims priority from US Provisional Patent Application No. 62/011161 filed June 12, 2014. All of the above applications are incorporated herein by reference.

The present invention relates to the field of semiconductor integrated circuits and methods for manufacturing and testing such circuits.

“Test structures” on a product wafer (this is not necessary here for the functionality of the circuit, but is not part of the fabrication process or the resulting partially or fully fabricated (Defined as any patterning, designed, configured, or used for wafer/chip monitoring or evaluation) of any of the above has become commonplace in the last decade. Conventionally, such test structures are placed in the scribe line area between the active dies. See, for example, Non-Patent Document 1.

F. Duan et al., U.S. Pat. No. 5,697,097 ("Test Structures in Unused Areas of Semiconductor Integrated Circuits and Methods for Cells"), describes a test and wafer to pad test, and a product to test and wafer to pad test, and a product to wafer test. is doing.

S. U.S. Pat. No. 5,837,83 to Jansen et al. ("Semiconductor integrated test structures for electron beam inspection of semiconductor wafers") is located within a pre-designed large area of structure of a product IC.

While these and other known techniques for placing test structures on a product wafer have yielded useful results, they are still less than ideal. Specifically, the area available in the scribe line of a product wafer is severely limited and can only accommodate certain types of test structures. Furthermore, both the method within the scribe line and the method under the probe pad result in the test structure being located far from the most important active circuit configuration area, thus accurately representing the processing environment of the active circuit configuration. There is a drawback that it may not be done. Although US Pat. No. 6,037,037 can potentially alleviate this problem, the cost of the required large designated test area (see US Pat. No. 5,968,698, areas 44-45 in FIG. 5) is too unacceptable. And consumes valuable active die area.

US registered patent No. 7223616B2 US registered patent No. 7679,083B2

Hess, Christopher, et al. , "Scribe characterisation vehicle test chip for ultra fast product monitoring," IEEE International Conference on Microelectronics Tactics.

The present invention discloses several techniques for improving test structure occupancy on a product IC with little or no sacrifice in active die area.

According to one aspect of the invention, a "filler cell" (which is located within the active circuit configuration area to prevent/mitigate wiring congestion and/or equalize cell density, (Defined as non-functional cells) with self-contained test structures that do not require additional areas or interconnects. Current standard cell layouts typically use such filler cells to reduce wiring congestion. For example, Cong, J. et al. , Et al. "Optimizing routing in large-scale mixed-size placement," ASP-DAC, 2013; and Menezes, C.; , Et al. See "Design of regular layouts to improve predictability," Proceedings of the 6th IEEE International Caribbean Conference on Devices, Circuits 6th. C. International Publication No. 2009/090516A1 (“Monitor Cell and Monitor Cell Placement Method”) by Mayor refers to a filler cell as a “monitor cell” (see FIG. 5, step 540). ), but the proposed monitor cell is too large to fit in the space of the filler cell, and more importantly added for integration into the scan chain. Need interconnection. Examples of test-ready filler cells suitable for use in connection with the present invention are disclosed in the above-referenced US provisional patent application and Figures 11-32 of this application.

According to another aspect of the invention, a decap: decoupling capacity cell is modified to incorporate one or more self-contained test structures. The use of such decap cells is known in the art. For example, X. Meng, et al. , "Novel Decoupling Capacitor Designs for sub-90 nm CMOS Technology," Proceedings of the 7th IEEE International Symposium on Quality Err.

In another aspect of the invention, a well tap (tap) cell is modified to incorporate one or more self-contained test structures. The use of such tap cells is well known in the art. For example, U.S. Pat. No. 6,388,315 ("Tap connections for circuits with leakage support capability"), incorporated herein by reference, Jungeburt, T. et al. , Et al. , 2010, "A modular design flow for very large design space exploration," see Figure 4 ("add well tap cells"). An example of such a test-ready tap cell is disclosed in the above-mentioned US provisional patent application.

According to yet another aspect of the invention, a test structure pattern is placed in a "dummy fill" region (see U.S. Pat. No. 7,137,092 B2, which is incorporated herein by reference).

U.S. Pat. No. 7,217,579 ("Voltage contrast test structure") and U.S. Pat. No. 5,096,049, both of which are incorporated herein by reference, disclose the use of voltage contrast test structures in the scribe line region of a semiconductor wafer. .. Another aspect of the invention involves the use of scribe line regions for insertion of additional test structures. Such scribe line areas are not recommended for use within the active die area of a product wafer due to actual performance issues or requirements for compatibility with existing DRC (design rule checking) flows. It may be used to advantage to implement test structures that may or may be prohibited. Examples of such deprecated/forbidden test structures include one or more intentional interlayer inconsistencies. , Structures below design rules or canary structures, or structures whose density or patterning cannot meet the requirements in the active die area, eg with respect to e-beam compatible canary test structures. Reference is made to the invention of abandoned U.S. Patent Application No. 2009-0102501A ("Test structures for e-beam testing of systematic and random defects in integrated inventions", incorporated herein by reference). In form, all or most of the die-to-die scribe line area of the product IC wafer of the present invention is provided with a voltage contrast test structure that is deprecated or prohibited for use in the active die area.

Another aspect of the invention is to attach a test pad (one type of "test structure" as defined above) to the dummy fill, filler cell, decap cell and/or tap cell locations described above. With (and/or within) these opportunistic insertions. Such a test pad preferably comprises a charged particle (eg e-beam) target, which is preferably in the range of 1 to 10 times the smallest resolvable feature size at a node of a given technology. Although sized to a relatively small size, the test pad may also include a micro or nanoprobe probeable contact pad. Such test pads may be positioned above the associated test structure, adjacent to the associated test structure, and connected to non-adjacent test structures on the same layer. , Or an associated test structure on one or more underlying layers.

Another aspect of the invention is one, two, of opportunistically inserted test structures of the type described above, with or without conventional scribe lines and underpad test structures. It relates to an IC having three or four and an IC layout. Yet further aspects of the invention are: CAD methods for forming IC layouts as described above; fabrication processes that at least partially utilize information obtained from opportunistically inserted test structures according to the invention; And an IC manufactured by the above process.

Thus, in general, but not intended to be limiting, certain aspects of the invention include, for example: at least 10, 20, 30 or more, at least 50, 75, 100 or more of the present invention. It relates to a product IC including a contacted cell. The product IC includes: each of the rows including a plurality of logic cells; and at least half, 3/4 or more than 3/4 of the rows in a filler, decap or tap cell position (and/or these It is characterized by including a test structure (in a cell). The product IC further includes a plurality of dummy fill test structures (including, but not limited to, test pads) mounted in dummy fill regions that at least partially overlap the rows. The dummy fill test structure may be present on any patterning layer, especially one or more metal layers.

Each test structure is preferably self-contained so that no wiring area needs to be used for on-chip connections. In other words, with this self-contained aspect of the invention, replacement of the filler/decap/tap cell with the test cell/structure of the invention does not affect the available wiring area. In some embodiments, the self-contained test structure may be formed in the footprint of multiple adjacent fillers, decaps or tap cells, and thus larger and/or irregularly shaped self-contained test structures. A structure is feasible. The product IC is a test structure configured for e-beam testing, a test structure configured for SEM inspection, a test structure configured for brightfield inspection, (using a microprobe, nanoprobe or probe card). ) It may include a test structure configured for probe contact, or any combination of two, three or four of these.

Also, although not intended to be limiting, in general, other aspects of the invention include, for example, at least 100, 150, at least 20, 30, 40 or more contiguous rows with wiring areas. , A product IC containing a continuous area containing 200 or more adjacent cells. The product IC includes: each row contains a majority (or an excess of 60%, 70%, 80%, etc.) of logic cells; and the continuous area is at least 25 (or 50, 100, 150). (Or more) randomly distributed self-contained test structures, each said self-contained test structure being suitable for a logic cell or filler cell or tap cell of one of said columns It is characterized in that it is positioned at the position which should have been. In some embodiments, at least some of the test structures are contained within a decap cell. The product IC may also include a plurality of self-contained dummy fill test structures, each self-contained dummy fill test structure at least partially overlapping the continuous region, but It is not connected to any of the above logic cells (except for connections). In some embodiments, the dummy fill test structure may occupy more than one interconnect layer. In some embodiments, at least some of the test structures are canary (ie, sub-design rule) test structures and some of the dummy fill test structures are random defect test structures. It is the body. In other embodiments, the test structure may comprise a DR compliant structure configured to test or evaluate systematic failure modes. Further, an embodiment provided with these combinations is also conceivable.

In general, but not intended to be limiting, other aspects of the invention include, for example, at least the following steps: subjecting the IC wafer to an initial fabrication step; opportunistically distributed within the continuous logic portion of the wafer. , Obtaining at least 5 (or 10, 20, 40 or more) self-contained test structures; and based at least in part on the measurements obtained from the test structures. , An IC fabrication process including selectively subjecting the wafer to additional and/or modified fabrication steps. In certain embodiments, the steps of obtaining a measurement include exciting the test structure with charged particles (eg, with an e-beam), inspecting the test structure with a brightfield inspection, SEM inspection with the test structure. Or contacting the test structure by probe probing for electrical measurements. In certain embodiments, selectively subjecting the wafer to an additional fabrication step or physical failure analysis determines whether to rerun one or more of the initial fabrication steps, or This may involve determining whether to perform the additional fabrication steps or discard the wafer.

Also, although not intended to be limiting, in general, according to certain embodiments of the present invention, a process for making a product IC wafer may include, for example, at least the following steps: obtaining an initial product wafer layout; using a computer. And analyzing the initial product wafer layout to identify opportunistic regions (eg, dummy fills, filler cells, tap cells, decap cells) for test structure insertion; Modifying the initial product wafer layout by inserting a plurality of test structures integrally forming at least one distributed DOE across the opportunistic region for; Storing in a computer-readable layout data record the information necessary to fabricate the modified product wafer layout, but not the information required to utilize the mold DOE; and the information from the layout data record to the manufacturer. To enable fabrication of a wafer based on the modified product wafer layout. According to this and other aspects of the invention, such layout modification may be performed during the design flow (i.e., before the end of the design), or during one or more subsequent mask data processing (MDP) steps. Alternatively, it can proceed between both. In accordance with related aspects of the invention, a method for making an IC product chip may include, for example, at least the following steps: a plurality of products having a plurality of implantable test structures integrally forming at least one distributed DOE. Receiving a first product IC wafer comprising an IC die: Receiving data that identifies and makes available at least one of the one or more distributed DOEs; Or utilizing said at least one of a plurality of distributed DOEs to obtain information regarding fabrication of said first product IC wafer; and dicing said first product IC wafer into a plurality of IC product chips. Processing may be included. The method further comprises at least the following additional steps: receiving a second product wafer that is the same as the first product IC wafer; one or more of the distributions on a second product IC wafer. Obtaining information about fabrication of the second product IC wafer using at least one of the mold DOEs; and processing the second product IC wafer into a plurality of IC product chips. .. In accordance with these aspects of the invention, data from the one or more DOEs and/or one or more test structures is used to determine wafer placement decisions, rework decisions, process controls, yield learning, or It may be used in the diagnosis of defects.

Also, although not intended to be limiting, in general, in accordance with another aspect of the invention, a product IC wafer has at least: a number of e-beam excitable test structures (or pads/targets) dispersed therein. Area of the functional product circuitry; and at least its entire scan length (measured in the scan direction) without missing any opportunity for the e-beam scanner to excite any test structure (or pad/target). Multiple e-beam skip regions may be provided to skip 10%, 15% or 20% respectively. The product IC wafer may preferably further include at least one or more empty e-beam scan tracks each extending across the width of the area of the functional product circuitry.

Also, although not intended to be limiting, in general, another aspect of the invention is, for example, of at least: at least 3×3 (or 5×5, 10×10, 20×20 or 50×50, etc.) product dies. An array of product wafers containing the array, wherein a scribe line region separates the product dies. The wafer includes: each product die including a plurality (many) of operable (combined and/or ordered) logic cells that support product functionality; each product die is interspersed with the logic cells. A plurality of test-enabled tap cells, the test-enabled tap cells comprising a self-contained voltage contrast test structure (with or without an e-beam test pad); and each scribe line region having a (corresponding e-beam test pad). Including a plurality of voltage contrast test structures (with or without pads). The product die further comprises: a plurality of test-capable decap cells, each with a self-contained voltage contrast test structure (with or without an e-beam test pad); (with or without a corresponding e-beam test pad) A plurality of test-enabled filler cells, each with a self-contained voltage contrast test structure; and/or a plurality of self-mounted (with or without corresponding e-beam test pads) mounted in a dummy fill region of the product die. A complete voltage contrast test structure may be included. In a particular embodiment, the scribe line region is substantially entirely disposed with a voltage contrast test structure (including an e-beam target pad) of the test structure contained within the scribe line region. Some or the majority contain intentional layer mismatches and/or contain intentional violations of process design rules.

Also, although not intended to be limiting, in general, another aspect of the invention is, for example, at least the following steps: subjecting a product IC wafer to an initial fabrication step; at least 40 (preferably at least 100) self-sufficient. Obtaining e-beam excited measurements from a mold test structure, wherein at least 20 of the test structures are within a continuous logic portion of the wafer (ie, the portion of the wafer that contains functional product logic). Randomly distributed on the wafer, and at least 20 of the test structures are located within the scribe line region of the wafer; and at least partially for measurements taken from the test structures. Accordingly, the present invention relates to an IC fabrication process including selectively subjecting the wafer to additional fabrication steps. In certain preferred embodiments, the step of obtaining the measurement is performed without continuously scanning any substantial portion of the wafer (eg, by sampling a single pixel value or less than 10 pixel values). , Targeting an e-beam target pad located in the scribe line region of the wafer. In certain preferred embodiments, the step of obtaining the measurement selects e-beam target pads located within the continuous logic region of the wafer without continuously scanning any substantial portion of the wafer. Targeting step. In some embodiments, the selectively providing step may include determining whether to re-execute one or more of the initial fabrication steps. Also, in some embodiments, the selectively providing step may include determining whether to perform the additional fabrication steps.

Certain embodiments of the present invention may include electrically probeable test structures, including but not limited to those of the type described in the above US provisional patent applications. , Located within the scribe line area of the product wafer. The electrically probeable test structure may include its own probe pad, or a voltage close to it so that a single pad can function as both a probe pad and an e-beam target pad. One or more pads may be shared with the contrast test structure.

In the following discussion, the cell of the present invention (of FIGS. 11-85 below) is also referred to as “cell” or “means”. For the sake of clarity and clarity, for example, the designation "FIG82 cell" means "a cell having the topology design shown in FIG. 82", while similar to "FIG82 means". Under US Pat. It is understood to include "cells having a structure".

In general, but not by way of limitation, a further aspect of the invention is to provide (i) FIG33A-B cells; FIG34A-B within a contiguous logical region of at least 500 (or 1000, 1500, etc.) cells. Cell; FIG35A-B cell; FIG36A-B cell; FIG37A-B cell; FIG38A-B cell; FIG39A-B cell; FIG40A-B cell; FIG41A-B cell; FIG42A-B cell; FIG43A-B cell; FIG44A-B cell FIG. 45 cell; FIG. 46 cell; FIG. 47 cell; FIG. 48 cell; FIG. 49 cell; FIG. 50 cell; FIG. 51 cell; FIG. 52 cell; FIG. 53 cell; FIG. 54 cell; FIG. 55 cell; FIG. 56 cell; FIG. 57 cell; FIG. 58 cell; FIG. 59 cell; FIG. 60 cell; FIG. 61 cell; FIG. 62 cell; FIG. 63 cell; FIG. 64 cell; FIG. 65 cell; FIG. 66 cell; FIG. 67 cell; FIG. 68 cell; FIG. 69 cell; FIG. 70 cell; FIG. 71 cell; FIG. 72 cell; FIG. 73 cell; FIG. 74 cell; FIG. 75 cell; FIG. 76 cell; FIG78 cell; FIG79 cell; FIG80 cell; FIG81 cell; FIG82 cell; FIG83A-B cell; FIG84 cell; and FIG85 cell, at least some selected number (for example, three, four, five; , 6, 7, etc.) distinct functional cells and (ii) at least one (or 2, 3, 4, etc.) distinct types, and: FIG11 cells; FIG12 cells; FIG. 13 cell; FIG. 14 cell; FIG. 15 cell; FIG. 16 cell; FIG. 17 cell; FIG. 18 cell; FIG. 19 cell; FIG. 20 cell; FIG. 21 cell; FIG. 22 cell; FIG. 23 cell; FIG. 24 cell; FIG. 25 cell; FIG. 26 cell; FIG. 27 cell; FIG. 28 cell; FIG. 30 shows a product integrated circuit including at least 10 test-ready cells selected from the set of FIG30 cells; FIG31 cells; and FIG32 cells. Another aspect of the invention relates to a method for making the IC, for example by instantiating and making at least some selected number of distinct cells selected from the above set.

Also, although not intended to be limiting, in general, a further aspect of the invention is to provide (i) FIG33A-B means; FIG34A within at least 200 (or 500, 1000, etc.) means of contiguous logical regions. -B means; FIG35A-B means; FIG36A-B means; FIG37A-B means; FIG38A-B means; FIG39A-B means; FIG40A-B means; FIG41A-B means; FIG42A-B means; FIG43A-B means; FIG. B means; FIG45 means; FIG46 means; FIG47 means; FIG48 means; FIG49 means; FIG50 means; FIG51 means; FIG52 means; FIG53 means; FIG54 means; FIG55 means; FIG56 means; FIG57 means; FIG58 means; FIG59 means; FIG. 61 means; FIG. 62 means; FIG. 63 means; FIG. 64 means; FIG. 65 means; FIG. 66 means; FIG. 67 means; FIG. 68 means; FIG. 69 means; FIG. 70 means; FIG. 71 means; FIG. 72 means; FIG. 73 means; FIG. 74 means; FIG. 75 means; FIG. 76 means; FIG. 78 means; FIG. 78 means; FIG. 79 means; FIG. 80 means; FIG. 81 means; FIG. 82 means; FIG. 83A-B means; FIG. 84 means; and FIG. 85 means, at least some selected number (two, three, Four, five, etc.) separate "means" (ie corresponding means or "the equivalent" thereof according to 35 U.S.C. 112,6), and (ii) at least one (or two, three) FIG. 11 means; FIG12 means; FIG12 means; FIG12 means; FIG12 means; FIG12 means; FIG12 means; FIG12 means; FIG. 23 means; FIG. 24 means; FIG. 25 means; FIG. 26 means; FIG. 27 means; FIG. 28 means; FIG. 29 means; FIG. 30 means; FIG. 31 means; and FIG. 32 means, at least 10 test response “means” selected from the set consisting of The present invention relates to a product integrated circuit. Another aspect of the invention relates to a method for making an IC as described above, for example by instantiating and making at least a selected number of distinct means selected from the above set. A further aspect of the invention is that at least some selected number (1, 2, 3, 4) of the above defined type of IC and any other optional one or more rechargeable power supplies. And an electronic system (stationary or portable) including components. Also, yet a further aspect of the invention relates to a method for making said IC, eg by instantiating at least some selected number of the “cells” and/or “means” mentioned above.

The exemplary logic and test enabled cells (FIGS. 11-85) avoid the use of tapered devices, thereby avoiding the parametric variability and functional yield loss problems associated with such devices. However, one of ordinary skill in the art will readily understand that equivalent alternative versions of these cells may employ tapered devices and that such alternative tapered versions are within the scope of the present invention. Let's do it.

Another aspect of the invention relates to the use of a tool with a charged particle column (electrons or ions), the main function of which is to find defects on the surface of a semiconductor wafer (ie to act as an inspector). That is). (This description uses the term "e-beam", but it should be understood that this description applies to all charged beams.)

In accordance with one aspect of the invention, we describe a VC checker that samples pixels on the wafer surface. This scanning method differs in principle from all previously designed checkers. In one embodiment, a pixel has a particular designated XY coordinate, and its pixel value (ie, electron beam signal) is used to determine if a defect is present or absent. This can be considered as a 0D inspection, rather than the typical 2D inspection of the prior art.

In one embodiment, the pixels correspond to "pads" in the electronic test structure that are specifically formed for the purpose of finding voltage contrast defects. The beam illuminates the pad for a specified time. Each test structure may have one or more pads (the checker reads one pixel per pad). The test pads may be present on a semiconductor wafer whose pattern is primarily designed as a “test chip” or may be embedded in a “product wafer”.

In one embodiment, each pixel corresponds to a particular location in the semiconductor product layout. These pixels are selected because signal anomalies at these locations on the product are indicative of one or more particular types of defects.

In one embodiment, the stage is held stationary, similar to a "step and scan" inspection. When the pixel value corresponding to a given field of view is sensed, the stage moves to another location where the next set of pixels can be read out.

In one embodiment, the stage is inspected by moving during scanning of the pixels and refracting the e-beam accordingly to compensate for stage movement.

In one embodiment, the duration of pixel readout at each location is dynamic for each pixel, that is, the duration of holding the beam at that location is preferred, depending on the test structure or product circuit being inspected at each point. Changes to.

In one embodiment, the beam size on the wafer is not fixed and changes dynamically for each position read. This type of beam shaping is similar to that used in e-beam writer. The beam size can be optimized for each structure by setting the spot size for each structure. This optimization can typically maximize the signal-to-noise ratio of the inspection. Another aspect of the invention relates to the design of a voltage-contrast device-under-test (“VC DUT”) having a test pad, which is a complete structure with very few pixels (less than 10). Only test. The VC DUT may have a test pad whose size and shape simultaneously accepts a non-circular incident e-beam while simultaneously maximizing SNR. The beam may also be square shaped to fit square shaped pads as well. The pad has a beam with an asymmetric aspect ratio (X/Y length ratio) of greater than 3 (eg, a DUT with an X dimension of 100 nm and a Y dimension of 300-600 nm has an aspect ratio of 3:1, 4:1, 5:1). May be configured to capture).

These and other aspects, features and advantages of the present invention are illustrated in the following series of drawings.

FIG. 1 is a conceptual diagram of an exemplary section of a standard cell layout, which layout includes logic cells (L), filler cells (F) and tap cells (T) arranged in a plurality of rows and the columns described above. It includes a wiring region between them and a decap cell (dC) in the vicinity. FIG. 2 shows the same layout as FIG. 1 with the dummy fill regions shown in the first layer. FIG. 3 shows the same layout as FIGS. 1 and 2, with one or more dummy fill regions shown in the second layer. FIG. 4 shows an exemplary layout according to the present invention, in which the filler cells, tap cells, decap cells and dummy fill regions of FIG. 3 have been replaced with self-contained test structures. FIG. 5 is a conceptual diagram of one preferred form of a standard cell layout (for use in accordance with the present invention). FIG. 6 shows an exemplary layout according to the present invention, in which the filler cells, decap cells, tap cells and dummy fill regions of FIG. 5 have been replaced with self-contained test structures. FIG. 7 illustrates an exemplary process flow for opportunistic test structure insertion, according to certain embodiments of the invention. FIG. 8 shows an exemplary process flow for utilizing the opportunistically inserted test structure (by FIG. 7 or 10) to produce useful results. FIG. 9 is a conceptual diagram of a portion of an exemplary wafer or die, where one or more opportunistically inserted test pads and/or structures allow for faster e-beam scanning. Of empty tracks and/or arranged to create one or more skip regions. FIG. 10 illustrates an alternative exemplary process flow for opportunistic test structure insertion, according to certain embodiments of the invention. FIG. 11 shows a first exemplary test enabled tap cell. FIG. 12 shows a first exemplary test-ready filler cell. FIG. 13 shows another exemplary test-enabled filler cell. FIG. 14 illustrates another exemplary test enabled tap cell. FIG. 15 shows another exemplary test-enabled filler cell. FIG. 16 illustrates another exemplary test enabled tap cell. FIG. 17 shows another exemplary test-enabled filler cell. FIG. 18 shows another exemplary test-enabled filler cell. FIG. 19 shows another exemplary test enabled tap cell. FIG. 20 shows another exemplary test-enabled filler cell. FIG. 21 shows another exemplary test-enabled filler cell. FIG. 22 shows another exemplary test-enabled filler cell. FIG. 23 illustrates another exemplary test enabled tap cell. FIG. 24 shows another exemplary test-enabled filler cell. FIG. 25 shows another exemplary test enabled tap cell. FIG. 26 shows another exemplary test-enabled filler cell. FIG. 27 shows another exemplary test enabled tap cell. FIG. 28 shows another exemplary test-enabled filler cell. FIG. 29 illustrates another exemplary test enabled tap cell. FIG. 30 shows another exemplary test enabled tap cell. FIG. 31 shows another exemplary test-enabled filler cell. FIG. 32 shows another exemplary test-enabled filler cell. 33A-85 show exemplary cells from an exemplary standard cell library. 33A, B respectively show abutting left and right portions of the first exemplary standard cell. 34A, B respectively show abutting left and right portions of another exemplary standard cell. 35A, B respectively show abutting left and right portions of another exemplary standard cell. 36A, B respectively show abutting left and right portions of another exemplary standard cell. 37A, B respectively show abutting left and right portions of another exemplary standard cell. 38A and 38B respectively show abutting left and right portions of another exemplary standard cell. 39A, B respectively show abutting left and right portions of another exemplary standard cell. 40A, B respectively show abutting left and right portions of another exemplary standard cell. 41A, B respectively show abutting left and right portions of another exemplary standard cell. 42A, B respectively show abutting left and right portions of another exemplary standard cell. 43A, B respectively show abutting left and right portions of another exemplary standard cell. 44A, B respectively show abutting left and right portions of another exemplary standard cell. FIG. 45 shows another exemplary standard cell. FIG. 46 shows another exemplary standard cell. FIG. 47 shows another exemplary standard cell. FIG. 48 shows another exemplary standard cell. FIG. 49 shows another exemplary standard cell. FIG. 50 shows another exemplary standard cell. FIG. 51 shows another exemplary standard cell. FIG. 52 shows another exemplary standard cell. FIG. 53 shows another exemplary standard cell. FIG. 54 shows another exemplary standard cell. FIG. 55 shows another exemplary standard cell. FIG. 56 shows another exemplary standard cell. FIG. 57 shows another exemplary standard cell. FIG. 58 shows another exemplary standard cell. FIG. 59 shows another exemplary standard cell. FIG. 60 shows another exemplary standard cell. FIG. 61 shows another exemplary standard cell. FIG. 62 shows another exemplary standard cell. FIG. 63 shows another exemplary standard cell. FIG. 64 shows another exemplary standard cell. FIG. 65 shows another exemplary standard cell. FIG. 66 shows another exemplary standard cell. FIG. 67 shows another exemplary standard cell. FIG. 68 shows another exemplary standard cell. FIG. 69 shows another exemplary standard cell. FIG. 70 shows another exemplary standard cell. FIG. 71 shows another exemplary standard cell. FIG. 72 shows another exemplary standard cell. FIG. 73 shows another exemplary standard cell. FIG. 74 shows another exemplary standard cell. FIG. 75 shows another exemplary standard cell. FIG. 76 shows another exemplary standard cell. FIG. 77 shows another exemplary standard cell. FIG. 78 shows another exemplary standard cell. FIG. 79 shows another exemplary standard cell. FIG. 80 shows another exemplary standard cell. FIG. 81 shows another exemplary standard cell. FIG. 82 shows another exemplary standard cell. 83A, B respectively show abutting left and right portions of another exemplary standard cell. FIG. 84 shows another exemplary standard cell. FIG. 85 shows another exemplary standard cell. FIG. 86 illustrates prior art “step and scan” and “swathing” techniques. FIG. 87 shows a prior art beam scanning/shaping device. 88 shows an example of a beam shape that can be realized using the column of FIG. FIG. 89 shows an exemplary semiconductor wafer, which is typically circular and is divided into multiple identical dies, with all test structures located within the scribe line region of the die. The target case is shown. FIG. 90 shows a series of test structures in which the pads are laid out in a row, with the electron beam spot scanning the entire pad by relative movement of the wafer relative to the spot. FIG. 91 shows an electron beam spot shaped non-circularly to fit the size and shape of the pad in order to maximize the electron flow delivered to the pad. FIG. 92 shows a pad shape sized according to the amount of charge that needs to be delivered to the test structure, with the test structure requiring more charge having a longer pad along the scan direction of the beam. , Which increases the beam dwell time on the pad. FIG. 93 shows that the beam moves quickly but at a constant speed when there is a long section where there is no pad to be charged, and more pad is charged to the test structure in the area where the pad is arranged. We will show a scenario of moving more slowly so that FIG. 94 shows the test structure laid out on both sides of the pad so that a single pass of the beam on the wafer can be used to scan more test structures. FIG. 95 illustrates how solid pads can be divided into finer lines or alternative shapes so that the pad layout complies with semiconductor processing design rules. FIG. 96 illustrates a “net gray” pad for use with certain embodiments of the invention. FIG. 97 is a conceptual diagram of one embodiment of a VC DUT in accordance with certain aspects/embodiments of the present invention. FIG. 98 is a conceptual diagram of another embodiment of a VC DUT according to a particular aspect/embodiment of the invention. FIG. 99 is a conceptual diagram of another embodiment of a VC DUT according to a particular aspect/embodiment of the invention.

FIG. 1 is a conceptual diagram of an exemplary section of a standard cell layout, the layout of which includes logic cells (L), tap cells (T) and filler cells (F) arranged in multiple rows and columns of the above. Includes wiring channels between and decap cells (dC) in the vicinity. As shown, the overall distribution of decaps, taps and filler cells within this exemplary section is irregular and does not follow any well-defined pattern or symmetry. (A person skilled in the art will readily recognize that this illustration is conceptual and is not intended to represent the actual layout itself, but only to illustrate the principles of the invention. In fact, one of ordinary skill in the art will appreciate that tap cells are typically one size and are present at regular or nearly regular intervals. Similarly, those of skill in the art will recognize that decap cells can be sized to fit within standard cell rows, can be located within standard cell rows, and are often sized and positioned as such. Will.

FIG. 2 shows the same prior art layout as FIG. 1, but with a dummy fill region shown in the first layer. These dummy fill regions are shown as shaded regions and may have regular (eg rectangular) or irregular shapes, as shown. The most useful dummy fill regions in accordance with the present invention are typically on the third and above metal layers (eg, M3, M4, M5, M6), but one or more active poly layers. It may be on a lower metal layer, such as a layer and/or a previous layer, or on a local interconnect. (Those skilled in the art will understand that the illustration of the dummy fill region in FIG. 2 is conceptual, as the dummy fill region is typically much larger in area than one or a few standard cells. Will be done.)

FIG. 3 is a conceptual view of the same layout as FIGS. 1 and 2, but one or more dummy fill regions are shown in the second layer. The dummy fill region of this second layer is shown in a scaly pattern.

FIG. 4 is a conceptual diagram of an exemplary layout based on the layout of FIG. 3 and illustrates certain aspects of the present invention. As illustrated in FIG. 4, the filler cell (F) and the tap cell (T) are replaced with a test structure (TS4, TS5, TS6, TS7, TS8, TS9, TS10) and a decap cell (dC). Are replaced with test-capable decap cells (dC-T) and the dummy fill regions are replaced with test structures (TS1, TS2, TS3).

FIG. 5 is a conceptual diagram of a preferred form of a standard cell layout suitable for use in accordance with the present invention. The figure shows a relatively modern style in which multiple rows of cells abut and the wiring area covers the entire cell. Although not shown, the wiring regions do not have to have a regular shape and need not be oriented in a direction parallel to the rows.

FIG. 6 shows that the filler cell (F), tap cell (T), decap cell (dC) and dummy fill (shaded) area of FIG. 5 are self-contained test structures (TS, dC-T and shaded, respectively). 3 shows an exemplary layout according to the present invention, replaced by a region).

One of ordinary skill in the art will recognize that there are numerous options for opportunistically instantiating a particular test structure in accordance with the present invention.

Product ICs according to the present invention are adapted for in-line systematic defect inspection by brightfield and/or e-beam (or other charging) of product layout patterns that are most susceptible to systematic defects, including multi-patterned structures. Including test structure. The test structure may preferably include a canary structure (ie, a sub-design rule structure used to probe process layout limits).

The product IC according to the present invention is also for in-line random defect inspection with bright field of product-like patterns and/or e-beam tools regarding the most likely defects such as single line openings and the most likely via hole opening position. Test structures adapted to (including canary structures)) may also be included.

The product IC according to the present invention also has in-line metrology features such as overlay/misalignment, poly CD, MOL CD, via hole bottom CD, metal CD, and product specific patterns and structures for extracting height, dielectric height, etc. Test structures adapted for use may also be included and may be testable electrically (eg for overlays, linear CDs and profiles) and/or by scanning electron microscopy.

The product IC according to the present invention may also include a Physical Failure Analysis (PFA) structure for a systematic failure with a high probability of occurrence, wherein the PFA includes a product-specific layout pattern (canary structure). ), and pads for probe probing.

The product IC according to the present invention may also include any combination of the above or other useful test structures.

For test-ready decap cells, the preferred test structure is the M1 structure for single linear aperture inspection.

The key goals of designing a test structure according to certain embodiments of the invention are: (1) the test structure must not affect the printability of the active areas (ie standard cells or interconnects); And/or (2) the test structure must be typical of active cell properties (printability and electrical characteristics).

As described in detail below, FIGS. 11-32 show a series of exemplary VC DUTs suitable for use in certain embodiments of the present invention.

Reference is made to FIG. 11 showing a first exemplary test enabled tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Merged Via Hole Configuration (Merged Via). configuration) shorts to nearby metal/local interconnects. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded lower layer metal→grounded pad=light pad. .. (It will be appreciated by those skilled in the art that the e-beam inspection can be configured to produce dark or light states for floating polygons. The latter configuration is typically relatively stable. (Thus, while this configuration is envisioned for the embodiments of the present disclosure, it will be understood by those of ordinary skill in the art that the present invention is useful in either configuration.)

Reference is made to FIG. 12, which shows a first exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Underlayer of coupled via hole configuration. Short circuit to metal. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded lower layer metal→grounded pad=light pad. ..

Reference is made to FIG. 13 showing another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Underlayer of coupled via hole configuration. Short circuit to metal. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded lower layer metal→grounded pad=light pad. ..

Reference is made to FIG. 14 showing another exemplary test enabled tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Apertures in coupled via hole configurations. In the configuration shown, pass response = grounded metal = light colored pad, while fail response = failure to connect to grounded lower layer metal → floating pad = dark colored pad It is a pad.

Reference is made to FIG. 15 showing another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Apertures in coupled via hole configurations. In the configuration shown, pass response = grounded metal = light colored pad, while fail response = failure to connect to grounded lower layer metal → floating pad = dark colored pad It is a pad.

Reference is made to FIG. 16 showing another exemplary test enabled tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: metal near via hole. / Short to local interconnect. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded lower layer metal→grounded pad=light pad. ..

Reference is made to FIG. 17 showing another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: via hole, underlying metal Short circuit against. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded lower layer metal→grounded pad=light pad. ..

Reference is made to FIG. 18 showing another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: via hole, underlying metal Short circuit against. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded lower layer metal→grounded pad=light pad. ..

Reference is made to FIG. 19 showing another exemplary test enabled tap cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: contact short to bottom layer. In the configuration shown, pass response=floating metal=dark pad, while fail response=grounded bottom layer→grounded pad=light pad.

Reference is made to FIG. 20 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: contact short to bottom layer. In the configuration shown, pass response=floating metal=dark pad, while fail response=grounded bottom layer→grounded pad=light pad.

Reference is made to FIG. 21 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: contact short to bottom layer. In the configuration shown, pass response=floating metal=dark pad, while fail response=grounded bottom layer→grounded pad=light pad.

Reference is made to FIG. 22 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: contact short to bottom layer. In the configuration shown, pass response=floating metal=dark pad, while fail response=grounded bottom layer→grounded pad=light pad.

Reference is made to FIG. 23 showing another exemplary test enabled tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Metal with metal end Short circuit to the side. In the configuration shown, pass response=floating metal=dark pad, while fail response=grounded metal layer→grounded pad=light pad.

Reference is made to FIG. 24 showing another exemplary test-enabled filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Metal with metal end Short circuit to the side. In the configuration shown, pass response=floating metal=dark pad, while fail response=grounded metal layer→grounded pad=light pad.

Reference is made to FIG. 25 showing another exemplary test enabled tap cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: metal aperture. In the configuration shown, pass response = grounded metal = light colored pad, while fail response = failed connection to grounded metal → floating pad = dark colored pad. Is.

Reference is made to FIG. 26 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: metal aperture. In the configuration shown, pass response = grounded metal = light colored pad, while fail response = failed connection to grounded metal → floating pad = dark colored pad. Is.

Reference is made to FIG. 27 showing another exemplary test enabled tap cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Metal shorts to metal corners. .. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded metal layer→grounded pad=light pad. ..

Reference is made to FIG. 28 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Metal shorts to metal corners. .. In the configuration shown, pass response=floating metal=dark pad, while fail response=short to grounded metal layer→grounded pad=light pad. ..

Reference is made to FIG. 29 showing another exemplary test enabled tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: Short circuit to contacts. In the configuration shown, pass response=floating contacts=dark pad, while fail response=short to grounded contact layer→grounded pad=light pad. ..

Reference is made to FIG. 30 showing another exemplary test enabled tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: contacts of different color contacts. Short circuit to the end. In the configuration shown, pass response=floating contacts=dark pad, while fail response=short to grounded contact layer→grounded pad=light pad. ..

Reference is made to FIG. 31 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: short-circuit to contact short-circuit. In the configuration shown, pass response=floating contacts=dark pad, while fail response=short to grounded contact layer→grounded pad=light pad. ..

Reference is made to FIG. 32 showing another exemplary test-enabled filler cell. The cell contains an E-shaped voltage contrast target/pad and is configured for e-beam (or other charged particle) in-line testing to detect the following failure modes: short-circuit to contact short-circuit. In the configuration shown, pass response=floating contacts=dark pad, while fail response=short to grounded contact layer→grounded pad=light pad. ..

33A-85 show exemplary cells from a standard cell library. These cells are compatible with the test-ready filler cells of Figures 11-32 above. These exemplary standard cells are detailed in the accompanying Figures 33A-85. The function of each cell shown is described below. FIG. 33A provides a legend of layers for these figures, the layers being illustrated as follows: metal-1/first mask (11); metal-1/second Mask (12); Via hole-0 (13); Via hole-1 (14); Metal-2 (15); Poly contact (16); Active (17); Active contact (18); Poly (19); Poly cut ( 20); and active cut (21). These cells are described in, for example: S. Saika, "Standard cell library and semiconductor integrated circuit," U.S. Pat. No. 8302057B2 (incorporated herein by reference); J. J. Lee, et al. Standard Cell Placement Technology for Double Patterning Technology", U.S. Patent Application No. 20130036397A1, which is also incorporated herein by reference; D. D. Sherlkar, "Dell Sherlekar, "Dr. HH Nguyen, et al., "7-tracks standard cell library," U.S. Pat. No. 6,938,226, which is also incorporated herein by reference. P. Penzes, et al., "High-speed low-leakage-power standard cell library," U.S. Pat. No. 8,079,008, which is also incorporated herein by reference. , Et al., "Standard cell libraries and integrated circuits including standard cells," U.S. Pat. No. 8,174,052 (also incorporated herein by reference); and OM K. Law, et al. Instantiation and use in methods and configurations known in the art, as described in Standard cell architecture and methods with variable design rules, US Pat. No. 8,173,491, which is also incorporated herein by reference. It will be understood by those skilled in the art that it is configured to do so. Moreover, as those skilled in the art will recognize, the dummy poly stripes shown beyond the right and left edges of each cell boundary are used for DRC testing and are therefore considered part of the cell itself. must not. Product ICs constructed using the library of the present invention are preferably fabricated using a commercially available 14 nm fabrication process.

Reference is made to Figures 33A,B, which show abutting left and right portions of the first exemplary standard cell, respectively. This cell implements the logic function of a scan-ready d-flip-flop with the output set and inverted at a drive strength of 3.

34A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements the logic function of a scan-enabled d-flip-flop with the output set and inverted at a drive strength of 2.

35A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements the logic function of a scan-ready d-flip-flop with the output set and inverted at a drive strength of one.

Reference is made to Figures 36A,B, which show the abutting left and right portions of another standard cell, respectively. This cell implements a scan-ready d-flip-flop set to a drive strength of 3.

Reference is made to FIGS. 37A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements the logic function of a scan-enabled d-flip-flop set to a drive strength of 2.

38A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements a scan-ready d-flip-flop set to a drive strength of 1.

39A, B, showing the abutting left and right portions of another standard cell, respectively. This implements the logic function of a scan-enabled d-flip-flop with a reset and inverted output at drive strength 3.

Reference is made to FIGS. 40A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements a scan-ready d-flip-flop with a reset and inverted output at a drive strength of 2.

41A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements a scan-ready d-flip-flop with a reset and inverted output at a drive strength of 1.

42A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements the logic function of a scan-enabled d-flip-flop reset to a drive strength of 3.

Reference is made to FIGS. 43A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements a scan-ready d-flip-flop reset to a drive strength of two.

Reference is made to Figures 44A,B, which show the abutting left and right portions of another standard cell, respectively. This cell implements the logic function of a scan-ready d-flip-flop reset to a drive strength of one.

Reference is made to FIG. 45 showing another standard cell. This cell implements the logic function of a latch set and reset at drive strength 3.

Reference is made to FIG. 46 showing another standard cell. This cell implements the logic function of a latch set and reset at a drive strength of two.

Reference is made to FIG. 47 showing another standard cell. This cell implements the logic function of a latch set and reset at a drive strength of one.

Reference is made to FIG. 48 showing another standard cell. This cell implements the logic function of the latch set at drive strength 3.

Reference is made to FIG. 49 showing another standard cell. This cell implements the logic function of a latch set at a drive strength of 2.

Reference is made to FIG. 50 showing another standard cell. This cell implements the logic function of the latch set at drive strength one.

Reference is made to FIG. 51 showing another standard cell. This cell implements the logic function of a latch reset at drive strength 3.

Reference is made to FIG. 52 showing another standard cell. This cell implements the logic function of a latch reset at drive strength 2.

Reference is made to FIG. 53 showing another standard cell. This cell implements the logic function of a latch reset at a drive strength of one.

Reference is made to FIG. 54 showing another standard cell. This cell implements the logic function of a latch with an inverted output at drive strength 4.

Reference is made to FIG. 55 showing another standard cell. This cell implements the logic function of a latch with an inverted output at drive strength 3.

Reference is made to FIG. 56 showing another standard cell. This cell implements the logic function of a latch with an inverted output at drive strength two.

Reference is made to FIG. 57 showing another standard cell. This cell implements the logic function of a latch with an inverted output at a drive strength of one.

Reference is made to FIG. 58 showing another standard cell. This cell implements the logic function of a latch with an inverted output at drive strength 3.

Reference is made to FIG. 59 showing another standard cell. This cell implements the logic function of a latch with an inverted output at drive strength two.

Reference is made to FIG. 60 showing another standard cell. This cell implements the logic function of a latch with an inverted output at a drive strength of one.

Reference is made to FIG. 61 showing another standard cell. This cell implements the logic function of a latch with a clock set, reset and inverted at a drive strength of 3.

Reference is made to FIG. 62 showing another standard cell. This cell implements the logic function of a latch with a clock set, reset and inverted at a drive strength of two.

Reference is made to FIG. 63 showing another standard cell. This cell implements the logic function of a latch with a clock set, reset and inverted at a drive strength of one.

Reference is made to FIG. 64 showing another standard cell. This cell implements the logic function of a latch with a clock set and inverted at a drive strength of 3.

Reference is made to FIG. 65 showing another standard cell. This cell implements the logic function of a latch with a clock set and inverted at a drive strength of two.

Reference is made to FIG. 66 showing another standard cell. This cell implements the logic function of a latch with the clock set and inverted at a drive strength of one.

Reference is made to FIG. 67 showing another standard cell. This cell implements the logic function of a latch with a clock reset and inverted at a drive strength of three.

Reference is made to FIG. 68 showing another standard cell. This cell implements the logic function of a latch with a clock reset and inverted at a drive strength of two.

Reference is made to FIG. 69 showing another standard cell. This cell implements the logic function of a latch with a clock reset and inverted at a drive strength of one.

Reference is made to FIG. 70 showing another standard cell. This cell implements the logic function of a latch with reset, inverted clock and inverted output at drive strength 3.

Reference is made to FIG. 71 showing another standard cell. This cell implements the logic function of a latch with reset, inverted clock and inverted output at drive strength 2.

Reference is made to FIG. 72 showing another standard cell. This cell implements the logic function of a latch with reset, inverted clock and inverted output at drive strength one.

Reference is made to FIG. 73 showing another standard cell. This cell implements the logic function of a latch with inverted clock and inverted output at drive strength 4.

Reference is made to FIG. 74 showing another standard cell. This cell implements the logic function of a latch with inverted clock and inverted output at drive strength 3.

Reference is made to FIG. 75 showing another standard cell. This cell implements the logic function of a latch with an inverted clock and an inverted output at a drive strength of 2.

Reference is made to FIG. 76 showing another standard cell. This cell implements the logic function of a latch with an inverted clock and an inverted output at a drive strength of one.

Reference is made to FIG. 77 showing another standard cell. This cell implements the logic function of a latch with a clock inverted at a drive strength of 3.

Reference is made to FIG. 78 showing another standard cell. This cell implements the logic function of a latch with a clock inverted at a drive strength of two.

Reference is made to FIG. 79 showing another standard cell. This cell implements the logic function of a latch with a clock inverted at a drive strength of one.

Reference is made to FIG. 80 showing another standard cell. This cell implements the logic function of a 2-input 3-state multiplexer at a drive strength of 4.

Reference is made to FIG. 81 showing another standard cell. This cell implements the logic function of a 2-input 3-state multiplexer at a drive strength of 2.

Reference is made to FIG. 82 showing another standard cell. This cell implements the logic function of a 2-input 3-state multiplexer at a drive strength of 1.

Reference is made to FIGS. 83A, B, showing the abutting left and right portions of another standard cell, respectively. This cell implements the logic function of a 2-input 3-state multiplexer with an output inverted at a drive strength of 4.

Reference is made to FIG. 84 showing another standard cell. This cell implements the logic function of a 2-input 3-state multiplexer with the output inverted at a drive strength of 2.

Reference is made to FIG. 85 showing another standard cell. This cell implements the logic function of a 2-input 3-state multiplexer with an inverted output at a drive strength of 1.

As will be appreciated by those skilled in the art, the exemplary flip-flop, latch and mux designs illustrated in FIGS. 33A-85 show significant improvements (eg, at least one (Reduction of poly stripes) has been achieved.

FIG. 86 illustrates prior art “step and scan” and “swathing” techniques.

FIG. 87 shows a prior art beam scanning/shaping device.

88 shows an example of a beam shape that can be realized using the column of FIG.

FIG. 89 shows an exemplary semiconductor wafer, which is typically circular and is divided into multiple identical dies, with all test structures located within the scribe line region of the die. Shows the target case.

FIG. 90 shows a series of test structures in which the pads are laid out in a row, with the electron beam spot scanning the entire pad by relative movement of the wafer relative to the spot.

FIG. 91 shows an electron beam spot shaped non-circularly to fit the size and shape of the pad in order to maximize the electron flow delivered to the pad.

FIG. 92 shows another view of a pad shape sized according to the amount of charge that needs to be delivered to the test structure, with the test structure requiring more charge being along the scan direction of the beam. And have a longer pad, which increases the beam dwell time on the pad.

FIG. 93 shows that the beam moves quickly but at a constant speed when there is a long section where there is no pad to be charged, and more pad is charged to the test structure in the area where the pad is arranged. We will show a scenario of moving more slowly so that

FIG. 94 shows the test structure laid out on both sides of the pad so that a single pass of the beam on the wafer can be used to scan more test structures.

FIG. 95 illustrates how a solid pad can be divided into finer lines or alternative shapes so that the pad layout complies with semiconductor processing design rules. Referring now to FIG. FIG. 96 shows a VC DUT sized and shaped to accept a non-circular incident e-beam for readout in a single spot measurement, where the pad groups have only every other line connected to the DUT. The remaining lines are either floating or connected to ground so that their polarity is designed to be the opposite of that of a functional DUT.

For a functioning DUT, the lines of the pad will appear as alternating light/dark colors, while for a non-functioning DUT (ie a failed DUT), are the pads all light color? , Or all dark. Here, the advantage is that the "net" gray levels for all non-defective DUTs are virtually always the same, allowing the image computer to use the same threshold for detection of all defective DUTs. It is a point. This simplifies the software algorithms and hardware of the image computer.

Reference is now made to FIG. 97, which is a conceptual diagram of one embodiment of a VC DUT in accordance with certain aspects of the invention. The pad uses a large spot size e-beam tool to measure a single pixel (ie a single analog readout) or N analog values at the same location (ie a binary of N samples to improve SNR). Can be used for averaging).

The beam and pad are designed to have a somewhat identical footprint. In this case, the X/Y aspect ratio is ˜1. The beam is square shaped to fit the pad, but may be similarly sized circular. Although the figure shows four pads, the invention applies equally to one or more pads.

Reference is made to FIG. 98, which is a conceptual diagram of another embodiment of a VC DUT in accordance with certain aspects of the invention. The pad uses a large spot size e-beam tool to measure a single pixel (ie a single analog readout) or N analog values at the same location (ie a binary of N samples to improve SNR). Can be used for averaging). Overall, the pads and beams have similar footprints on the wafer. However, to accommodate asymmetric beams (X/Y aspect ratio>3) while meeting semiconductor layout design rules, pads are divided into arrays of narrow horizontal lines. Although the figure shows one pad, the invention applies to one or more pads as well.

Reference is made to FIG. 99, which is a conceptual diagram of another embodiment of a VC DUT in accordance with certain aspects of the invention. The pad is optimized for a linear beam. The X/Y aspect ratio of the pad and beam is greater than 3. The pads are read like a barcode scanner, with each pad having a polarity of less than 10 pixels. Although the figure shows four pads, the invention applies equally to one or more pads.

Claims (20)

At least the following steps:
Subjecting the product IC wafer to an initial fabrication step;
Obtaining e-beam excitation measurements from a plurality of test structures on the wafer without performing continuous scanning, the e-beam pads associated with each of the test structures comprising a plurality of electrically Obtaining said measurement selectively targeting an e-beam pad by selectively sampling less than 10 pixels from the e-beam pad comprising a logic device with connected elongated metal segments ; and said test. An IC fabrication process comprising the step of selectively subjecting the wafer to additional fabrication steps based at least in part on measurements obtained from a structure. The IC fabrication process of claim 1, wherein obtaining the measurement comprises selectively targeting an e-beam target pad having an asymmetric aspect ratio. The IC fabrication process of claim 1, wherein obtaining the measurement involves obtaining only a single pixel measurement from each of the targeted e-beam pads. The IC fabrication process of claim 1, wherein the selectively providing step comprises the step of determining whether to rerun one or more of the initial fabrication steps. The IC fabrication process of claim 1, wherein the selectively providing step comprises determining whether to perform the additional fabrication step. At least the following steps:
Subjecting the product IC wafer to an initial fabrication step;
Obtaining e-beam excitation measurements from a plurality of test structures provided on the wafer, the e-beam pads associated with each of the test structures using an e-beam spot having an elongated principal axis , Selectively targeting an e-beam pad that includes a logic device comprising a plurality of electrically connected elongated metal segments ; obtaining the measurement ; and at least partially in the measurement obtained from the test structure. An IC fabrication process comprising selectively subjecting the wafer to additional fabrication steps based on the above. 7. The IC fabrication process of claim 6, wherein each e-beam spot is shaped to match the size and shape of each targeted e-beam pad to maximize scanning efficiency. Each of the targeted e-beam pads has a first dimension in the scan direction of the e-beam that matches the elongated major axis of the e-beam spot,
7. The IC fabrication process of claim 6, wherein at least some of the targeted e-beam pads differ in a second dimension perpendicular to the first dimension. Each of the targeted e-beam pads is positioned along a linear scan line,
7. The IC fabrication process of claim 6, wherein the elongate major axis of the e-beam spot is oriented perpendicular to the scan line. 7. The IC fabrication process of claim 6, wherein obtaining the measurement involves obtaining less than 10 pixel measurements from each of the targeted e-beam pads. The IC fabrication process of claim 10, wherein obtaining the measurement involves obtaining only a single pixel measurement from each of the targeted e-beam pads. 7. The IC fabrication process of claim 6, wherein the selectively providing step comprises the step of determining whether to rerun one or more of the initial fabrication steps. 7. The IC fabrication process of claim 6, wherein the selectively providing step comprises the step of determining whether to perform the additional fabrication step. At least the following steps:
Subjecting the product IC wafer to an initial fabrication step;
Obtaining e-beam excitation measurements from a plurality of test structures on the wafer, the e-beam pads associated with each of the test structures along a linear scan direction having a plurality of electrical properties. Selectively targeting an e-beam pad that includes a logic device with an elongated metal segment connected to , said obtaining a measurement ; and, based at least in part on a measurement obtained from said test structure, An IC fabrication process comprising selectively subjecting a wafer to additional fabrication steps. Each e-beam pad was targeted, the size and shape have the same at least two of said have elongated metal segments, IC fabrication process of claim 14. 15. The IC fabrication process of claim 14, wherein obtaining the measurement involves obtaining less than 10 pixel measurements from each of the targeted e-beam pads. 17. The IC fabrication process of claim 16, wherein obtaining the measurement involves obtaining only a single pixel measurement from each of the targeted e-beam pads. 15. The IC fabrication process of claim 14, wherein obtaining the measurement involves selectively targeting with an e-beam spot having an elongated principal axis oriented perpendicular to the linear scan direction. .. The IC fabrication process of claim 14, wherein the selectively providing step comprises the step of determining whether to rerun one or more of the initial fabrication steps. 15. The IC fabrication process of claim 14, wherein the selectively providing step comprises the step of determining whether to perform the additional fabrication step.

Images