KR102474252B1 - Opportunistic placement of IC test structures and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product IC chips containing same - Google Patents

Abstract

Product ICs/wafers include additional diagnostic, test, or monitoring structures conveniently disposed at fill cell locations, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill areas. . Advanced manufacturing processes use data from such structure(s) in wafer placement decisions, reprocessing decisions, process control, yield learning, or failure diagnosis.

Description

Convenience of filling material cells, tap cells, decap cells, scribe lines, and/or dummy filling, and IC test structures and/or electron beam target pads to areas that are used differently from the use of product IC chips containing them Placement {Opportunistic placement of IC test structures and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product IC chips containing same}

Cross Reference of Related Applications

This application claims priority based on US Patent Application No. 14/303,578 filed on June 12, 2014, which is based on US Patent Application No. 14/303,578 filed on February 25, 2014. 190,040, which is a continuation-in-part of U.S. patent application Ser. No. 14/038,799 filed on September 27, 2013, which is also a U.S. patent application filed on June 12, 2014. Priority is claimed on the basis of Provisional Patent Application No. 62/011,161, all of which are incorporated herein by reference.

technology field

The present invention relates to the field of semiconductor integrated circuits and methods of manufacturing and testing such circuits.

“Test structures” on product wafers (any patterning not necessary for circuit function, but designed, intended, or used for monitoring or evaluation of partially or fully fabricated wafers/chips in accordance with the manufacturing process or its results) The deployment of "test structures" (as defined herein) has become quite common over the past decade. Traditionally, such test structures have been placed at scribe line sites between the active dies. For example, refer to "Scribe characterization vehicle test chip for ultra fast product wafer yield monitoring," IEEE International Conference on Microelectronic Test Structures, 2006 by Hess, Christopher and his colleagues.

U.S. Patent 7,223,616 B2 ("Test Structures in Unused Areas of Semiconductor Integrated Circuits and Methods for Designing the Same") to F. Duan and his colleagues describes interconnected active test cells under probe pads of test and product wafers. Placement is indicated.

US Patent 7,679,083 B2 ("Semiconductor integrated test structures for electron beam inspection of semiconductor wafers") to S. Jansen and his colleagues describes the placement of test structures within pre-specified large areas of product ICs.

Although these and other known techniques for placing test structures on product wafers produce useful results, they are still far from ideal. In particular, the available area on the scribe line of product wafers is severely limited and can accommodate only certain types of test structures. In addition, at the scribe line and below the probe pad methods face the fact that the test structures are located remotely from the most important active circuit areas and thus are not very likely to accurately represent the processing environment of the active circuit. Although the U.S. Patent 7,679,083 B2 potentially mitigates this problem, the U.S. Patent 7,679,083 B2 potentially mitigates the problem at the unacceptable cost of the large, dedicated test areas required (see U.S. Patent 7,679,083 B2). 5, paragraphs 44-45), valuable active die area can be consumed if one does not want to pay the unacceptable cost of large, dedicated test areas required for potential mitigation of the above problem.

The present invention discloses several techniques to improve test structure coverage on production ICs with little or no sacrifice of active die site.

According to one embodiment of the present invention, "filler cells" (defined as non-functional cells placed within an active circuit area for the purpose of avoiding/relieving routing congestion and/or equalizing cell density) Filler cells") are replaced with self-contained test structures that require no additional parts or interconnections. It is common in recent normal cell layouts to use such filler cells to relieve routing congestion. For example, “Optimizing routability in large-scale mixed-size placement,” ASP-DAC, 2013 by Cong, J. and colleagues and “Design of regular layouts to improve predictability by Menezes, C. and colleagues. ," Proceedings of the 6th IEEE International Caribbean Conference on Devices, Circuits and Systems, 2006". PCT Application Publication WO 2009/090516 A1 ("Monitor Cell and Monitor Cell Placement Method") in the name of C. Mayor and his co-workers includes a method of replacing a filler cell with a "monitor cell" (PCT Application Publication WO 2009/090516 5 of A1, step 540) is proposed, but the proposed monitor cell may be too large to fit in the filler cell space and, more importantly, require additional interconnections for integration into the scan chain. do it with Examples of test-accepting filler (fill) cells suitable for use in connection with the present invention are disclosed in the aforementioned US Provisional Patent Application No. 62/011,161 and in the drawings herein, Figures 11-32.

According to another embodiment of the present invention, decap (decoupling capacitance) cells are modified to incorporate one or more self-contained test structures. The use of such decap cells is known in the art. For example, "X. See "Novel Decoupling Capacitor Designs for sub-90nm CMOS Technology," Proceedings of the 7th IEEE International Symposium on Quality Electronic Design, 2006 by Meng and his colleagues.

According to another embodiment of the present invention, well tap (tap) cells are modified to incorporate one or more self-contained test structures. The use of such tap cells is known in the art. See, eg, U.S. Patent No. 6,388,315 ("Tap connections for circuits with leakage suppression capability"); "Jungeblut, T. and his colleagues, 2010, "A modular design flow for very large design space exploration," at FIG. 4 ("- add well tap cells")”. Examples of such test-accepting tap cells are disclosed in the aforementioned US provisional patent application Ser. No. 62/011,161.

According to still another embodiment of the present invention, "dummy fill" areas (see US Pat. No. 7,137,092 B2, incorporated herein by reference) are packed with test structure patterns.

U.S. Patent Nos. 7,217,579 ("Voltage contrast test structure") and 7,679,083 ("Semiconductor integrated test structures for electron beam inspection of semiconductor wafers"), both of which are supplemented by reference herein, refer to scribe line regions of semiconductor wafers. It discloses the use of voltage contrast test structures in fields. Another embodiment of the present invention includes the use of scribe line sites for insertion of additional test structures. Such scribe line regions may be discouraged or prohibited from use within actual die regions of product wafers due to practical performance issues or requirements for compatibility with existing design rule checking (DRC) flows. It can advantageously be used to implement test structures. Examples of such abandoned/prohibited test structures include structures that contain intentional interlayer misalignment(s), sub-design rules or canary structures, or structures that have density or patterning incompatible with the requirements of the active die area. are included See, for example, abandoned US Patent Application Publication No. 2009-0102501 A1 ("Test structures for e-beam testing of systematic and random defects in Integrated circuits"). In some embodiments of the present invention, the inter-die scribe line regions of product IC wafers of the present invention are all or mostly populated with voltage contrast test structures that are discouraged or prohibited from use within the active die regions.

Another embodiment of the present invention includes test pads (one type as defined above) into (and/or within) the above-mentioned dummy fill, filler cell, decap cell, and/or tap cell locations. An opportunistic insertion of "test structures") is included. Such test pads are charged particle (e.g., electron beam) targets, preferably sized to relatively small dimensions to achieve a range of 1x to 10x the minimum feature size resolvable at a given technology node (e.g., electron beam). ) targets, but may also include micro- or nano-probeable contact pads. Such test pads may be disposed on related test structures, disposed adjacent to related test structures, connected to non-adjacent test structures on the same layer, or related test structures on lower layer(s). may be connected to

Other embodiments of the present invention may use one, two, three, or four types of test structures under the pad and conveniently inserted test structures with or without the traditional scribe line mentioned above. It relates to ICs and IC layouts with dogs. Still additional embodiments of the present invention relate to CAD methods for forming such IC layouts, a manufacturing process that uses at least in part information obtained from the conveniently inserted test structures of the present invention, and ICs fabricated therefrom. do.

Thus, generally speaking, and without intending to be limiting, some embodiments of the present invention may include at least 10, 20, 30, or more of, for example, at least 50, 75, 100 or more contiguous cells. Product ICs comprising one or more rows, each of the rows including a plurality of logic cells, and at least half, three-quarters or more of the rows having filler, decap, or tap cell locations (and/or such cells) in) product ICs characterized by including a test structure. Such product ICs may further include a plurality of dummy fill test structures (including but not limited to test pads) implemented in dummy fill areas at least partially overlaying the rows. Such dummy fill test structures may appear on any patterned layer, in particular on one metal layer or more metal layers.

Each of the test structures is preferably self-contained, so that it does not require the use of routing areas for on-chip connections. In other words, with this self-contained embodiment of the present invention, replacing the filler/decap/tab cells with the test cells/structures of the present invention should not affect the available routing areas. In some embodiments, such self-contained test structures are formed in the footprints of multiple adjacent filler, decap, or tap cells, thereby allowing self-contained test structures that are relatively much larger and/or have irregular shapes. can be done Such product ICs are test structures configured for electron beam testing, test structures configured for SEM inspection, test structures configured for brightfield inspection, and probe contacts (by microprobe, nanoprobe or probe card). test structures configured for , or any combination of two, three, or four thereof.

Also, generally speaking, and without intending to be limiting, other embodiments of the present invention may include, for example, at least 20, 30, Product ICs that include a contiguous area comprising 40 or more contiguous rows, each of said rows containing a majority (or an overwhelming majority, such as 60%, 70%, or 80%) of logic cells; The regions also include at least 25 (or 50, 100, 150, or more) irregularly spaced cells each disposed in one of the rows, at locations otherwise suitable for logic cells, filler cells, or tab cells. It relates to product ICs characterized by including distributed self-contained test structures. In some embodiments, at least some of the test structures are included in decap cells. Such product ICs may also include a plurality of self-contained dummy fill test structures, each self-contained dummy fill test structure at least partially overlaying the contiguous area, but with a connection to common power supply networks. ) is not connected to any of the logic cells. In some embodiments, such dummy fill test structures may occupy one or more interconnect layers. In some embodiments, at least some of the test structures are canary (ie, lower design rule) test structures, and at least some of the dummy filling test structures are random defect test structures. In other embodiments, the test structures may include DR-compliant structures configured to test for or evaluate systematic failure modes. And embodiments including combinations thereof may also be considered.

Also, generally speaking, and without intending to be limiting, other embodiments of the invention include, for example, performing initial fabrication steps on at least an IC wafer; obtaining measurements from at least 5 (or 10, 20, 40 or more) self-contained test structures conveniently distributed within an adjacent logic portion of the wafer; and selectively causing additional and/or modified fabrication steps to be performed on the wafer based at least in part on measurements obtained from the test structures; It relates to IC manufacturing processes including. In some embodiments, obtaining measurements includes exciting the test structures with charged particles (e.g., an electron beam), inspecting the test structures with brightfield inspection, and inspecting the test structures with SEM inspection. It may include inspecting the test structures, or contacting the test structures with probing for electrical measurements. In some embodiments, selectively causing the wafer to undergo additional fabrication steps or physical failure analysis determines whether one or more of the initial fabrication steps should be reprocessed, or whether the additional fabrication steps should be performed. , or determining whether the wafer should be discarded.

Also, generally speaking, and without intending to be limiting, the process of fabricating a product IC wafer according to some embodiments of the present invention typically includes obtaining at least an initial product wafer layout; analyzing the initial product wafer layout using a computer and identifying convenient areas for insertion of a test structure (eg, dummy fill, fill cells, tap cells, decap cells); altering the initial product wafer layout by using the computer to insert a plurality of test structures that collectively constitute at least one distributed DOE across the identified convenient sites for insertion of the test structure; storing in a computer readable layout data record information necessary to fabricate the modified product wafer layout but not storing information necessary to utilize the distributed DOE(s); storing information necessary to utilize the distributed DOE(s) in a computer readable test data record; and providing information from the layout data record to a manufacturer to permit fabrication of wafers based on the altered product wafer layout. can include In accordance with this and other embodiments of the present invention, such layout changes may be made during design flow (ie, before design sign-off) or subsequent mask data processing (MDP). It may proceed during the step(s), or during both. In accordance with a related embodiment of the present invention, a method of manufacturing IC product chips typically includes receiving at least a first product IC wafer, wherein the first product IC wafer collectively constitutes at least one distributed DOE. comprising a plurality of product IC dies having embedded test structures; receiving data identifying at least one of the distributed DOE(s) and permitting use of at least one of the distributed DOE(s); obtaining information about fabrication of a first product IC wafer using the at least one distributed DOE(s); and processing the first product IC wafer to form a plurality of IC product chips. Such methods include at least the following additional steps: receiving a second product IC wafer identical to the first product IC wafer; obtaining information regarding fabrication of the second product IC wafer using at least one of the distributed DOE(s) on the second product IC wafer; and processing the second product IC wafer to form a plurality of IC product chips; may further include. According to these embodiments of the invention, data from such DOE(s) and/or test structure(s) can be used in wafer placement decisions, reprocessing decisions, process control, yield learning, or failure diagnosis. have.

Also, generally speaking, and without intending to be limiting, a product IC wafer according to another embodiment of the present invention has multiple electron beam operable test structures (or pads/targets) distributed within at least functional product circuitry areas. functional product circuit regions; and at least 10%, 15% of the total scan length of the electron beam scanner (measured in the scan direction) without lacking the convenience of operating any test structures (pads/targets). , or a plurality of electron beam skipping zones each allowing skipping of 20%. Such product IC wafers may further preferably include at least one or more blank electron beam scanning tracks, each of the one or more blank electron beam scanning tracks spanning the entire width of the functional product circuitry area.

Again, generally speaking and without intending to be limiting, another embodiment of the present invention is for example at least 3 x 3 (or 5 x 5, 10 x 10, 20 x 20, 20 x 20, or 50 x 50, etc.) product wafers, each of which includes a (many) plurality of operable (combination and/or sequential) logic cells supporting a product function; Each of the product dies includes a plurality of test-accepting tap cells interspersed with the logic cells, each of the test-accepting tap cells being self-contained (with or without electron beam test pads) product wafers comprising a voltage contrast test structure, wherein each of the scribe line portions comprises a plurality of voltage contrast test structures (with or without corresponding electron beam test pads) related to Such product dies are a plurality of test-accepting decap cells, each of which includes a self-contained voltage contrast test structure (with or without corresponding electron beam test pads). test allowed decap cells; a plurality of test acceptance filler cells, each of the test acceptance filler cells (with or without corresponding electron beam test pads) self-contained voltage contrast test structure; and/or a plurality of self-contained voltage contrast test structures implemented in dummy fill areas of the product dies (with or without corresponding electron beam test pads). In some embodiments, the scribe line regions are substantially completely populated with voltage contrast test structures (including electron beam target pads), and some or a plurality of the test structures included in the scribe line regions canary structures, may include intentional layer misalignments, and/or may include intentional process design rule violations.

Again, generally speaking, and without intending to be limiting, another embodiment of the present invention includes, for example, performing initial fabrication steps on at least a product IC wafer; At least 40 (preferably at least 100) self-contained test structures, at least 20 of the test structures randomly distributed within adjacent logic portions of the wafer (ie, portions of the wafer containing functional product logic) obtaining electron beam excitation measurements from a test structure and at least 20 of the test structures located within scribe line portions of the wafer; and selectively causing additional fabrication steps to be performed on the wafer based at least in part on measurements obtained from the test structures; It relates to IC manufacturing processes including. In some preferred embodiments, obtaining measurements is performed without continuously scanning any significant portion of the wafer (e.g., by sampling a single pixel value, or less than 10 pixel values), and and selectively targeting electron beam target pads located at scribe line portions. In some preferred embodiments, acquiring measurements includes selectively targeting electron beam target pads located within an adjacent logical portion of the wafer, without continuously scanning any significant portion of the wafer. In some embodiments, selectively causing may include determining whether one or more of the initial fabrication steps should be reprocessed. And in some embodiments, selectively performing may include determining whether to perform the additional fabrication steps.

Some embodiments of the present invention may include electrically probeable test structures, including but not limited to the type described in the above-mentioned US Provisional Patent Application No. 62/011,161, located in the scribe line regions of product wafers. . Such electrically probeable test structures may include their own probe pads and share one or more pads with adjacent voltage-contrast test structures, so that single pads function as probe pads and as electron beam target pads. can be allowed to

에 따라 해석됨을 의도한 것이다.In the discussion below, cells of the present invention (hereinafter in FIGS. 11-85) will be referred to both as “cells” and “means”. For the sake of clarity and clarity, Applicants shall interpret, for example, reference to a "FIG. 82 cell" to mean "a cell having the topological design shown in FIG. 82", whereas "FIG. 82 A similar reference to "means" refers to "a cell that implements the logic function of the Figure 82 cell, namely 'two-input, three-state multiplexer of driving force 1', and has the structure shown in Figure 82, or an equivalent structure" by covering

It is intended to be interpreted accordingly.

Generally speaking, and without intending to be limiting, additional embodiments of the present invention may include, within a contiguous logical region of at least 500 (or 1000, 1500, etc.) cells: (i) FIGS. 33A and 33B cells; 34a and 34b cell; 35A and 35B cells; 36A and 36B cells; 37A and 37B cells; 38A and 38B cells; 39A and 39B cells; 40A and 40B cells; 41A and 41B cells; 42A and 42B cells; 43A and 43B cells; 44A and 44B cells; Figure 45 cell; Figure 46 cell; Figure 47 cell; Figure 48 cell; Figure 49 cell; Figure 50 cells; Figure 51 cell; Figure 52 cell; Figure 53 cell; Figure 54 cells; Figure 55 cells; Figure 56 cell; Figure 57 cells; Figure 58 cell; Figure 59 cells; Figure 60 cells; Figure 61 cell; Figure 62 cell; Figure 63 cells; Figure 64 cells; Figure 65 cells; Figure 66 cell; Figure 67 cell; Figure 68 cell; Figure 69 cells; Figure 70 cells; Figure 71 cell; Figure 72 cell; Figure 73 cell; Figure 74 cell; Figure 75 cells; Figure 76 cells; Figure 77 cell; Figure 78 cells; Figure 79 cell; Figure 80 cell; Figure 81 cell; Figure 82 cell; 83A and 83B cells; Figure 84 cell; and FIG. 85 cells; at least a select number (eg, 3, 4, 5, 6, 7, etc.) of individual functional cells selected from the set consisting of, and (ii) at least one (or two, three, four, etc.) ), as at least 10 test-accepting cells comprising distinct types of FIG. 11 cell; Figure 12 cell; Figure 13 cell; Figure 14 cell; Figure 15 cell; Figure 16 cell; Figure 17 cell; Figure 18 cell; Figure 19 cell; Figure 20 cell; Figure 21 cell; Figure 22 cell; Figure 23 cell; Figure 24 cell; Figure 25 cell; Figure 26 cell; Figure 27 cell; Figure 28 cell; Figure 29 cell; Figure 30 cells; Figure 31 cell; and Figure 32 cell; It relates to product integrated circuits comprising at least 10 test-accepting cells selected from the set consisting of. Another embodiment of the present invention relates to methods of manufacturing such ICs, for example by instantiating and fabricating at least a select number of individual cells selected from the aforementioned sets.

에 따른 해당 수단 및 그의 등가물), 및 (ii) 적어도 1개(또는 2개, 3개, 4개 등등)의 개별 타입들을 포함하는 적어도 10개의 테스트-허용 수단으로서, 도 11 수단; 도 12 수단; 도 13 수단; 도 14 수단; 도 15 수단; 도 16 수단; 도 17 수단; 도 18 수단; 도 19 수단; 도 20 수단; 도 21 수단; 도 22 수단; 도 23 수단; 도 24 수단; 도 25 수단; 도 26 수단; 도 27 수단; 도 28 수단; 도 29 수단; 도 30 수단; 도 31 수단; 및 도 32 수단; 으로 이루어진 집합으로부터 선택되는 적어도 10개의 테스트-허용 셀을 포함하는 제품 집적 회로들에 관련된다. 본 발명의 다른 한 실시형태는 예를 들면 위에 언급한 집합들로부터 선택되는 적어도 선택 개수의 개별 수단들을 인스턴스(instance)화하여 제작함으로써 그러한 IC들을 제조하는 방법들에 관련된다. 본 발명의 부가적인 실시형태들은 위에서 정의된 타입의 적어도 선택된 개수(예컨대, 1개, 2개, 3개, 4개)의 상기 IC들과 아울러, 재충전 가능한 전원(들)과 같은 다른 옵션 구성요소들을 포함하는 전자 시스템들(고정식 또는 이동식)에 관련된다. 그리고 본 발명의 여전히 부가적인 실시형태들은 예를 들면 적어도 선택된 개수의 상기 위에서 언급한 "셀들" 및/또는 "수단들"을 인스턴스화함으로써 그러한 IC들을 제조하는 방법들에 관련된다.Again, generally speaking and without intending to be limiting, additional embodiments of the present invention may include, within a contiguous logical area of at least 200 (or 500, 1000, etc.) means: (i) means FIGS. 33A and 33B; Figures 34a and 34b means; Figures 35a and 35b means; Figures 36a and 36b means; Figures 37a and 37b means; Figures 38a and 38b means; Figures 39a and 39b means; Figures 40a and 40b means; Figures 41a and 41b means; Figures 42a and 42b means; Figures 43a and 43b means; Figures 44a and 44b means; Fig. 45 means; Fig. 46 means; Fig. 47 means; Fig. 48 means; Fig. 49 means; Fig. 50 means; Fig. 51 means; Fig. 52 means; Fig. 53 means; Fig. 54 means; Fig. 55 means; Fig. 56 means; Fig. 57 means; Fig. 58 means; Fig. 59 Means; Fig. 60 means; Fig. 61 means; Fig. 62 means; Fig. 63 means; Fig. 64 means; Fig. 65 means; 66 means; 67 means; Fig. 68 means; Fig. 69 Means; Fig. 70 means; Fig. 71 means; Fig. 72 means; Fig. 73 means; Fig. 74 means; Fig. 75 means; Fig. 76 means; Fig. 77 Means; Fig. 78 means; Fig. 79 Means; Fig. 80 means; 81 means; 82 means; 83a and 83b means; 84 means; and Figure 85 means; At least a select number (e.g., 2, 3, 4, 5, etc.) of individual "means" (in other words,

and (ii) at least 10 test-accepting means, including at least one (or two, three, four, etc.) distinct types, FIG. 11 means; Fig. 12 means; Fig. 13 means; Fig. 14 means; Fig. 15 means; Fig. 16 means; Fig. 17 means; Fig. 18 means; Fig. 19 means; Fig. 20 means; Fig. 21 means; Fig. 22 means; Fig. 23 means; Fig. 24 means; Fig. 25 means; Fig. 26 means; Fig. 27 means; Fig. 28 means; Fig. 29 means; Fig. 30 means; Fig. 31 means; and Figure 32 means; It relates to product integrated circuits comprising at least 10 test-accepting cells selected from the set consisting of. Another embodiment of the present invention relates to methods for manufacturing such ICs, for example by instantiating and fabricating at least a select number of individual means selected from the aforementioned sets. Additional embodiments of the present invention may include at least a selected number (e.g., 1, 2, 3, 4) of the ICs of the type defined above, as well as other optional components such as rechargeable power source(s). It relates to electronic systems (stationary or mobile) comprising And still further embodiments of the present invention relate to methods of manufacturing such ICs, for example by instantiating at least a selected number of the above mentioned “cells” and/or “means”.

Although typical logic and test-accepting cells (FIGS. 11-85) avoid the use of tapered devices to avoid the parameter variation problems and functional yield loss problems associated with tapered devices, those skilled in the art can immediately As will be appreciated, equivalent, variants of these cells may use tapered devices and examples of tapered devices with such variations are within the scope of the present invention.

Another embodiment of the present invention relates to the use of a tool that uses a column of charged particles (electrons or ions) whose main function is to find defects on the surface of semiconductor wafers (that is, to function as an inspector). do. (While the term "electron beam" is used in the description of the present invention, it is to be understood herein that the term "electron beam" applies to all charged beams.)

In accordance with one embodiment of the present invention, a VC inspector for sampling pixels on a wafer surface is described. This scanning method is fundamentally different from all previously designed inspection systems. In one embodiment, pixels have some designated X-Y coordinates at which the pixel value (ie, the electron beam signal) is used to determine if a defect exists. This can be considered a 0-D inspection instead of the typical 2-D inspection of the prior art.

In one embodiment, the pixels correspond to "pads" of an electrical test structure specially designed for the purpose of finding voltage contrast defects. The beam is projected onto the pad for a specified period of time. Each test structure can have one or more pads (the tester reads one pixel per pad). Such test pads may exist on semiconductor wafers whose patterns are primarily designed as "test chips" or may be embedded in "product wafers".

In one embodiment, each pixel corresponds to a specific location in the semiconductor product layout. These pixels are selected because the signal abnormality at these locations on the product indicates a certain type of defect or certain types of defects.

In one embodiment, the stage remains stationary, similar to a “step and scan” inspection. Once pixel values corresponding to a given field of view are detected, the stage moves to another position from which the next set of pixels can be read out.

In one embodiment, the stage is moved as the pixels are being scanned and inspection is made by deflecting the electron beam accordingly to account for the stage movement.

In one embodiment, the duration of pixel reading at each location is dynamic for each pixel, i.e. depending on the test structure or product circuit being tested at each point in time, the beam held at that location is continuous. The period of time will change accordingly.

In one embodiment, the size of the beam on the wafer is not fixed, but changes dynamically for each position being read. This type of beam shaping is similar to that used in electronic beam recorders. The sizing of the spot on a structural unit basis allows the beam to be optimized for each structure. The optimization typically maximizes the signal-to-noise ratio (SNR) of the test. Another embodiment of the present invention relates to the design of a "voltage-contrast device-under-test (VC DUT)" with test pads, in which case the complete structure is very small (<10). It is tested with pixels. Such a VC DUT may have a test pad whose size and shape accommodates a non-circular incident electron beam while maximizing SNR. Such beams may also be rectangular in shape to match pads which are also rectangular in shape. Such pads can be configured to obtain beams with an asymmetric aspect ratio (X/Y length ratio) greater than 3 (a DUT with an X-dimension of 100 nm and a Y-dimension of 300-600 nm is 3:1, 4:1 , which has an aspect ratio of 5:1).

These and other embodiments, features and advantages of the present invention are exemplified in the accompanying drawings below.

1 includes logic cells (L), filler cells (F), and tap cells (T) arranged in rows, with routing parts between the rows and decap cells (dC) adjacent to the rows. A diagram showing a representative cross-section of a typical cell layout in a conceptual manner.
FIG. 2 is a view showing the same layout as FIG. 1 but in which dummy filling areas are shown in the first layer.
FIG. 3 is a view showing the same layout as FIGS. 1 and 2 but with dummy filling area(s) shown in the second layer.
FIG. 4 is a diagram showing a typical layout according to the invention in which the filler cells, tap cells, decap cells, and dummy filling areas of the layout of FIG. 3 are replaced with self-contained test structures.
Figure 5 is a diagram showing in a conceptual manner a preferred form of a generic cell layout (for use in accordance with the present invention).
FIG. 6 is a diagram showing a typical layout according to the present invention in which the filler cells, decap cells, tap cells, and dummy filling areas of the layout of FIG. 5 are replaced with self-contained test structures.
7 is a diagram showing an exemplary process flow for opportunistic test structure insertion in accordance with some embodiments of the present invention.
Figure 8 is a diagram showing an exemplary process flow for obtaining useful results using expediently inserted test structures (according to Figure 7 or Figure 10).
9 is a concept of a portion of a typical wafer or die showing conveniently inserted test pads and/or structures arranged to create blank track(s) and/or skip zone(s) allowing rapid electron beam scanning. It is a drawing that shows in an intuitive way.
10 is a diagram showing a modification of a typical process flow for opportunistic test structure insertion in accordance with some embodiments of the present invention.
11 is a diagram showing a first exemplary test-accepting tap cell.
12 is a diagram showing a first exemplary test-accepting filler cell.
13 is a diagram showing another typical test-accepting filler cell.
14 is a diagram showing another typical test-accepting tap cell.
15 is a diagram showing another typical test-accepting filler cell.
16 is a diagram showing another typical test-accepting tap cell.
17 is a diagram showing another typical test-accepting filler cell.
18 is a diagram showing another typical test-accepting filler cell.
19 is a diagram showing another typical test-accepting tap cell.
20 is a diagram showing another typical test-accepting filler cell.
21 is a diagram showing another typical test-accepting filler cell.
22 is a diagram showing another typical test-accepting filler cell.
23 is a diagram showing another typical test-accepting tap cell.
24 is a diagram showing another typical test-accepting filler cell.
25 is a diagram showing another typical test-accepting tap cell.
26 is a diagram showing another typical test-accepting filler cell.
27 is a diagram showing another typical test-accepting tap cell.
28 is a diagram showing another typical test-accepting filler cell.
29 is a diagram showing another typical test-accepting tap cell.
30 is a diagram showing another typical test-accepting tap cell.
31 is a diagram showing another typical test-accepting filler cell.
32 is a diagram showing another typical test-accepting filler cell.
33A to 85 are diagrams showing typical cells of a typical normal cell library, in particular
33A and 33B are views respectively showing adjacent left and right portions of a first exemplary normal cell;
34a and 34b are views respectively showing adjacent left and right parts of another typical normal cell;
35A and 35B are views respectively showing adjacent left and right parts of another typical normal cell;
36A and 36B are views respectively showing adjacent left and right portions of another typical normal cell;
37A and 37B are views respectively showing adjacent left and right parts of another typical normal cell;
38A and 38B are views respectively showing adjacent left and right portions of another typical normal cell;
39A and 39B are views respectively showing adjacent left and right parts of another typical normal cell;
40A and 40B are views respectively showing adjacent left and right portions of another typical normal cell;
41A and 41B are views respectively showing adjacent left and right portions of another typical normal cell;
42A and 42B are views respectively showing adjacent left and right portions of another typical normal cell;
43A and 43B are diagrams respectively showing adjacent left and right portions of another typical normal cell;
44A and 44B are views respectively showing adjacent left and right portions of another typical normal cell;
45 is a diagram showing another typical normal cell;
46 is a diagram showing another typical normal cell;
47 is a diagram showing another typical normal cell;
48 is a diagram showing another typical normal cell;
49 is a diagram showing another typical normal cell;
50 is a diagram showing another typical normal cell;
51 is a diagram showing another typical normal cell;
52 is a diagram showing another typical normal cell;
53 is a diagram showing another typical normal cell;
54 is a diagram showing another typical normal cell;
55 is a diagram showing another typical normal cell;
56 is a diagram showing another typical normal cell;
57 is a diagram showing another typical normal cell;
58 is a diagram showing another typical normal cell;
59 is a diagram showing another typical normal cell;
60 is a diagram showing another typical normal cell;
61 is a diagram showing another typical normal cell;
62 is a diagram showing another typical normal cell;
63 is a diagram showing another typical normal cell;
64 is a diagram showing another typical normal cell;
65 is a diagram showing another typical normal cell;
66 is a diagram showing another typical normal cell;
67 is a diagram showing another typical normal cell;
68 is a diagram showing another typical normal cell;
69 is a diagram showing another typical normal cell;
70 is a diagram showing another typical normal cell;
71 is a diagram showing another typical normal cell;
72 is a diagram showing another typical normal cell;
73 is a diagram showing another typical normal cell;
74 is a diagram showing another typical normal cell;
75 is a diagram showing another typical normal cell;
76 is a diagram showing another typical normal cell;
77 is a diagram showing another typical normal cell.
78 is a diagram showing another typical normal cell;
79 is a diagram showing another typical normal cell.
80 is a diagram showing another typical normal cell;
81 is a diagram showing another typical normal cell;
82 is a diagram showing another typical normal cell;
83A and 83B are views respectively illustrating adjacent left and right portions of another typical normal cell;
84 is a diagram showing another typical normal cell;
85 is a diagram showing another typical normal cell.
86 is a diagram showing prior art “step and scan” and “swathing” techniques.
87 is a diagram showing a prior art beam scanning/shaping (shaping) device.
FIG. 88 is a diagram showing examples of beam shapes that can be implemented using the columns of FIG. 87 .
FIG. 89 is a diagram showing a typical semiconductor wafer that is typically circular and divided into identical dies, and additionally shows a typical case in which test structures are all located at scribe regions of the die.
90 illustrates a series of test structures in which the pads of a series of test structures are laid out when relative movement of the wafer to the spot of the electron beam causes the spot of the electron beam to scan over the pads of the series of test structures. it is a drawing
91 is a diagram showing an example of an electron spot shaped in a non-circular manner to match the size and shape of the pad to maximize the electron current supplied to the pad.
92 shows a pad sized according to the amount of charge that needs to be supplied to the test structures when high charge test structures will have long pads along the scanning direction of the electron beam to increase the electron beam dwell time on the pad. It is a drawing showing examples of shapes.
93 shows that the electron beam moves quickly when there is a long stretch where none of the pads are charging, but at less than a constant speed in dense areas to allow for more charging of the pads of the test structures. This is a diagram showing the scenario.
94 is a diagram showing test structures laid out on either side of the pads, allowing a relatively large number of test structures to be scanned in a single pass of the electron beam over the wafer.
95 is a diagram showing how the solid pads can be divided into fine lines or alternate shapes so that the layout of the solid pads is compatible with the design rules of the semiconductor process.
96 is a diagram showing “net gray” pads for use with some embodiments of the present invention.
97 is a diagram illustrating in a conceptual manner one embodiment of a VC DUT according to some embodiments/examples of the present invention.
98 is a diagram illustrating in a conceptual manner another embodiment of a VC DUT according to some embodiments/examples of the present invention.
99 is a diagram illustrating in a conceptual manner another embodiment of a VC DUT according to some embodiments/examples of the present invention.

1 includes logic cells (L), tap cells (T) and filler cells (F) arranged in rows, with routing channels between the rows and decap cells (dC) adjacent to the rows. A diagram showing a representative cross-section of the general cell layout of the technology in a conceptual manner. As shown, the overall distribution of decaps, tabs and filler cells within this representative cross-section is irregular and does not follow any apparent pattern or symmetry. (As a person skilled in the art will know immediately, the descriptions described in this specification are conceptual and are only intended to illustrate the principles of the present invention rather than to represent actual layout objects. In fact, such a person skilled in the art will understand However, it is typical that tap cells concern only one size and appear at regular or near regular intervals Similarly, decap cells will fit within the normal cell rows and be placed within the normal cell rows, as will also be appreciated by those skilled in the art. and is often sized to fit within and be placed within the normal cell rows.)

FIG. 2 shows in a conceptual manner a prior art layout identical to FIG. 1 but showing dummy filling areas in the first layer; These dummy filling parts are shown as diagonally hashed parts, and may have a regular shape (eg, a rectangle) or an irregular shape as shown. The most useful dummy filling sites according to the present invention typically appear on third metal layers (e.g., M3, M4, M5, M6), but active poly layer(s), or underlying metal and/or Or it may appear on previous layers. (As the skilled person will understand, the dummy fill illustration shown in FIG. 2 is conceptual, since the dummy fill areas are much larger in area than one or several normal cells. Because it is typical.)

FIG. 3 is a diagram illustrating in a conceptual manner the same layout as FIGS. 1 and 2 but with dummy filling area(s) shown in the second layer. This second layer dummy filling area is represented by scale pattern hashing.

Figure 4 is a diagram showing in a conceptual manner an exemplary layout based on the layout of Figure 3, illustrating some embodiments of the present invention. As typified in FIG. 4, the filler cells F and the tap cells T are replaced with the test structures TS4, TS5, TS6, TS7, TS8, TS9, and TS10, and the decap cells dC are the test- It has been replaced with acceptable decap cells (dC-T), and dummy filling regions have been replaced with test structures (TS1, TS2, TS3).

Figure 5 is a diagram showing in a conceptual manner a preferred form of a generic cell layout suitable for use in accordance with the present invention. A more recent style is shown in this figure in which cell rows are contiguous and routing areas form over-the-cell wires. Although not shown, it should be understood here that the routing areas do not have to be regular in shape and do not have to be oriented parallel to the rows.

6 shows the self-contained test structures TS, dC-T, and dummy filling (diagonally hashed) regions of the layout of FIG. It is a diagram showing a typical layout according to the present invention in which each of the dotted line areas) is replaced.

As will be appreciated by those skilled in the art, there are a number of options for the selection of specific test structures which will be exemplified for convenience in accordance with the present invention.

Product ICs according to the present invention are product layouts that are most susceptible to systemic defects caused by bright field and/or electron beams (or other charging), including multi-patterned structures. It may include a test structure suitable for in-line system defect inspection of the patterns. These test structures preferably include canary structures (ie, sub-design structures used to explore process-layout marginalities).

Product ICs according to the present invention are also resistant to the most probable defects, such as single line opens, and the most probable defects appearing through open locations, by lightfield (including canary structures) and electron beam tools. It may include test structures suitable for inline random defect inspection of product-like patterns for the product.

Product ICs according to the present invention also have product specific patterns of overlay/misalignment for poly CD, MOL CD, via bottom CD, metal CD and height, dielectric heights, etc. It may include test structures suitable for in-line metrology, such as structures to extract, and may be capable of testing electrically and/or scanning electron microscopy (eg, for overlays, line CDs and profiles).

Product ICs according to the present invention may also include Physical Failure Analysis (PFA) structures for probable systemic failures, in which case such PFAs may include pads for probing and Can include product specific layout patterns (including canary structures).

And product ICs according to the present invention may also include the available test structures noted above, or any combination of other available test structures.

For test-tolerant decap cells, preferred test structures are M1 structures for single line open check.

Important objectives for the design of test structures according to some embodiments of the present invention are (1) that the test structures conform to the printability of the active geometry (ie, normal cells or interconnects); and/or (2) the test structures must exhibit active cell properties (printability and electrical properties).

11-32 are diagrams showing a set of representative VC DUTs suitable for use in some embodiments of the present invention, as described in detail below.

Referring now to FIG. 11, FIG. 11 is a diagram showing a first exemplary test-accepting tap cell. These cells contain E-shaped voltage contrast targets/pads for electron beam (or other charged particle) inline testing to detect the following failure modes: merged via component shorts to adjacent metal/local interconnects. It consists of In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom metal -> short to grounded pad = bright pad. (As will be appreciated by those of ordinary skill in the art, electron beam inspection can be configured to produce dark or light conditions for floating polygons. The latter configuration is typically more stable, and as a result examples in the present disclosure It is assumed for , but as will be appreciated by those skilled in the art, the present invention is useful in any configuration.)

Referring now to FIG. 12, FIG. 12 is a diagram showing a first exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure modes: merged via configuration short to underlying metal. . In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom metal -> short to grounded pad = bright pad.

Referring now to FIG. 13, FIG. 13 is a diagram showing another exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure modes: merged via configuration short to underlying metal. . In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom metal -> short to grounded pad = bright pad.

Referring now to FIG. 14, FIG. 14 is a diagram showing another exemplary test-accepting tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: merged via configuration open. In the configuration shown, pass response = grounded metal = light pad, but fault response = grounded bottom metal -> fault connection to floating pad = dark pad.

Referring now to FIG. 15, FIG. 15 is a diagram showing another exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: merged via configuration open. In the configuration shown, pass response = grounded metal = light pad, but fault response = grounded bottom metal -> fault connection to floating pad = dark pad.

Referring now to FIG. 16, FIG. 16 is a diagram showing another exemplary test-accepting tap cell. These cells include E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: via shorts to adjacent metal/local interconnects. have. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom metal -> short to grounded pad = bright pad.

Referring now to FIG. 17, FIG. 17 is a diagram showing another exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: via short to underlying metal. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom metal -> short to grounded pad = bright pad.

Referring now to FIG. 18, FIG. 18 is a diagram showing another exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: via short to underlying metal. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom metal -> short to grounded pad = bright pad.

Referring now to FIG. 19, FIG. 19 is a diagram showing another exemplary test-accepting tap cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: contact shorts to the underlying layer. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom layer -> short to grounded pad = bright pad.

Referring now to FIG. 20, FIG. 20 is a diagram showing another exemplary test-accepting filler cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: contact shorts to the underlying layer. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom layer -> short to grounded pad = bright pad.

Referring now to FIG. 21, FIG. 21 is a diagram showing another exemplary test-accepting filler cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: contact shorts to the underlying layer. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom layer -> short to grounded pad = bright pad.

Referring now to FIG. 22, FIG. 22 is a diagram showing another exemplary test-accepting filler cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: contact shorts to the underlying layer. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded bottom layer -> short to grounded pad = bright pad.

Referring now to FIG. 23, FIG. 23 is a diagram showing another exemplary test-accepting tap cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: same color metal end to metal side shorts. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded metal layer -> short to grounded pad = bright pad.

Referring now to FIG. 24, FIG. 24 is a diagram showing another exemplary test-accepting filler cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: same color metal end to metal side shorts. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded metal layer -> short to grounded pad = bright pad.

Referring now to FIG. 25, FIG. 25 is a diagram showing another exemplary test-accepting tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: metal open. In the configuration shown, pass response = grounded metal = light pad, but fault response = grounded metal -> connection to floating pad fault = dark pad.

Referring now to FIG. 26, FIG. 26 is a diagram showing another exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: metal open. In the configuration shown, pass response = grounded metal = light pad, but fault response = grounded metal -> connection to floating pad fault = dark pad.

Referring now to FIG. 27, FIG. 27 is a diagram showing another exemplary test-accepting tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: metal short to metal edge. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded metal layer -> short to grounded pad = bright pad.

Referring now to FIG. 28, FIG. 28 is a diagram showing another exemplary test-accepting filler cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: metal short to metal edge. In the configuration shown, pass response = floating metal = dark pad, but fault response = grounded metal layer -> short to grounded pad = bright pad.

Referring now to FIG. 29, FIG. 29 is a diagram showing another exemplary test-accepting tap cell. This cell contains an E-shaped voltage contrast target/pad and is configured for electron beam (or other charged particle) inline testing to detect the following failure mode: same color contact end to contact short. In the configuration shown, pass response = floating contacts = dark pad, but fault response = grounded contact layer → short to grounded pad = bright pad.

Referring now to FIG. 30, FIG. 30 is a diagram showing another exemplary test-accepting tap cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: different color contact to contact end shorts. In the configuration shown, pass response = floating contacts = dark pad, but fault response = grounded contact layer → short to grounded pad = bright pad.

Referring now to FIG. 31, FIG. 31 is a diagram showing another exemplary test-accepting filler cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: contact-to-contact shorts. In the configuration shown, pass response = floating contacts = dark pad, but fault response = grounded contact layer → short to grounded pad = bright pad.

Referring now to FIG. 32, FIG. 32 is a diagram showing another exemplary test-accepting filler cell. These cells contain E-shaped voltage contrast targets/pads and are configured for electron beam (or other charged particle) inline testing to detect the following failure modes: contact-to-contact shorts. In the configuration shown, pass response = floating contacts = dark pad, but fault response = grounded contact layer → short to grounded pad = bright pad.

33A-85 are diagrams showing typical cells from a generic cell library. These cells are compatible with the test-accepting fill cells of FIGS. 11-32 above. These typical normal cells are specifically shown in FIGS. 33A-85 of the accompanying drawings. The function of each illustrated cell will be explained below. 33A shows a metal-1/first mask 11; a metal-1/second mask 12; Via-0 (13); Via-1 (14); metal-2 (15); poly-contact 16; active (17); active-contact 18; poly(19); poly-cut (20); and active-cut (21); It is a diagram providing a layer legend for the accompanying drawings having the layers indicated by . As will be appreciated by those skilled in the art, such cells are known in the art (e.g., U.S. Patent No. 8302057 B2 to S. Saika, entitled "Standard cell library and semiconductor integrated circuit"; incorporated herein by reference); US Patent Application Publication No. 20130036397 A1 "Standard Cell Placement Technique For Double Patterning Technology" in the name of J. J. Lee and colleagues (also incorporated herein by reference); D. D. US Patent Application Publication No. 20120249182 A1 "Power Routing in Standard Cell Designs" in the name of Sherlekar; US Patent No. 6938226 "7-tracks standard cell" in the name of H. H. Nguyen et al. U.S. Patent No. 8079008 "High-speed low-leakage-power standard cell library" to P. Penzes et al. (also incorporated herein by reference); (also incorporated herein by reference) U.S. Patent No. 8174052 "Standard cell libraries and integrated circuit including standard cells" to H.-Y. Kim et al. and O. M. K. Law et al. It is intended to be instantiated and used with methods and configurations described in Patent No. 8173491 "Standard cell architecture and methods with variable design rules". Moreover, as will be appreciated by those skilled in the art, the dummy poly stripes shown over the right and left edges of each cell boundary are used for DRC checking and should therefore be considered part of the cells themselves. Product ICs constructed using the library of the present invention are preferably manufactured using commercially available 14nm manufacturing processes.

Referring to FIGS. 33A and 33B , FIGS. 33A and 33B are views respectively showing adjacent left and right portions of a first typical normal cell. This cell implements the logic function of a scan-tolerant d-flip-flop with a set of driving forces of 3 and an inverting output.

Referring to FIGS. 34A and 34B , FIGS. 34A and 34B are views respectively showing adjacent left and right portions of another normal cell. This cell implements the logic function of a scan-tolerant d-flip-flop with a set of driving force of 2 and an inverting output.

Referring to FIGS. 35A and 35B , FIGS. 35A and 35B are views respectively showing adjacent left and right portions of another normal cell. This cell implements the logic function of a scan-tolerant d-flip-flop with set driving force 1 and an inverting output.

Referring to FIGS. 36A and 36B , FIGS. 36A and 36B are views respectively showing adjacent left and right portions of another normal cell. This cell implements a scan-tolerant d-flip-flop with a set of driving forces of 3.

Referring to FIGS. 37A and 37B , FIGS. 37A and 37B are views respectively showing adjacent left and right portions of another normal cell. This cell implements the logic function of a scan-tolerant d-flip-flop with a set of driving forces of 2.

Referring to FIGS. 38A and 38B , FIGS. 38A and 38B are views respectively showing adjacent left and right portions of another normal cell. This cell implements a scan-tolerant d-flip-flop with a set of driving forces of 1.

Referring to FIGS. 39A and 39B , FIGS. 39A and 39B are views respectively showing adjacent left and right portions of another normal cell. It implements the logic function of a scan-tolerant d-flip-flop with reset and invert outputs of driving force 3.

Referring to FIGS. 40A and 40B , FIGS. 40A and 40B are views respectively showing adjacent left and right portions of another normal cell. This cell implements a scan-tolerant d-flip-flop with reset and invert outputs of driving force 2.

Referring to FIGS. 41A and 41B , FIGS. 41A and 41B are views respectively showing adjacent left and right portions of another normal cell. This cell implements a scan-tolerant d-flip-flop with reset and invert outputs of driving force 1.

Referring to FIGS. 42A and 42B , FIGS. 42A and 42B are views respectively showing adjacent left and right portions of another normal cell. This cell implements the logic function of a scan-tolerant d-flip-flop with a reset of driving force 3.

Referring to FIGS. 43A and 43B , FIGS. 43A and 43B are views respectively showing adjacent left and right portions of another normal cell. This cell implements a scan-tolerant d-flip-flop with reset of driving force 2.

Referring to FIGS. 44A and 44B , FIGS. 44A and 44B are views respectively showing adjacent left and right portions of another normal cell. This cell implements the logic function of a scan-tolerant d-flip-flop with reset of driving force 1.

Referring to FIG. 45, FIG. 45 is a diagram showing another normal cell. This cell implements the logic function of a latch with set and reset of driving force 3.

Referring to FIG. 46, FIG. 46 is a diagram showing another normal cell. This cell implements the logic function of a latch with set and reset of driving force 2.

Referring to FIG. 47, FIG. 47 is a diagram showing another normal cell. This cell implements the logic function of a latch with set and reset of driving force 1.

Referring to FIG. 48, FIG. 48 is a diagram showing another normal cell. This cell implements the logic function of a latch with a set of driving forces of 3.

Referring to FIG. 49, FIG. 49 is a diagram showing another normal cell. This cell implements the logic function of a latch with a set of driving forces of 2.

Referring to FIG. 50, FIG. 50 is a diagram showing another normal cell. This cell implements the logic function of a latch with a set of driving forces of 1.

Referring to FIG. 51, FIG. 51 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset of driving force 3.

Referring to FIG. 52, FIG. 52 is a diagram showing another normal cell. This cell implements the logic function of a latch with reset of driving force 2.

Referring to FIG. 53, FIG. 53 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset of driving force 1.

Referring to FIG. 54, FIG. 54 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 4.

Referring to FIG. 55, FIG. 55 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 3.

Referring to FIG. 56, FIG. 56 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 2.

Referring to FIG. 57, FIG. 57 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 1.

Referring to FIG. 58, FIG. 58 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 3.

Referring to FIG. 59, FIG. 59 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 2.

Referring to FIG. 60, FIG. 60 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverted output of driving force 1.

Referring to FIG. 61, FIG. 61 is a diagram showing another normal cell. This cell implements the logic function of a latch with set, reset and invert clocks of drive force 3.

Referring to FIG. 62, FIG. 62 is a diagram showing another normal cell. This cell implements the logic function of a latch with set, reset and invert clocks of drive force 2.

Referring to FIG. 63, FIG. 63 is a diagram showing another normal cell. This cell implements the logic function of a latch with set, reset and invert clocks of drive force 1.

Referring to FIG. 64, FIG. 64 is a diagram showing another normal cell. This cell implements the logic function of a latch with a set of driving force 3 and an inverting clock.

Referring to FIG. 65, FIG. 65 is a diagram showing another normal cell. This cell implements the logic function of a latch with a set of driving force 2 and an inverting clock.

Referring to FIG. 66, FIG. 66 is a diagram showing another normal cell. This cell implements the logic function of a latch with a set of driving force 1 and an inverting clock.

Referring to FIG. 67, FIG. 67 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset and invert clock of drive force 3.

Referring to FIG. 68, FIG. 68 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset and invert clock of drive force 2.

Referring to FIG. 69, FIG. 69 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset of driving force 1 and an inverting clock.

Referring to FIG. 70 , FIG. 70 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset of driving force 3, an inverting clock and an inverting output.

Referring to FIG. 71 , FIG. 71 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset of driving force 2, an inverting clock and an inverting output.

Referring to FIG. 72 , FIG. 72 is a diagram showing another normal cell. This cell implements the logic function of a latch with a reset of driving force 1, an inverting clock and an inverting output.

Referring to FIG. 73, FIG. 73 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock and an inverting output of driving force 4.

Referring to FIG. 74 , FIG. 74 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock and an inverting output of drive force 3.

Referring to FIG. 75, FIG. 75 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock and an inverting output of driving force 2.

Referring to FIG. 76, FIG. 76 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock and an inverting output of driving force 1.

Referring to FIG. 77, FIG. 77 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock of driving force 3.

Referring to FIG. 78 , FIG. 78 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock of driving force 2.

Referring to FIG. 79, FIG. 79 is a diagram showing another normal cell. This cell implements the logic function of a latch with an inverting clock of driving force 1.

Referring to FIG. 80, FIG. 80 is a diagram showing another normal cell. This cell implements the logic function of a 2-input, 3-state multiplexer of driving force 4.

Referring to FIG. 81, FIG. 81 is a diagram showing another normal cell. This cell implements the logic function of a 2-input, 3-state multiplexer of driving force 2.

Referring to FIG. 82, FIG. 82 is a diagram showing another normal cell. This cell implements the logic function of a 2-input, 3-state multiplexer of driving force 1.

Referring to FIGS. 83A and 83B , FIGS. 83A and 83B are views respectively showing adjacent left and right portions of another normal cell. This cell implements the logic function of a two-input, three-state multiplexer with an inverting output of driving force 4.

Referring to FIG. 84, FIG. 84 is a diagram showing another normal cell. This cell implements the logic function of a two-input, three-state multiplexer with an inverting output of driving force 2.

Referring to FIG. 85, FIG. 85 is a diagram showing another normal cell. This cell implements the logic function of a two-input, three-state multiplexer with an inverting output of driving force 1.

As will be appreciated by those of ordinary skill in the art, the typical flip-flop, latch, and multiplexer designs shown in FIGS. 33A-85 are significant improvements over competing designs (e.g., reduction of at least one poly stripe). to achieve

86 is a diagram showing prior art “step and scan” and “swathing” techniques.

87 is a diagram showing a prior art beam scanning/shaping (shaping) device.

FIG. 88 is a diagram showing examples of beam shapes that can be implemented using the columns of FIG. 87 .

FIG. 89 shows a typical semiconductor wafer that is typically circular and divided into identical dies, and additionally shows a typical case in which test structures are all located at the scribe regions of the die.

90 shows the layout of the pads of a series of test structures constituting a row when the spot of an electron beam is scanned on the pads of a series of test structures constituting a row by the relative movement of the wafer with respect to the spot of the electron beam. A diagram illustrating a series of test structures in

91 is a diagram showing an example of an electron spot shaped in a non-circular manner to match the size and shape of the pad to maximize the electron current supplied to the pad.

92 shows a pad sized according to the amount of charge that needs to be supplied to the test structures when high charge test structures will have long pads along the scanning direction of the electron beam to increase the electron beam dwell time on the pad. It is a drawing showing another example of shapes.

93 shows that the electron beam moves quickly when there is a long stretch where none of the pads are charging, but at less than a constant speed in dense areas to allow for more charging of the pads of the test structures. This is a diagram showing the scenario.

94 is a diagram showing test structures laid out on either side of the pads, allowing a relatively large number of test structures to be scanned in a single pass of the electron beam over the wafer.

95 is a diagram showing how the solid pads can be divided into fine lines or alternate shapes so that the layout of the solid pads is compatible with the design rules of the semiconductor process. Referring now to FIG. 96, FIG. 96 shows a VC DUT sized and shaped to accommodate non-circular incident electron beams for readout in a single spot measurement, with a pad designed with only alternate lines connecting the DUT. As a diagram showing a group, the remaining pad lines are connected to floating or ground so that their polarity is opposite to that of the functional DUT.

For functional DUTs, the pad lines alternate bright/dark, whereas for non-functional DUTs (ie, faulty DUTs) the pads are either all light pads or dark pads. . The advantage here is that the "net" gray level for all DUTs that are not defective is virtually always the same, and the image computer can use the same thresholds for detection of all DUTs that are defective. This simplifies the software algorithms and hardware of the image computer.

Referring now to FIG. 97 , FIG. 97 is a diagram illustrating in a conceptual manner one embodiment of a VC DUT in accordance with some embodiments of the present invention. The pads are either a single pixel measurement (i.e. a single analog readout) or N analog values (i.e. an N-sample digital average) at the same location using a large spot size electron beam tool can be used to improve SNR. present) is read.

The beam and pad are designed to have a more or less identical footprint. In this case, the X/Y aspect ratio is -1. The beam is square shaped to match the pad, but could be circular with similar dimensions. Although the pictograph shows four pads, the invention equally applies to one or multiple pads.

Referring now to FIG. 98 , FIG. 98 is a diagram illustrating in a conceptual manner another embodiment of a VC DUT in accordance with some embodiments of the present invention. The pads are either a single pixel measurement (i.e. a single analog readout) or N analog values (i.e. an N-sample digital average) at the same location using a large spot size electron beam tool can be used to improve SNR. present) is read. In general, pads and beams have similar footprints on a wafer. However, to accommodate non-symmetric beams (X/Y aspect ratio > 3) while meeting semiconductor layout design rules, the pad is divided into an array of narrow horizontal lines. Although the pictograph shows one pad, the invention applies equally to one or multiple pads.

Referring now to FIG. 99, FIG. 99 is a diagram illustrating in a conceptual manner another embodiment of a VC DUT in accordance with some embodiments of the present invention. The pads are optimized for line-shaped beams. The X/Y aspect ratio of the pads and beams is greater than 3. The pads are read like a bar-code scanner, and the polarity of each pad is read with fewer than 10 pixels. Although the pictograph shows four pads, the invention equally applies to one or multiple pads.

Claims (20)

As an IC manufacturing method,
The IC manufacturing method is at least
subjecting a product IC wafer to initial fabrication steps;
obtaining electron beam excitation measurements without continuously scanning from a plurality of test structures installed on the product IC wafer - selectively selecting less than 10 pixels from an electron beam pad associated with each of the plurality of test structures. the electron beam pad is selectively targeted by sampling with , the electron beam pad comprising a logic device having a plurality of electrically connected elongated metal segments; and
selectively causing additional fabrication steps to be performed on the product IC wafer based at least in part on measurements obtained from the test structures;
Including, IC manufacturing method. 2. The method of claim 1, wherein obtaining electron beam excitation measurements comprises selectively targeting electron beam target pads having an asymmetric aspect ratio. 2. The method of claim 1, wherein obtaining electron beam excitation measurements comprises obtaining only a single pixel measurement from each electron beam pad that is targeted. 2. The method of claim 1, wherein selectively causing additional fabrication steps to be performed on the product IC wafer comprises determining whether one or more of the initial fabrication steps are to be reprocessed. 2. The method of claim 1, wherein selectively causing additional fabrication steps to be performed on the product IC wafer comprises determining whether to perform the additional fabrication steps. As an IC manufacturing method,
The IC manufacturing method is at least
subjecting a product IC wafer to initial fabrication steps;
obtaining electron beam excitation measurements from a plurality of test structures installed on the product IC wafer - using an electron beam spot having a long axis, an electron beam pad associated with each of the plurality of test structures is selectively targeted to , wherein the electron beam pad comprises a logic device having a plurality of electrically connected elongated metal segments; and
selectively causing additional fabrication steps to be performed on the product IC wafer based at least in part on measurements obtained from the test structures;
Including, IC manufacturing method. 7. The method of claim 6, wherein scanning efficiency is maximized by shaping each electron beam spot to match the size and shape of each of the targeted electron beam pads. 7. The method of claim 6, wherein each of the targeted electron beam pads has a first dimension in a scanning direction of the corresponding electron beam that matches a major axis of the electron beam spot, and targeting at least some of the targeted electron beam pads and the electron beam pads are varied in a second dimension perpendicular to the first dimension. 7. The method of claim 6, wherein each of the targeted electron beam pads is disposed along a linear scan line, and wherein a long axis of the electron beam spot is oriented perpendicular to the scan line. 7. The method of claim 6, wherein obtaining electron beam excitation measurements comprises obtaining fewer than 10 pixel measurements from each electron beam pad that is targeted. 11. The method of claim 10, wherein obtaining electron beam excitation measurements comprises obtaining only a single pixel measurement from each electron beam pad that is targeted. 7. The method of claim 6, wherein selectively causing additional fabrication steps to be performed on the product IC wafer comprises determining whether one or more of the initial fabrication steps are to be reprocessed. 7. The method of claim 6, wherein selectively causing additional fabrication steps to be performed on the product IC wafer comprises determining whether to perform the additional fabrication steps. As an IC manufacturing method,
The IC manufacturing method is at least
subjecting a product IC wafer to initial fabrication steps;
obtaining electron beam excitation measurements from a plurality of test structures installed on the product IC wafer, wherein an electron beam pad associated with each of the plurality of test structures is selectively targeted along a linear scan direction; the beam pad includes a logic device having a plurality of electrically connected elongated metal segments; and
selectively causing additional fabrication steps to be performed on the product IC wafer based at least in part on measurements obtained from the test structures;
Including, IC manufacturing method. 15. The method of claim 14, wherein each of the targeted electron beam pads has at least two of the elongated metal segments that are identical in size and shape. 15. The method of claim 14, wherein obtaining electron beam excitation measurements comprises obtaining fewer than 10 pixel measurements from each electron beam pad that is targeted. 17. The method of claim 16, wherein obtaining electron beam excitation measurements comprises obtaining only a single pixel measurement from each electron beam pad that is targeted. 15. The method of claim 14, wherein obtaining electron beam excitation measurements comprises selectively targeting with an electron beam spot having a long axis oriented perpendicular to the linear scan direction. 15. The method of claim 14, wherein selectively causing additional fabrication steps to be performed on the product IC wafer comprises determining whether one or more of the initial fabrication steps are to be reprocessed. 15. The method of claim 14, wherein selectively causing additional fabrication steps to be performed on the product IC wafer comprises determining whether to perform the additional fabrication steps.

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