JP2564440B2 - Method of manufacturing chip with in-wafer position indication - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a chip with an in-wafer position indication.

[0002]

2. Description of the Related Art Providing a symbol or pattern in an LSI chip to show where the wafer was located plays a major role in defect analysis after dicing, especially after packaging. The method of forming the symbol or pattern is described in JP-A-58-51513,
Although disclosed in Japanese Patent Application Laid-Open No. 2-101729, both of them have a problem that a large device modification is required to add a function.

Therefore, in a general LSI manufacturing factory, it is difficult to give the above-mentioned symbols to the chips, and it has been completely unknown where the chips are located on the wafer after dicing the wafer.

[0004]

When it is known from which position on the wafer the LSI chip is cut out, when a trouble occurs in a package product manufactured using the chip, it has a great effect on failure analysis. . The present invention has been made in view of the above circumstances, and has developed a technique for facilitating the analysis when a defect is found in the future by displaying the position on a chip in a wafer by a simple method. It is a thing. That is, the conventional LSI
It is an object of the present invention to provide a chip manufacturing method capable of providing an in-wafer position indication to a chip without significantly modifying the manufacturing factory.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a chip having a position indicating symbol indicating the position of a semiconductor chip in a raw wafer before dicing,
During the exposure process of the wiring process of the in-wafer chip, the underlayer of the in-wafer chip position display pattern is exposed by using the first reticle formed in a part of the device area of each chip, and then the positional information for the underlayer is exposed. The second reticle thus formed is used for exposure to form a position display pattern in each chip.

[0006]

By providing the LSI chip with a symbol or a pattern indicating where the wafer was located, the chip can be analyzed back to the wafer stage when a defect occurs. As a specific method of forming the original position display pattern in the wafer on the in-wafer chip, a position on a part of the device region of each chip is exposed during the exposure process of the wiring process of the in-wafer chip such as polysilicon wiring or Al wiring. Exposure is performed using a first reticle on which a base of a display pattern is formed, and then exposure is performed using a second reticle on which each position information having a predetermined deviation from the center of the base is formed in the base, An in-wafer chip position display pattern is formed by the combination.

FIG. 1 is a schematic view for schematically explaining this method. In the first reticle 1 shown in FIG. 1A, a certain underlayer 3 is formed in the area of each chip 2 on which a device is formed and drawn around a certain position deviated from the center of each chip. It is a thing. The shape of the base 3 is not limited, but is, for example, a circle having a diameter of about 50 μm, and in the case of a positive resist, it is a chrome pattern.

After the normal resist coating is applied to the wafer on which the wiring has not been formed, the normal exposure is performed by the first reticle 1 using the reduction projection exposure apparatus. First reticle 1
In, a chrome pattern imitating a wafer or a shot map is formed in a part of the device area. As a result, a pattern which is not removed by development is formed on the wafer.

Next, the first reticle 1 is exchanged with the second reticle 4 without lowering the wafer from the XY stage, and then the alignment and alignment of the first reticle 1 during exposure is performed.
Exposure is performed using the data. In the second reticle 4 shown in FIG. 1 (b), shots 6 are drawn in the above-described base material at respective positions deviated from the center. When the second reticle 4 is exposed, each shot 6 is shifted according to the shot position and is exposed. For example, if the shot is located near the orientation flat, a negative shift is applied in the Y direction. In order to perform this shift on the entire surface of the wafer, the step pitch of the shot layout of the reduction projection exposure apparatus may be increased by an amount calculated from the original step pitch and the diameter of the underlying pattern. A hole pattern is formed in the second reticle 4 at the same coordinates as the center coordinates of the base pattern of the first reticle 1. As a result, the hole pattern corresponding to the shot position is transferred to the resist base pattern on the wafer transferred by the first reticle 1.

The wafer is subjected to usual development and etching. As a result, due to the combination of the different positions of the base and the shot, as shown in FIG.
The internal position display pattern 11 is formed.

[0011]

FIG. 2 is an explanatory view showing a first reticle 1 for forming an underlayer for giving an in-wafer position indication according to an embodiment of the present invention. This reticle 1 has chips R1, R2, ~ R
The circular base is specified by the row (row) indicated by n and the column (Column) represented by C1, C2, and ~ Cm, each centering on the position of the coordinates (x, y) deviated from the center of the chip. 3 is formed. This base 3 is shown in FIG.
The chrome part (hatched part) on the reticle as shown in FIG. 2 is a substantially circular shape, and the dimensions on the wafer are diameter 31 = 60 μm, orientation flat 32 = 20 μm, and orientation flat center angle 33 = 19.5 degrees. did.

FIG. 3 shows the second reticle 4 forming the shot 6. The second reticle 4 also has a chip R
1, R2, ~ Rn and C1, C2, ~ Cm, and a shot 6 is formed at a position of coordinates (x + α, y + β) deviated from the center of the base formed by the first reticle 1. . As shown in FIG. 5, this shot 6 has a horizontal dimension 61 and a vertical dimension 62 of 3 μm (dimensions on the wafer) in a region that becomes chrome on the reticle.
It has a square shape.

[0013]

According to the present invention, it is possible to form a symbol or a pattern indicating a chip position with a commercially available standard reduction projection exposure machine (stepper). Only one dedicated reticle per product is specifically required to form the mark.

According to the method of the present invention, the object can be easily achieved at a low cost without any major modification of the apparatus. Further, there is no trouble such as a transfer error due to the device modification, and there is no need for maintenance. The required time is 30 minutes per product (25 wafers), and the influence on the production efficiency can be almost ignored. The pattern formed by this method greatly contributes to the defect analysis after dicing and the evaluation of the manufacturing process such as the correlation investigation of wafer probing.

[Brief description of drawings]

FIG. 1 is a schematic explanatory view of a method of the present invention.

FIG. 2 is an array diagram of a first reticle according to the embodiment of the present invention.

FIG. 3 is an array diagram of a second reticle according to the embodiment of the present invention.

FIG. 4 is a shape diagram of a base of a reticle according to an embodiment of the present invention.

FIG. 5 is a shape view of a shot of a reticle according to an embodiment of the present invention.

[Explanation of symbols]

 1 First Reticle 2 Chip 3 Base 4 Second Reticle 5 Chrome 6 Shot 10 Wafer 11 Pattern 12 Chip

Claims (1)

(57) [Claims] 1. An exposure process in a wiring process for a chip in a wafer is performed by exposing a base of an in-wafer chip position display pattern using a first reticle formed in a part of a device region of each chip, and then exposing the base. On the other hand, a method of manufacturing a chip with an in-wafer position indication is characterized by exposing by using a second reticle on which position information is formed to form a position indication pattern in each chip.