JP3333603B2 - Chip with position indication in wafer and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip having an in-wafer position indication and a method of manufacturing the chip.

[0002]

2. Description of the Related Art If it is possible to determine from which position on a wafer a chip has been cut out after dicing, when a defect occurs in a package product in which the chip is incorporated, it plays a large role in the analysis of the defect. It has a tremendous effect. For this reason, it has been conventionally performed to form, on each chip, a symbol or a pattern indicating from which position on the wafer the chip was cut.

A method of forming a symbol or a pattern representing the position of each chip in a wafer on each chip is disclosed in
No. 5,515,513 and Japanese Patent Application Laid-Open No. 2-101729. In these methods, there is a problem that the device needs to be largely remodeled in order to form a symbol or the like on a chip. Therefore, a method has been proposed in which a pattern representing the position of a chip in a wafer is formed on the chip without extensive modification of the apparatus (see Japanese Patent Application Laid-Open No. 5-175093). In this method, a pattern simulating the shape of a wafer is formed on each chip, and a position display pattern indicating the position of each chip is formed on this pattern.

[0004]

The above-described method of forming a pattern simulating the shape of a wafer on each chip does not require a significant modification of the apparatus, but each chip has only a mark indicating a rough position in the wafer. Do not show. Therefore, there is a problem that the position of each chip in the wafer cannot be accurately determined.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a chip provided with an in-wafer position display capable of accurately determining the position of each chip in a wafer after dicing, and a method of manufacturing the chip.

[0006]

According to the present invention, there is provided a method of manufacturing a chip provided with an in-wafer position display, which simulates an array pattern of a plurality of chips formed on a single wafer. A first step of exposing the display pattern to each chip in a wafer using a first reticle in which a display pattern is formed in a part of each device region; By using a second reticle on which a position pattern for displaying a position is formed, by positioning and exposing the second reticle relative to the wafer on which the display pattern has been exposed, And forming a position mark indicating the position of each chip in the wafer on the display pattern formed on the chip.

Instead of transferring the position display pattern using the second reticle, the position mark is irradiated by irradiating the corresponding position of each chip on the array pattern imprinted on each chip with condensed light. May be formed. In order to achieve the above object, a chip provided with an in-wafer position display of the present invention has a display pattern imitating an array pattern of a plurality of chips formed in one wafer, and a display pattern formed on the display pattern. And a position mark indicating a position in the wafer.

Here, the array pattern refers to a pattern representing the entire area where one wafer is exposed, and is divided into areas for a plurality of chips exposed at one time. Also,
The device area refers to an area for each chip of the reticle on which a pattern to be transferred to each chip is formed.

[0009]

According to the method of manufacturing a chip with an in-wafer position display of the present invention, first, a display pattern is transferred to each chip. Next, the display pattern transferred to each chip
A position pattern for displaying the position of each chip is transferred. The display pattern transferred to each chip is divided from each other for each area of a plurality of chips, and a position mark is formed on this display pattern. This position mark indicates the position of each chip in the wafer. Therefore,
Even after dicing the wafer, by observing the display pattern formed on the chip, it is possible to accurately determine from which position on the wafer the chip has been cut.

In this case, when the array pattern imprinted on each chip is irradiated with condensed light for indicating the position of each chip, a position mark can be formed without using the second reticle. . Therefore, the number of exposure steps is reduced by one, and the use efficiency of the exposure apparatus is improved. Further, since the display pattern on which the position mark indicating the corresponding position in the wafer is formed is formed on the chip with the in-wafer position display of the present invention, even after dicing the wafer, the chip By observing the display pattern formed on the wafer, it is possible to accurately determine from which position on the wafer the chip has been cut.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of manufacturing a chip with an in-wafer position indication according to the present invention will be described below with reference to the drawings.
Here, an example is shown in which a method of manufacturing a chip with an in-wafer position display is applied to an LSI product (actual device). FIG.
FIG. 1A shows a first reticle, FIG. 2A is a plan view schematically showing the first reticle, and FIG. 2B is an enlarged view showing a display pattern transferred to each chip. Represents a chrome area. RA indicates an alignment mark.

The first reticle 10 is divided into nine regions 12 in which patterns corresponding to nine chips are formed, and the vertical and horizontal dimensions of this region 12 are both 6024 μm.
m. A scribe center line 14 is formed between the respective regions 12. At the upper left of each region 12 in the figure, a display pattern 16 imitating an array pattern is formed. The vertical dimension 18 of the display pattern 16 formed on the reticle 10 is 59.0 μm, and the horizontal dimension 20 is 51.5 μm
It is. The display patterns 16 are separated from each other by a distance 24 for each single exposure area 22 exposed at one time, and the distance 24 is 1.0 μm. The vertical dimension 26 and the horizontal dimension 28 of the single exposure area 22 are both 6.5 μm.

FIGS. 2A and 2B show a second reticle. FIG. 2A is a plan view schematically showing the whole of the second reticle, and FIG. 2B is an enlarged view of a position pattern for displaying the position of each chip itself. In the figure, a hatched portion represents a chrome region. RA indicates an alignment mark. This second
The reticle 30 is for transferring a position pattern 32 for displaying the position of each chip in the wafer to each chip of the wafer to which the display pattern 16 (see FIG. 1) has been transferred. The shape of the position pattern 32 is a square shape of 2.2 μm in both the vertical dimension 34 and the horizontal dimension 36 simulating the shape of a chip. Position pattern 32
Are formed in each of the nine regions 38 corresponding to the regions 12 (see FIG. 1). The coordinates of each area 38 are the coordinates (α, β) of the central area 38,
Are shifted by 2.2 μm in accordance with the position of.

A method of giving an in-wafer position indication to a chip using the first reticle 10 and the second reticle 30 will be described with reference to FIG. Wafer 40 before wiring formation
Is subjected to a normal resist coating, and then a normal exposure is performed by a first reticle 10 (see FIG. 1) using a reduction projection exposure apparatus. Since the display pattern 16 (see FIG. 1) is formed on the first reticle 10, the display pattern 16 is transferred into the wafer. Next, the wafer 40
Reticle 10 without lowering it from the XY stage.
Is replaced with a second reticle 30 (see FIG. 2), and exposure is performed using alignment data of the first reticle 10 at the time of exposure. At the time of exposure of the second reticle 30, each time exposure is performed, a shift is performed according to the exposure position, and exposure is performed. For example, in the case of exposure located near the orientation flat, a negative shift is applied in the Y direction. In order to perform this shift over the entire wafer, the step pitch of the shot layout of the reduction projection exposure apparatus may be increased by an amount calculated from the original step pitch and the diameter of the entire exposure area display pattern. Thereby, the position pattern 32 (see FIG. 2) for displaying the position of each chip in the wafer is transferred to the display pattern 16 transferred to the wafer using the first reticle 10.

As a result, for example, chip 42
As shown in (b), a position mark 32a indicating the position of the chip 42 in the wafer is formed on the display pattern 16 formed on the chip 42. In addition, chip 4
As shown in FIG. 3C, the display pattern 16 formed on the chip 42 has the chip 4 in the wafer.
A position mark 32b indicating the position of No. 4 is formed. These chips 42 and 44 are separated by using, for example, an optical microscope.
By observing at a magnification of 00, the position of each chip in the wafer 40 can be easily and accurately determined after dicing.

In the above embodiment, 51.5 μm × 59.0.
Since the display pattern is formed in an area of μm, it can be determined for each chip by observation at low magnification. However, assuming observation at high magnification, a smaller occupied area may be used. In the above embodiment, the position pattern is formed using the second reticle. However, the display pattern 16 transferred to the wafer may be irradiated with a spot of laser light or exposure light for displaying the position of each chip. May be used to form a position mark on each chip. Further, chip position coordinate information may be printed on the display pattern of each chip.

[0017]

As described above, according to the method of manufacturing a chip with the in-wafer position indication of the present invention, the position of each chip in the wafer is determined by using the first reticle and the second reticle. Since the indicated position mark is formed on each chip, the position of each chip in the wafer can be accurately determined after dicing without significantly modifying the apparatus.

Further, since the position mark indicating the position of each chip in the wafer is formed on the chip having the in-wafer position display of the present invention, the position of each chip in the wafer is accurately determined after dicing. it can.

[Brief description of the drawings]

FIGS. 1A and 1B show a first reticle. FIG. 1A is a plan view schematically showing the first reticle, and FIG. 1B is an enlarged view showing a display pattern.

FIGS. 2A and 2B show a second reticle. FIG. 2A is a plan view schematically showing the second reticle, and FIG. 2B is an enlarged view showing a position pattern.

FIG. 3 is a diagram showing a display pattern of a chip to which an in-wafer position is displayed using a first reticle and a second reticle.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st reticle 12, 38 area 16 Display pattern 22 1 time exposure area 30 2nd reticle 32 Position pattern 32a, 32b Position mark

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 1/08

Claims (3)

(57) [Claims] 1. A first reticle in which a display pattern imitating an array pattern of a plurality of chips formed in one wafer is formed in a part of each device region, is applied to each chip in the wafer. A first step of exposing the display pattern, and using a second reticle on which a position pattern for displaying the position of each chip with respect to the display pattern is formed, the display pattern is exposed. A second position mark indicating the position of each chip in the wafer is formed on the display pattern formed on each chip by positioning and exposing the second reticle relative to the wafer. And a method for manufacturing a chip with an in-wafer position indication. 2. The position mark is formed by irradiating condensed light on a corresponding position of each chip on the array pattern imprinted on each chip, instead of the second step. 2. The method for manufacturing a chip with an in-wafer position indication according to claim 1, wherein: 3. A display device comprising: a display pattern imitating an array pattern of a plurality of chips formed in one wafer; and a position mark formed on the display pattern and indicating a position in the wafer. And chips.