JP2011082407A - Semiconductor chip and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip capable of achieving both exposure position identification when a surface of a semiconductor wafer is divided and exposed, and semiconductor chip position identification for identifying a position of each semiconductor chip, not to mention that it is possible to identify a plurality of semiconductor chips manufactured from the same semiconductor wafer; and to provide a method of manufacturing the semiconductor chip. <P>SOLUTION: The semiconductor chip includes: at least one or more exposure position identification parts 41 for identifying the exposure position of each divisional exposure process on the surface of the semiconductor wafer, when the surface of the semiconductor wafer is divided and exposed a plurality of times at different exposure positions; and at least one or more semiconductor chip position identification parts 42 for identifying positions of respective semiconductor chips 10 in a single divisional exposure process, when regions corresponding to the plurality of semiconductor chips are simultaneously exposed through the single divisional exposure process. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor chip and a manufacturing method thereof.

  Conventionally, as technologies related to the semiconductor chip and the like, for example, Japanese Patent Laid-Open Nos. 4-288811, 7-335510, 11-26333, 11-214274, and 2006 are disclosed. JP-A-269598, JP-A-2007-42882, JP-A-2007-59605, and the like have already been proposed.

  The semiconductor chip manufacturing method according to the above-mentioned Japanese Patent Application Laid-Open No. 4-28811 is configured to display a number indicating the position in the semiconductor wafer in each effective chip of the semiconductor wafer.

  In addition, the semiconductor chip according to the above-mentioned Japanese Patent Application Laid-Open No. 7-335510 is provided with an identifier including at least information indicating the manufacturing order of the semiconductor chips.

  Further, the semiconductor chip according to the above Japanese Patent Laid-Open No. 11-26333 is configured such that an information management two-dimensional barcode pattern is projected and exposed as chip ID information on each chip arranged on the wafer surface. .

  Further, in the semiconductor device manufacturing method according to the above-mentioned Japanese Patent Application Laid-Open No. 11-214274, the position of a chip in the wafer can be identified by visual recognition on the element portion of the wafer that is divided into a plurality of chips. A method of manufacturing a semiconductor device for forming an identification information portion, wherein an identification number indicating the position of the device portion in the wafer is given to each device portion of the wafer, and is given to all the device portions in the wafer. Forming a number group including all of the identified identification numbers in each element part, or forming a map showing the positions of all element parts on the wafer in each element part, and dividing the wafer into a plurality Prior to forming the chip, an identification information part is formed by marking with a laser at the position of the identification number given to the element part in the number group formed on each element part. Or those configured as a second step of marking to form the identifying information section using the laser to the position of the active element of the map which is formed in the respective element units.

Furthermore, the manufacturing method of the solid-state imaging device according to the above Japanese Patent Laid-Open No. 2006-269598 is a manufacturing method of a solid-state imaging device including a solid-state imaging device portion formed on a semiconductor substrate and a plurality of electrode pads.
A manufacturing information marking step of marking manufacturing information of the solid-state imaging device in a region between the regions where the plurality of electrode pads are formed on the semiconductor substrate is included.

In addition, a semiconductor chip according to the above Japanese Patent Application Laid-Open No. 2007-42882 includes a semiconductor integrated circuit portion in which an integrated circuit is formed on a rectangular substrate, and a dicing uncut region located around the semiconductor integrated circuit portion. In a semiconductor chip provided with a scribe part,
Provided in the scribe unit is an information display unit that displays individual management information in the manufacturing process by combining a plurality of layer patterns.

Further, the semiconductor chip according to the above-mentioned Japanese Patent Application Laid-Open No. 2007-59605 is a semiconductor chip manufactured by dividing a wafer processed for each lot for each chip,
An identifier indicating the lot name or wafer number to which the semiconductor device belongs is attached to the surface of the chip.

JP-A-4-288811 JP 7-335510 A Japanese Patent Laid-Open No. 11-26333 JP-A-11-214274 JP 2006-269598 A JP 2007-42882 A JP 2007-59605 A

  By the way, the problem to be solved by the present invention is that it is possible to identify a plurality of semiconductor chips manufactured from the same semiconductor wafer, as well as exposure position identification when the semiconductor wafer surface is divided and exposed. It is another object of the present invention to provide a semiconductor chip and a method for manufacturing the same, which enables both the semiconductor chip position identification for identifying the position of each semiconductor chip.

That is, the invention described in claim 1 identifies at least one exposure position of each of the divided exposures on the surface of the semiconductor wafer when exposing the surface of the semiconductor wafer by dividing the exposure position into a plurality of times at different exposure positions. Two or more exposure position identification units;
When simultaneously exposing a region corresponding to a plurality of semiconductor chips in the one-time division exposure, at least one semiconductor chip position identification unit for identifying the position of each semiconductor chip in the one-time division exposure is provided. This is a semiconductor chip characterized by the above.

The invention described in claim 2 is the semiconductor chip according to claim 1,
The exposure position identification unit is a semiconductor chip comprising an exposure position identification mark for identifying an exposure position of each divided exposure and an auxiliary mark for assisting position identification of the exposure position identification mark.

Furthermore, the invention described in claim 3 is the semiconductor chip according to claim 1 or 2,
The exposure position identification unit and the semiconductor chip position identification unit are semiconductor chips formed using a manufacturing process of a semiconductor device.

According to a fourth aspect of the present invention, in the semiconductor chip of the second aspect,
The exposure position identification unit is a semiconductor chip characterized in that the position of the exposure position identification mark is moved in accordance with an operation of moving the position of each divided exposure.

Furthermore, in the invention described in claim 5, when the exposure is performed by dividing the surface of the semiconductor wafer into a plurality of times with different exposure positions, the exposure position of each of the divided exposures on the surface of the semiconductor wafer is identified. An exposure position identification portion forming step for forming two or more exposure position identification portions;
When simultaneously exposing a region corresponding to a plurality of semiconductor chips in the single divided exposure, at least one semiconductor chip position identifying unit for identifying the position of each semiconductor chip in the single divided exposure is formed. A semiconductor chip manufacturing method comprising: a semiconductor chip position identification portion forming step.

  According to the first aspect of the invention, it is possible to identify a plurality of semiconductor chips as compared with the case where this configuration is not provided, and the exposure position when the surface of the semiconductor wafer is divided and exposed. Both identification and semiconductor chip position identification for identifying the position of each semiconductor chip are possible.

  Further, according to the invention of claim 2, it is possible to easily identify the exposure position when the semiconductor wafer surface is divided and exposed as compared with the case where the present configuration is not provided.

  Furthermore, according to the invention described in claim 3, the exposure position identification unit and the semiconductor chip position identification unit can be formed without adding a new process as compared with the case where the present configuration is not provided. .

  According to the fourth aspect of the present invention, the position of the exposure position identification mark can be reliably varied in accordance with the movement of the divided exposure position as compared with the case where the present configuration is not provided.

  Furthermore, according to the invention described in claim 5, it is possible to identify a plurality of semiconductor chips as compared with the case where this configuration is not provided, and to divide and expose the surface of the semiconductor wafer. It is possible to provide a semiconductor chip capable of both the exposure position identification at the time and the semiconductor chip position identification for identifying the position of each semiconductor chip.

1 is a schematic diagram showing a semiconductor chip according to Embodiment 1 of the present invention. It is sectional drawing which shows the semiconductor wafer for manufacturing the semiconductor chip which concerns on Embodiment 1 of this invention. It is a schematic diagram which shows the manufacturing process of the semiconductor chip which concerns on Embodiment 1 of this invention. It is a plane block diagram which shows the exposure area | region of a semiconductor wafer. It is a schematic diagram which shows the exposure state of a semiconductor wafer. It is a block diagram which shows the semiconductor chip manufactured in the same exposure area | region of a semiconductor wafer. It is a plane block diagram which shows a semiconductor chip. It is a circuit diagram which shows the equivalent circuit of a semiconductor chip. It is a block diagram which shows the identification mark of a semiconductor chip. It is a block diagram which shows a shot address pattern. It is a block diagram which shows the formation state of a shot address pattern. It is a block diagram which shows the shot address pattern according to the exposure area | region of a semiconductor chip. It is a block diagram which shows the formation state of the shot address pattern according to the exposure area | region of a semiconductor chip. It is a block diagram which shows the formation state of the shot address pattern according to the exposure area | region of a semiconductor chip. It is a block diagram which shows the chip address pattern according to a semiconductor chip. It is a block diagram which shows the modification of a shot address pattern. It is a block diagram which shows the modification of a shot address pattern. It is a block diagram which shows the modification of a shot address pattern.

  Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1
FIG. 2 shows a semiconductor wafer for manufacturing a self-scanning light emitting element array chip (SLED: SELF-SCANNING LIGHT-EMITTING DEVICE) as a semiconductor chip according to the first embodiment of the present invention. As shown in FIG. 2, the semiconductor wafer 1 includes a p-type wafer substrate 2 made of, for example, a GaAs substrate or the like, a p-type layer 3 as a first layer, and an n-type layer 4 as a second layer. A plurality of semiconductor layers including a p-type layer 5 as a third layer and an n-type layer 6 as a fourth layer are sequentially stacked. In FIG. 2B, reference numeral 7 denotes an orientation flat (OF) indicating the crystal orientation of the wafer substrate 2.

  The self-scanning light emitting element array chip as the semiconductor chip uses an exposure apparatus such as a stepper (reduction projection type exposure apparatus) after applying a photoresist on the surface of the semiconductor wafer 1 as shown in FIG. Development is performed after exposure according to a predetermined pattern, so-called photolithography process in which the photoresist is peeled off after etching, and a process for forming an electrode made of metal or a conductive material, A plurality of self-scanning light emitting element array chips are simultaneously manufactured through a semiconductor device manufacturing process in which the insulating material coating process is repeated as necessary.

  The self-scanning light emitting element array chip is manufactured as follows, for example.

  This self-scanning light emitting element array chip includes, for example, (1) a process of forming an electrode on the semiconductor wafer 1, (2) a substrate etching process (GETH), (3) a process of forming an insulating film, a protective film, etc. The semiconductor device is manufactured through a semiconductor device manufacturing process including 4) a film forming process for forming a wiring and a process for forming a wiring, and (5) a process of forming a contact hole.

  At that time, as shown in FIG. 3A, the self-scanning light-emitting element array chip is formed after, for example, (2) applying a photoresist (not shown) to the surface of the semiconductor wafer 1 in the step of etching the substrate. First, using a first mask 31 having an opening 30 of a first pattern predetermined according to the structure of the self-scanning light emitting element array on the surface of the semiconductor wafer 1 coated with this photoresist. A photolithography process in which exposure is performed, double exposure is performed using a second mask 33 having openings 32 of a predetermined second pattern, development is performed, etching is performed, and the photoresist is peeled off As a result, a substrate etching process or the like for forming a gate electrode region by performing an etching process on the p-type wafer substrate 2 of the semiconductor wafer 1 is performed.At that time, in the first exposure and double exposure using the masks 31 and 33, as shown in FIG. 3A, the first and second masks 31 and 33 having different patterns are used. Different patterns are formed by the first exposure and the double exposure.

At this time, in order to expose the surface of the semiconductor wafer 1 using a mask, as shown in FIG. 4, in order to efficiently manufacture a self-scanning light emitting element array chip, a plurality of surfaces (for example, the surface of the semiconductor wafer 1 are used). , 7 rows × 9 columns) of exposure areas 34 _3-1 , 34 _3-2 ... And divided exposure areas 34 _3-1 , 34 _3-2. Each time, as shown in FIG. 5, using a stepper (reduction projection type exposure apparatus) (not shown) having a mask 31 (33) incorporated therein, for example, division exposure (stepper shot) is performed by ultraviolet rays (UV) or the like. It is configured. Further, as shown in FIG. 6, one divided exposure region 34 subjected to the one-time divided exposure simultaneously exposes regions 35 ₁ , 35 ₂ ... Corresponding to a plurality of light emitting element array chips. Is set to Incidentally, the plurality of light emitting element array chips are individually cut by a dicing area 36 formed of concave grooves formed between regions 35 ₁ , 35 ₂ ... Corresponding to the plurality of light emitting element array chips after manufacturing. To be separated.

  FIG. 7 shows one cathode-scanning self-scanning light-emitting element array chip 10 formed on the surface of the semiconductor wafer 1 manufactured through the semiconductor manufacturing process as described above. FIG. 8 is a circuit diagram showing an equivalent circuit of the self-scanning light-emitting element array 11 formed on the self-scanning light-emitting element array chip 10.

As shown in FIGS. 7 and 8, the self-scanning light-emitting element array 11 is roughly divided into light-emitting sections 12 arranged linearly along the scanning direction which is the longitudinal direction of the light-emitting element array 11, and the light emission. It is comprised from the shift part 13 arrange | positioned in the width direction which cross | intersects the longitudinal direction of the light emitting element array 11 of the part 12. FIG. The light emitting unit 12 includes writing light emitting elements L _{1 to} L ₁₂₈ including a plurality of (for example, 128 or 256) light emitting thyristors arranged linearly along the scanning direction of the light emitting element array 11. Yes. These light emitting elements L _{1 to} L ₁₂₈ for writing are constituted by cathode common type light emitting thyristors, and the cathode electrode is grounded via a common electrode formed on the back surface of the p type wafer substrate 2. . A write signal φI is applied to the anode electrodes of the write light emitting elements L _{1 to} L ₁₂₈ via the write line 15 and a resistor. Further, the gate electrodes of the write light emitting elements L _{1 to} L ₁₂₈ are connected to the corresponding gate electrodes of the switching elements T _{1 to} T ₁₂₈ of the shift unit 13.

On the other hand, the shift unit 13 includes switching elements T _{1 to} T ₁₂₈ provided corresponding to the light emitting elements L _{1 to} L ₁₂₈ for writing as described above. These switching elements T _{1 to} T ₁₂₈ are constituted by, for example, a cathode common type light emitting thyristor, and the cathode electrode is grounded via a common electrode 15 formed on the back surface of the p type wafer substrate 2. Yes. Also, among the switching elements T _{1 to} T ₁₂₈ , the first transfer clock pulse φ 1 is connected to the current limiting resistor and the first transfer line 16 to the anode electrodes of the even-numbered switching elements T _{2 to} T _128. The second transfer clock pulse φ2 is applied to the anode electrodes of the odd-numbered switching elements T _{1 to} T ₁₂₇ via the current limiting resistor and the second transfer line 17. Yes. Further, a power supply voltage V _GK is applied to the gate electrodes of the switching elements T _{1 to} T ₁₂₈ via the resistor and the power supply line 18. Further, between the gate electrodes of the adjacent switching elements T _{1 to} T ₁₂₇ , diodes D _{1 to} D ₁₂₈ are interposed such that the direction facing the switching elements T _{1 to} T ₁₂₇ having a smaller number is the forward direction. .

  In FIG. 7, reference numerals 19 to 22 denote a write line, a first transfer line, a second transfer line, a power supply line, a write line for energizing the first and second transfer lines, and a first transfer line and a second transfer line. The electrode pads for power supply are shown respectively.

  Next, the operation of the self-scanning light-emitting element array 11 configured as described above will be described. In the self-scanning light-emitting element array 11, the start pulse φs is first set to the L level (about 0 V) and at the same time the second The transfer clock pulse φ2 is set to H level (about 2 to about 4 V), and the switching element T1 is turned on. Thereafter, the start pulse φs is immediately returned to the H level.

When the switching element T ₁ is turned on, the potential of the gate electrode G1 of the switching element T ₁ drops from the voltage VGK (for example, 5V) of the power supply line to about 0V. Accordingly, the write voltage of the signal φI is, if the diffusion potential (about 1V) or more pn junctions of the write light emitting element L _1, can be a write light-emitting element L1 and the light-emitting state.

Next, when the first voltage of the transfer clock pulses φ1 and high level, the switching element T ₂ is turned on. Then, the potential of the gate electrode G ₂ of the switching element T ₂ drops from 5V, which is the voltage VGK of the power supply line, to almost 0V. The influence of the voltage drop of the switching element T ₂ is transmitted to the gate electrode G ₃ of the switching element T ₃ adjacent to the right side via the diode D _2, and the potential of the gate electrode G ₃ of the switching element T ₃ is about 1V. It becomes (forward rise voltage of the diode D ₂ (equal to the diffusion potential)).

On the other hand, the influence of the voltage drop of the switching element T ₂ is in a reverse bias state with respect to the diode D ₁ adjacent to the left side, so that the potential connection to the gate electrode G ₁ of the diode D ₁ is Not performed, the potential of the gate electrode G ₁ of the switching element T ₁ remains at 5V.

By the way, the ON potential of the light emitting thyristors that are the light emitting elements L _{1 to} L ₁₂₈ for writing can be approximated by a voltage higher than the potential of the gate electrode G by the diffusion potential (about 1 V) of the pn junction. Therefore, if the write voltage φI applied to the anode electrodes of the write light-emitting elements L _{1 to} L ₁₂₈ is set higher than the on-potential, the light-emitting thyristor is turned on and emits light.

Here, a high level voltage is applied to the second transfer clock pulse φ2 in a state in which the writing light emitting element L is on. The second transfer clock pulse φ2 is simultaneously applied to the switching element T ₃ and the switching element T ₅ , but has a high level voltage value of about 2 V (voltage necessary for turning on the switching element T ₃ ) or more. If it is set to about 4 V (voltage necessary for turning on the switching element T ₅ ) or less, only the switching element T ₃ is turned on, and other switching elements T ₅ are kept off. it can.

When the high level voltage of the first transfer clock pulse φ1 is cut off, the switching element T ₂ is turned off, the light emitting element L ₂ is turned off, and the light emitting element L ₃ is turned on so that the on state is turned on. Can be transferred. Therefore, the ON state is transferred by switching the high level voltage and the low level voltage of the two first and second transfer clock pulses φ1 and φ2.

Now, assuming that the voltage of the first transfer clock pulse φ1 is at a high level and the switching element T ₂ is in an on state, the potential of the gate electrode G ₂ is assumed to be the voltage V _GK (here, 5 V) of the power supply line. ) To almost 0V. Therefore, when the voltage of the write signal φI is equal to or higher than the diffusion potential (about 1 V) of the pn junction, the write light emitting element L ₂ can be brought into a light emitting state.

In contrast, the gate electrode G ₁ of the switching element T ₁ is about 5V, the gate electrode G ₃ of the switching element T ₃ is about 1V. Therefore, the writing voltage of the light emitting element L1 is about 6V, and the writing voltage of the light emitting element L3 is about 2V. Therefore, the voltage of the write signal φI that can be written only to the light emitting element L2 is in the range of 1 to 2V. By setting the voltage of the write signal φI to 1 to 2V, only the light emitting element L2 can emit light.

  When the light emitting element L2 is turned on, that is, in a light emitting state, the light emission intensity of the light emitting element L2 is determined by the amount of current applied to the write signal φI, and image writing can be performed with an arbitrary intensity.

  In order to transfer the light emission intensity to the next light emitting element L, it is necessary to temporarily reduce the voltage of the write signal φI line to 0 V and turn off the light emitting element L2 that emits light.

As described above, the self-scanning light-emitting element array 11 switches the voltages of the first and second transfer clock pulses φ1 and φ2 and the voltage of the write signal φI line, thereby linearly changing according to a predetermined resolution. The writing light emitting elements L _{1 to} L ₁₂₈ arranged in a row can be sequentially scanned to emit light, and the number of bonding pads as terminals for switching the applied voltage is smaller than that of a normal light emitting element array. Thus, the area of the semiconductor chip can be reduced.

As shown in FIG. 5, the self-scanning light-emitting element array chip 10 operating as described above has a semiconductor wafer 1 having a layer structure as shown in FIG. 2, and a photoresist is applied to the surface of the semiconductor wafer 1. Thereafter, the entire surface is exposed by an aligner or the like, or a partial coating process using a stepper or the like, and further a manufacturing process of a semiconductor device in which an insulating material coating process is repeated as necessary, and then the switching elements T _{1 to} T _128. , Light emitting elements L _{1 to} L ₁₂₈ , diodes D _{1 to} D ₁₂₈ , resistance elements, first and second transfer clock pulses φ 1, φ 2 transfer lines 16, 17, write signal φI line 15, power supply line 18, etc. By forming on the surface of the semiconductor wafer 1, a large number (a plurality) of self-scanning light emitting element array chips 10 are manufactured at the same time.

  At this time, a large number of self-scanning light-emitting element array chips 10 are formed on the surface of the semiconductor wafer 1, and each self-scanning light-emitting element array chip 10 has a self-scanning light emission as shown in FIG. A device region 23 constituting the element array 11 and a dicing region 24 located on the outer periphery of the device region 23 and separated from the adjacent self-scanning light emitting element array 11 are configured. In the dicing region 24, as shown in FIG. 6B, dicing grooves 25 for cutting and separating the individual self-scanning light emitting element array chips 10 are formed. For example, it is set to have a width w of about 30 μm and a depth d of about 3 to 6 μm.

  By the way, in this embodiment, the self-scanning light emitting element array chip 10 is manufactured by subjecting the surface of the semiconductor wafer 1 as shown in FIG. When a defective product occurs in the self-scanning light-emitting element array chip 10, positional information such as where the self-scanning light-emitting element array chip 10 is formed on the surface of the semiconductor wafer 1 is tracked in order to analyze the cause. Need to investigate.

  Therefore, in this embodiment, as shown in FIG. 1, at least the exposure position of each divided exposure is identified inside the dicing groove 25 of the self-scanning light emitting element array chip 10 formed on the surface of the semiconductor wafer 1. A shot address pattern 41 as one or more exposure position identification units and a chip address pattern 42 as at least one semiconductor chip position identification unit for identifying the position of each semiconductor chip 10 in one divided exposure are provided. It is configured as follows.

  As the shot address pattern 41, for example, as shown in FIG. 10, a shot address mark 43 as an exposure position identification mark formed in a rectangular shape such as a square or a rectangle, and an outer periphery of the shot address mark 43 are surrounded. What consists of the scale mark 44 as an auxiliary | assistant mark formed in a rectangular shape is used. The shot address mark 43 and the scale mark 44 are for identifying the exposure position of each divided exposure 34. As shown in FIG. 4, the surface of the semiconductor wafer 1 has a plurality (for example, 7 rows × 9 columns). In the case of dividing the exposure area 12, as shown in FIG. 11, a plane corresponding to these 7 × 9 divided exposure areas 34 is flattened at a position 45 corresponding to the exposure position in the 7 × 9 squares. What displayed the rectangular dot 43 is used.

As shown in FIG. 13, when the shot address mark 43 is subjected to divided exposure 34 using a stepper (reduction projection type exposure apparatus) as shown in FIG. 12, in normal exposure, as shown in FIG. The exposure is performed by moving the mask so that the exposure area is continuous without any gap for each divided exposure 34. The maximum 46 for forming the shot address mark 43 is divided exposure 45 as shown in FIG. Each time the mask 46 is shifted by a minute amount by a minute distance ΔX in the X direction and by a minute distance ΔY in the Y direction, a flat rectangular dot 43 is formed at a position 45 indicating the divided exposure position inside the scale mark 44. Is done. The minute distances ΔX and ΔY are set to about ΔX = ΔY = 3 μm, for example, but of course may be set to a smaller value or a larger value. Further, the minute distances ΔX and ΔY are not necessarily the same value, and the values of ΔX and ΔY may be set to different values.

  The scale mark 44 is for assisting the discrimination of the position of the shot address mark 43, and one scale mark is a series of three shot address marks 43 as shown in FIGS. It is formed in a rectangular shape having the length. Further, the scale mark 44 is linearly arranged in two lines in the X direction and the Y direction with an interval corresponding to one shot address mark 43, and the scale mark is linearly arranged in the Y direction. A space for one shot address mark 43 is provided above and below 44, and as a result, the shot address mark 43 of 7 rows × 9 columns is formed so as to surround a rectangular shape. Yes.

  Here, when one scale mark 44 is formed to a length corresponding to three shot address marks 43, the shot address mark 43 is provided on the inner periphery of the scale mark 44. By comparing with the scale mark 44, the shot address mark 43 is located at the upper or left end of one scale mark 44, or at the center, or the scale mark 44 and the scale mark. This is because it is possible to easily determine whether the shot address mark 43 is positioned between the positions 43, and to determine the position of the 7 × 9 shot address mark 43 reliably and easily.

  On the other hand, the chip address pattern 42 is for identifying the position of each semiconductor chip in one division exposure 36, and is manufactured, for example, in one division exposure as shown in FIG. You may comprise by the serial number (1-N) according to the number (N pieces) of semiconductor chips to be.

Further, as the chip address pattern 42, as shown in FIG. 15B, 0 and 1 are represented by the presence or absence of a rectangular pattern similar to the shot address mark 43, and the number of the chip 10 is displayed by a binary system. You may comprise so that it may do. In FIG. 15B, 51 is displayed as the position of each semiconductor chip 10 with 0 when there is no pattern and 1 when there is a pattern. In the example of FIG. 15B, since the chip address pattern 42 is configured by a total of six rectangular patterns in which three patterns are arranged in two rows, 2 ⁶ = 64 from 0 to 63. Can be given different numbers. Note that the number of patterns constituting the chip address pattern 42 may be determined according to the number of chips in one shot.

  Further, as the chip address pattern 42, as shown in FIG. 15C, a numerical value is expressed in decimal notation by the number of rectangular patterns similar to the shot address mark 43. In this example, the number 53 is displayed as the chip address by the five rectangular patterns and the three rectangular patterns displaying the 1's place.

  As shown in FIG. 3B, these shot address mark 41 and chip address pattern 42 are formed in (2) substrate etching process in the semiconductor chip manufacturing process. It is formed by performing the first exposure and double exposure using a mask having openings 30 and 32 corresponding to the shape. In this case, for example, an etching process is performed according to the shape of the exposed portion of the semiconductor wafer 1 to form recesses according to the shapes of the shot address mark 41 and the chip address pattern 42.

  In the above configuration, in the semiconductor chip according to this embodiment, a plurality of semiconductor chips can be identified as follows, and the exposure position when the surface of the semiconductor wafer is divided and exposed Both identification and semiconductor chip position identification for identifying the position of each semiconductor chip are possible.

  That is, in the semiconductor chip according to this embodiment, as shown in FIG. 4, when manufacturing a self-scanning light emitting element array chip 10 as a semiconductor chip, an exposure apparatus such as a stepper is used to manufacture the semiconductor wafer 1. The surface is divided into a plurality of (for example, 7 rows × 9 columns) exposure regions 34 and exposed, and as shown in FIG. 6, a plurality of self-scanning light emitting element array chips 10 are obtained in one divided exposure 34. The area corresponding to the above is exposed at the same time.

  Then, on the surface of the device region of the self-scanning light-emitting element array chip 10, as shown in FIGS. 1 and 9, at least one exposure position identification unit for identifying the exposure position of each divided exposure 34 is provided. A shot address pattern 41 and at least one chip address pattern 42 as a semiconductor chip position identifying unit for identifying the position of each semiconductor chip 10 in one divided exposure are provided.

  Therefore, when a defective product or the like occurs in the manufactured self-scanning light-emitting element array chip 10, a magnifying glass is used for the shot address pattern 41 and the chip address pattern 42 of the self-scanning light-emitting element array chip 10. By observing visually or using a microscope, the shot address and the chip address can be immediately identified.

  At that time, the shot address pattern 41 indicating the shot address is composed of the shot address mark 43 and the scale mark 44, as shown in FIGS. By making the determination with reference, the position of the divided exposure 34 can be easily identified as 3 columns in the 5th row or 7 columns in the 5th row.

  Further, the chip address of the self-scanning light-emitting element array chip 10 is determined by a single divided exposure by discriminating numbers such as 1, 2, 3,... As shown in FIG. The position of each semiconductor chip 10 can be easily identified.

  As a result, according to the shot address pattern 41 of the self-scanning light emitting element array chip 10, the exposure position on the surface of one semiconductor wafer 10 can be easily identified. As a result of the exposure at the position, it is possible to easily determine the cause of the occurrence of a defective portion in the self-scanning light emitting element array chip 10.

  Further, according to the chip address pattern 42 of the self-scanning light-emitting element array chip 10, the position of the chip 10 in one divided exposure 34 can be easily identified. It is possible to easily determine the cause, for example, the mask corresponding to the chip 10 has a defective part such as a scratch, and a defective product is generated in the self-scanning light emitting element array chip 10 having the same chip address.

Embodiment 2
FIG. 16 shows a second embodiment of the present invention. In the second embodiment, the shape of the scale mark is different from that of the first embodiment.

  That is, in the second embodiment, for example, as shown in FIG. 16A, unlike the first embodiment, the scale mark 44 is formed in a rectangular shape having a length corresponding to three shot address marks 43. Rather than forming the shot address mark 43 in the same size and shape, the shot address mark 43 is formed along the X and Y directions at predetermined intervals so as to surround the region where the shot address mark 43 is formed. Are arranged in a straight line.

  In the second embodiment, for example, as shown in FIG. 16B, an E-type pattern 51 is arranged as a scale mark 44 so as to surround the shot address mark 43. In (3), the lower and right E-shaped patterns 51 are arranged so as to face outwards, thereby enabling discrimination between upper, lower, left and right.

  In the second embodiment, as shown in FIG. 16 (4), not all the scale marks 44 are formed in the same size and shape as the shot address marks 43, but the same size as the shot address marks 43. The scale mark 52 formed in a shape and the scale mark 53 formed in a size corresponding to a plurality (2 to 3) of the shot address marks 43 are alternately arranged. .

  Further, in the second embodiment, as shown in FIG. 16 (5), the pattern corresponding to the shot address mark is arranged in a matrix to form the scale mark 44, and the shot address mark 43 is arranged in a lattice pattern. Coordinates can be identified by placing them at the intersection.

  In the second embodiment, as shown in FIG. 16 (6), the scale mark is not arranged in a rectangular shape so as to surround the region where the shot address mark 43 is formed, but divided exposure of the semiconductor wafer 1 is performed. You may comprise so that the scale mark 44 may be arrange | positioned in the polygonal shape close | similar to the shape of a position. In this embodiment, the scale mark 44 is stepped and the step is graduated.

  Further, in the second embodiment, as shown in FIG. 16 (7), the scale mark 44 is formed in a thick straight line having an opening having a size corresponding to the shot address mark 43. For example, the openings 56 are arranged at intervals of one shot address mark, and the position of the opening 56 is a scale.

  Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

Embodiment 3
FIG. 17 shows a third embodiment of the present invention. In the third embodiment, the scale mark has a different shape from that of the first embodiment.

  That is, the third embodiment corresponds to the second embodiment, but the direction of the scale mark can be determined by making a part of the scale mark 44 different in shape from the other scale marks. Is given directionality.

  In FIG. 17A, only the scale mark 44a positioned at the upper right corner is set to be larger in a rectangular shape than the other scale marks 44, and the orientation of the scale mark 44 can be determined.

  In the third embodiment, for example, as shown in FIGS. 17 (2) and 17 (3), a rectangular pattern is added to the left end of the E-shaped pattern 51 located at the upper left.

  In the third embodiment, as shown in FIG. 17 (4), the scale mark 53 located at the upper right corner is formed to be larger.

  Furthermore, in the fourth embodiment, as shown in FIG. 17 (5), among the scale marks 44 arranged in a matrix, the scale mark 44b located at the upper right corner is formed to be larger. ing.

  In the third embodiment, as shown in FIG. 17 (6), the scale mark is not arranged in a rectangular shape so as to surround the region where the shot address mark 43 is formed, but divided exposure of the semiconductor wafer 1 is performed. The scale mark 44 is arranged in a polygonal shape close to the shape of the position, and the notch 60 is provided in the upper right scale mark 44.

  Further, in the third embodiment, as shown in FIG. 17 (7), a notch 60 is provided in the upper right scale mark 55.

  In the third embodiment, when the trouble occurs in the market and the semiconductor chip is returned, only a small part of the chip including the shot address pattern 41 remains, for example, the characteristic part having the directionality to the scale mark Since the orientation of the shot address pattern 41 can be determined, an error in determining the shot address can be prevented.

  Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

Embodiment 4
FIG. 18 shows a fourth embodiment of the present invention. In the fourth embodiment, the shape of the shot address mark is different from that of the previous embodiment.

  That is, in the fourth embodiment, as shown in FIG. 18A, the shot address mark 43 is formed in a rectangular shape instead of a square shape. Even when they overlap, the position of the shot address mark 43 can be identified.

  In the example shown in FIGS. 18 (3) to 18 (5), the shape of the shot address mark 43 is not a square shape, but a cross shape, a convex shape, and a circular shape. Easy going.

  Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

  In the above-described embodiment, when the n-type layer 6 as the fourth layer of the semiconductor wafer 1 is etched in the manufacturing process of the self-scanning light-emitting element array chip, for example, in (2) the substrate etching process or the like. Further, the case where the shot address pattern 41 and the chip address pattern 42 are formed has been described. However, the present invention is not limited to this, and etching of other layers of the semiconductor wafer 1 and the anode electrode formed on the semiconductor wafer 1 are not limited thereto. Of course, it may be formed by a metal layer such as aluminum forming a gate electrode or the like, or an insulating film or a protective film.

  Of course, the present invention is not limited to semiconductor chips such as self-scanning light emitting element array chips, but can be widely applied to other semiconductors in general.

10: Semiconductor chip, 41: Shot address pattern, 42: Chip address pattern

Claims (5)

In exposing the surface of the semiconductor wafer by dividing the exposure position differently at a plurality of times, at least one exposure position identifying unit for identifying the exposure position of each of the divided exposures on the surface of the semiconductor wafer;
When simultaneously exposing a region corresponding to a plurality of semiconductor chips in the one-time division exposure, at least one semiconductor chip position identification unit for identifying the position of each semiconductor chip in the one-time division exposure is provided. A semiconductor chip characterized by that. The semiconductor chip according to claim 1,
The semiconductor chip according to claim 1, wherein the exposure position identification unit includes an exposure position identification mark for identifying an exposure position of each of the divided exposures and an auxiliary mark for assisting position identification of the exposure position identification mark. In the semiconductor chip according to claim 1 or 2,
The exposure position identification unit and the semiconductor chip position identification unit are formed using a manufacturing process of a semiconductor device. The semiconductor chip according to claim 2,
The semiconductor chip according to claim 1, wherein the exposure position identification unit moves the position of the exposure position identification mark in accordance with an operation of moving the position of each of the divided exposures. An exposure position for forming at least one exposure position identification unit for identifying the exposure position of each of the divided exposures on the surface of the semiconductor wafer when exposing the surface of the semiconductor wafer by dividing the exposure position into a plurality of times at different exposure positions. An identification part forming step;
When simultaneously exposing a region corresponding to a plurality of semiconductor chips in the single divided exposure, at least one semiconductor chip position identifying unit for identifying the position of each semiconductor chip in the single divided exposure is formed. A semiconductor chip manufacturing method comprising: a semiconductor chip position identification portion forming step.

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