JP2007042882A - Semiconductor device, its manufacturing method and method for recognizing individual management information of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of directly imparting the individual management information of chips during a manufacturing process to all chips without an additional mask and an additional process, without an increase in a chip size, and without a damage by laser beams; and capable of ensuring a traceability only in a normal wafer manufacturing process. <P>SOLUTION: The semiconductor device has a semiconductor integrated circuit 17 with a formed integrated circuit on a rectangular substrate and a scriber 18 as the cut-leaving region of a dicing positioned around the semiconductor integrated circuit. In the semiconductor device, an information display unit 19 having a plurality of pattern-formed layers and displaying the individual management information in the manufacturing process by combining the patterns of each layer is formed to the scriber. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device to which individual management information is added during a manufacturing process.

  FIG. 6 is a plan view showing an example of a configuration of a conventional semiconductor device (semiconductor chip, hereinafter simply referred to as a chip) in a chip state separated by a dicing process. The chip shown in FIG. 6 includes a semiconductor integrated circuit 17 and a remaining area 18 after dicing (hereinafter referred to as a scribe section). Further, a product type name display section 20 for displaying the product type name of the corresponding chip is provided in the region of the semiconductor integrated circuit 17. In the product type name display section 20, a product type name, a mask name, a manufacturer name, etc. (hereinafter referred to as a product type name, etc.) are written, for example, MNxxxxxxx. Product type names and the like are formed by pattern formation on an exposure mask, and these names are transferred and written on a chip.

  In this way, the product type names and the like written on the conventional chip are all the same name for each product type, so when creating a mask for the chip, if the pattern is formed in the empty space of the chip, The same name can be easily assigned to the chip using the mask.

  Conventionally, a product type name given on a chip is merely a name such as a company name, a product type name, and a mask name. For example, a manufacturing process such as a chip lot number, a wafer number, a position coordinate in a wafer, etc. There has been little effort to give individual chip management information to chips. Even if the individual management information is given to the chip, the individual management information is about the assembly lot number.

  Therefore, in the case of chip packages and individual chips incorporated in them, the assembly lot number is used as a clue even if it is attempted to investigate the cause of a failure that occurred after the assembly process, such as a failure at a shipping test or use site. The fact is that there is no way to search process management information and test information.

  However, in general, in the chip manufacturing process, the lot structure in the wafer process is different from the lot structure in the assembly process after wafer dicing (the process of separating the wafer into chips). For example, one lot in the assembly process is the number in the wafer process. It is often composed of lots.

  When a lot number is given to a chip as process management information obtained in the chip manufacturing process, the manufacturing lot can be identified mainly in pursuit of the cause of a lot defect that temporarily occurred in a certain process at the manufacturing site, It is valid. However, if the process management information is only the lot number, the unambiguous correspondence between the lot management data and the failed chip in the wafer process is lost for the shipping test after the assembly process and the occurrence of a failure at the use site. For this reason, there is no method for retrieving process management information and test information using the assembly lot number as a clue, the cause of the failure cannot be sufficiently pursued, and so-called traceability is lacking.

  Further, in the form of chip selling in which the assembly process is performed by the customer, since the process management method is different for each customer, there is a problem that even if a defect occurs, it is substantially impossible to track.

  In recent years, the complexity of various manufacturing processes accompanying the miniaturization of semiconductor integrated circuits and the high accuracy of process condition setting have led to a large difference in characteristics of semiconductor integrated circuits from wafer to chip, even within the same manufacturing lot. ing. Therefore, when a faulty chip occurs, the fault countermeasures differ greatly depending on whether the faulty chip originally exists in the peripheral part of the wafer that tends to cause a process failure or in the central part of the wafer that should be a good product.

  In other words, in addition to the company name, product type name, etc. given to the chip, the management information to the extent that the assembly lot number is printed on the package is extremely important from the standpoint of finding the cause of defects at the manufacturing site and the occurrence of failures at the site of use. It is insufficient. Therefore, for example, even when there is a complete correspondence between the lot configuration in the wafer process and the lot configuration in the assembly process, as the chip individual identification information, for example, if the position coordinates of the chip in the wafer is unknown, It is difficult to make good countermeasures against failures.

In order to solve this problem, for example, in Patent Document 1, in an exposure process for manufacturing a chip, individual management information such as a lot number, a wafer number, and a position coordinate in a wafer is provided on an exposure apparatus on the front or back surface of each chip. A method of writing by forming a pattern using is described. Also described is a method of attaching a laser to a die sort tester and writing individual management information on the front or back surface of each chip using a laser beam.
JP 2000-228341 A

  However, the conventional chip has an advantage in that individual management information can be written on a chip basis, but a special reticle is required when writing individual management information in an exposure apparatus. Further, since a data area for writing in the chip is necessary, there is a problem that the chip size is increased as compared with the conventional technique.

  Further, when a laser beam is used, since data is written in a spot shape, an additional step of irradiating the laser beam is necessary in the wafer manufacturing process. Further, there is a concern that the laser beam may be damaged to some extent when the laser beam is applied. In addition, a region for applying a laser beam is required in the chip, and there is a problem that the chip size is increased as compared with the prior art.

  In view of the above problems, the present invention provides individual management information of chips during the manufacturing process without additional masks and additional processes, without increasing the chip size, and without damage by the laser beam. An object of the present invention is to provide a semiconductor device which can be directly applied to all chips and can ensure traceability.

  A semiconductor device according to the present invention includes a semiconductor integrated circuit portion in which an integrated circuit is formed on a rectangular substrate, and a scribe portion that is a dicing uncut region located around the semiconductor integrated circuit portion. The apparatus includes an information display unit that is provided in the scribe unit and displays individual management information in a manufacturing process by combining a plurality of layer patterns.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the above-described method of manufacturing a semiconductor device, wherein the layer of the information display unit is formed and patterned by the same process as the layer forming the semiconductor integrated circuit. Are stacked to form the information display section.

  An individual management information recognition method for a semiconductor device according to a first aspect of the present invention is the individual management information recognition method for the semiconductor device, wherein the individual management information for each layer is identified from the cross-sectional shape of the information display unit, The individual management information of the semiconductor device is recognized by combining the individual management information of each layer.

  An individual management information recognition method for a semiconductor device according to a second aspect of the present invention is the individual management information recognition method for the semiconductor device, wherein the individual management information of each layer is identified from the surface shape of the information display unit, The individual management information of the semiconductor device is recognized by combining the individual management information of each layer.

  According to the present invention, traceability of a semiconductor device can be ensured without adding equipment and processes. As a result, when a product defect occurs after shipment from the customer, it is possible to reduce the labor of the follow-up survey for the manufacturing process of the semiconductor device and to speed up the feedback to the manufacturing process.

  In addition, the individual management information at the time of manufacturing the semiconductor device uses the scribe part instead of the inside of the chip, and the size of the semiconductor device is not changed. Accordingly, there is no increase in cost due to the addition of individual management information.

  In addition, there is no fear of damage because there is no additional laser beam process.

  In the semiconductor device of the present invention, the information display unit may be configured to display the individual management information by a cross-sectional shape formed by a pattern of each stacked layer.

  Moreover, the pattern of each said layer can also be set as the structure currently formed so that identification is possible based on a physical shape. Individual management information can be easily identified.

  Each of the layers may be configured such that a pattern can be visually identified. Individual management information can be read visually in this configuration.

  In addition, each of the layers may have a configuration in which the constituent material is different from that of the adjacent layer. Layer identification becomes easy.

  In addition, the layers constituting the information display unit may be stacked so that the information description area where the pattern is formed does not overlap with the information description areas of other layers. With this configuration, the individual management information can be read from the surface shape of the information display unit.

  The substrate may have a shot end on at least one side, and the scribe portion may have the information display portion in a region in contact with the shot end.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention. FIG. 1A is a plan view showing the positional relationship of the shot 16 with respect to the silicon wafer 14. On the silicon wafer 14, shots 16 having semiconductor integrated circuits formed by a lithography process are regularly formed vertically and horizontally. Here, the position of the shot 16 in the silicon wafer 14 is defined as shown in FIG. That is, the first coordinate axis and the second coordinate axis are determined within the wafer surface with reference to the direction of the notch 15, and the position of the shot 16 (in-wafer position coordinates) is determined as shown in FIG.

  FIG. 1B is an enlarged plan view of one shot 16 of FIG. 1A. In this embodiment, a 10-chip configuration is taken as an example. The shot 16 is cut along a dicing line 18a between chips shown in FIG. 1B in a later process and separated into individual chips.

  Next, an enlarged plan view of individually separated semiconductor devices (semiconductor chips, hereinafter simply referred to as chips) is shown in FIG. As shown in FIG. 1C, the chip diced from the wafer state includes a semiconductor integrated circuit 17 including a product type name display unit 20 and an individual data unit 19 (information display unit) of the chip on the substrate. The uncut region 18 after dicing (hereinafter referred to as a scribe portion) is formed.

  The chip according to the present embodiment uses the scribe unit 18 positively and leaves individual chip management information in units of 16 shots.

  In the manufacturing process (lithography process) of the semiconductor integrated circuit 17, if the blind function is used for the end region of the shot 16, the setting of the exposure range can be changed for each shot 16. Therefore, by changing the exposure range for each shot 16 at a location corresponding to the individual data portion 19 of the reticle, different individual management information can be given to the individual data portion 19 for each shot 16. Although the number of pieces of individual management information is limited only by the accuracy of blinds in one layer, the amount of information increases by combining multiple layers, and expresses individual management information during the manufacturing process, such as lot number, wafer number, position coordinates in wafer, etc. It becomes possible to do.

  In other words, for a chip including at least one shot 16 end on one side of the scribe portion 18, it is possible to form the individual data portion 19 of the chip in units of shot 16 using a reticle.

  Hereinafter, the individual data portion of the chip will be described with reference to FIG. 2A is a plan view showing a reticle for writing individual management information in the individual data section 19a shown in FIG. 2B, and FIG. 2B is a plan view showing the individual data section 19a of the chip. ) Is a cross-sectional view showing an XX cross section of the individual data portion 19a of (b).

  First, the individual management information during the manufacturing process will be described with specific examples. Here, a lot number, a wafer number, and a position coordinate within the wafer are used as the individual management information. As the individual management information, the specific number of data necessary for tracking the state of the chip in the manufacturing process is as follows.

  For the lot number, it is necessary to designate all the lot numbers from the start of production to the end of production, and about 1000 to 3000 are necessary. The wafer number is information indicating the order of the wafers within one lot, and it is generally sufficient that a maximum of 25 can be designated when assuming a cassette unit. The in-wafer position coordinate is information indicating the position where the shot 16 is arranged in the wafer surface. When a defect occurs, the position of each chip cannot be traced. However, if the defect can be traced to a shot, the cause of the defect can be sufficiently narrowed down. When an 8-inch wafer is manufactured using a 6-inch reticle, the number of shots is about 70 to 100 including the invalid shot including the edge of the wafer, and it is sufficient that this can be specified.

  Next, the individual data portion 19a of the chip will be specifically described. The size of the chip body is 2 mm in the horizontal direction and 1 mm in the vertical direction. The interval between the semiconductor integrated circuits 17 is about 40 μm. Among them, the uncut region (scribe part) 18 after dicing is a region of about 25 μm from the semiconductor integrated circuit 17.

  A layer pattern 21a is arranged on the reticle in order to form the individual data portion 19a of the chip having a width of 20 μm using the scribe portion 18. A specific layer pattern is shown in FIG.

  Since the minimum accuracy of the stepper blind function is 5 μm and the individual data portion 19a has a width of 20 μm, five patterns can be set in each layer. In the present embodiment, as shown in FIG. 2A, five types of blind position setting 23 of 0, 1, 2, 3, 4 are performed.

  FIG. 2C is a cross-sectional view showing an X cross section of the individual data portion 19a in FIG. The individual data portion 19a of the chip is formed on the substrate 11 in order from the lower layer, the field oxide film 1a, the gate electrode 2a, the first interlayer insulating film 3a, the first wiring layer 4a, the second interlayer insulating film 5a, and the second wiring. Ten layers of a layer 6a, a third interlayer insulating film 7a, a third wiring layer 8a, a first protective film 9a, and a second protective film 10a are laminated. In the lowest layer, the active layer 12a in which the field oxide film 1a is not formed forms the individual management information of this layer. Further, contact holes 13a-1, 13a-2, 13a-3 are formed in the first interlayer insulating film 3a, the second interlayer insulating film 5a, and the third interlayer insulating film 7a to form individual management information for the layers. ing. Each layer is formed up to the set blind position, and forms individual management information for the layer.

  The blind position has five settings from 0 to 4, and there are 10 layers. Therefore, information of a maximum of 5 to the 10th power can be set as the individual management information. Therefore, if the first 5 layers are used for expressing the lot name, the next 2 layers are used for the wafer number, and the remaining 3 layers are used for expressing the position coordinates in the wafer, the maximum number of lots is 3125, the wafer number is maximum 25, Up to 125 can be specified. This amount of information is sufficient for individual management information as described above.

  Next, a method for decoding the individual data portion 19a of the chip will be described with reference to FIG. First, the cross section of the individual data portion 19a of the chip is analyzed, and it is read how many μm each layer is formed in the individual data portion 19a of the chip from the semiconductor integrated circuit 17 side. In FIG. 2C, the active region 12a formed in the layer of the field oxide film 1a is 20 μm, the gate electrode 2a is 10 μm, the contact hole 13a-1 in the first interlayer insulating film 3a is 0 μm, and the first wiring layer 4a is The contact hole 13a-2 in the second interlayer insulating film 5a is formed to a region of 15 μm. Similarly, the second wiring layer 6a is 15 μm, the contact hole 13a-3 in the third interlayer insulating film 7a is 10 μm, the third wiring layer 8a is 10 μm, the opening of the first protective film 9a is 5 μm, and the second protective film 10a The opening is formed to 0 μm.

  Next, a blind position setting value when each layer is formed is obtained from the read length of each layer. That is, since the accuracy of the blind is 5 μm, a value obtained by dividing the length of each layer by 5 μm is obtained. The obtained blind position setting values are 4 for the formation layer of the field oxide film 1a, 2 for the formation layer of the gate electrode 2a, 0 for the formation layer of the first interlayer insulating film 3a, 4 for the formation layer of the first wiring layer 4a, 3 for the formation layer of the second interlayer insulating film 5a, 3 for the formation layer of the second wiring layer 6a, 2 for the formation layer of the third interlayer insulating film 7a, 2 for the formation layer of the third wiring layer 8a, and the first protective film It is 1 in the formation layer of 9a and 0 in the formation layer of the second protective film 10a.

  Next, a value 42043332210 in which the obtained values are arranged in order from the lowest layer is divided into a lot number, a wafer number, and a shot number. In this embodiment, the lot number is expressed by the first five layers, that is, the field oxide film 1a, the gate electrode 2a, the first interlayer insulating film 3a, the first wiring layer 4a, and the second interlayer insulating film 5a. Become. When this is converted from a decimal number to a decimal number, the lot number can be read as 2773.

  Next, the wafer number is 32 because it is expressed by the next two layers, that is, the second wiring layer 6a and the third interlayer insulating film 7a. Similarly, the wafer number can be read as 17 when converted from a decimal number to a decimal number. In-wafer position coordinates are 210 because they are expressed by the remaining three layers, that is, the third wiring layer 8a, the first protective film 9a, and the second protective film 10a. Similarly, the in-wafer position coordinate can be read as 55 when converted from a decimal number to a decimal number.

  In this embodiment, there are 25 wafer numbers from 1 to 25, but strictly speaking, it can be expressed only from 0 to 24 in quinary numbers. However, there is no actual wafer number 0, and the quinary number 00 is a missing number. Therefore, using this, the wafer number 25 is expressed as 00. This is because it takes less time to create and analyze the sample than to increase the number of digits, that is, the number of layers in order to express only 25.

  Next, a manufacturing method of the individual data section 19 of the chip configured as described above will be described.

  In the lithography process of the semiconductor integrated circuit 17, a pattern is formed using the reticle shown in FIG. For example, in a certain shot, using the blind function of the stepper device, exposure is performed by selecting up to an area where the blind position setting value is 4 for the individual data portion 19a of the chip. In another shot, the pattern is formed by selecting up to an area where the blind position setting value is 3, particularly for the layer forming the position coordinates in the wafer, while changing the formation pattern for each shot individually. A data portion 19 is formed.

  A case where attention is paid to the same shot will be described. As described above, the blind position setting value is 4 in the formation layer of the field oxide film 1a, 2 in the formation layer of the gate electrode 2a, 0 in the formation layer of the first interlayer insulating film 3a, and in the formation layer of the first wiring layer 4a. 4, 3 in the formation layer of the second interlayer insulating film 5a, 3 in the second wiring layer 6a layer, 2 in the third interlayer insulating film 7a layer, 2 in the third wiring layer 8a layer, and a formation layer of the first protective film 9a Then, 1 is selected up to 0 region in the formation layer of the second protective film 10a, exposure is performed to form a pattern, and the individual data portion 19a is formed. As described above, the individual management information of the chip can be written in the individual data unit 19a in units of shots by combining different layers and patterns.

  As described above, according to the first embodiment of the present invention, the individual data portion can be formed on the chip without adding equipment and processes, and the traceability of the semiconductor device can be ensured.

  Furthermore, the XX cross section shown in FIG. 2C has the same shape at any position. Therefore, even if the chip after the dicing process is damaged, the individual management information can be read as long as a part of the individual data portion 19a of the chip where the blind position settings 0 to 4 remain. . Even if the area related to the setting 4 of the blind position setting 23 of the individual data portion 19a is missing, the individual management information of the chip can be obtained although the information is limited.

  In addition, the method for manufacturing the individual data portion does not require a special reticle, so that a semiconductor device can be realized at low cost.

  Note that the layer on which the individual management information is placed can be used in the same manner in a layer formed by injection or the like. However, from the viewpoint of facilitating tracking, the shape of the field oxide film, active region, gate electrode, interlayer insulating film, contact hole, wiring layer, protective film, etc. in this embodiment remains physically, and can be It is desirable that the appearance is easy to check.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIG. 3A is a reticle for forming a chip according to the present embodiment, FIG. 3B is a plan view of the chip, and FIG. 3C is an X sectional view of FIG.

  The individual data portion 19b of the chip according to the present embodiment shown in FIG. 3B uses the layer pattern 22b formed in the reticle pattern area 21b shown in FIG. 3A to continuously form layers. Instead, it is a divided configuration. Therefore, the active layer 12b, the gate electrode 2b, the first wiring layer 4b, the second wiring layer 6b, the third wiring layer 8b, the first protective film 9b, and the second protective film 10b in which the field oxide film 1b is not formed are also divided. Is formed. About another structure, it is the same as that of Embodiment 1, and abbreviate | omits description. In the dividing method, since the accuracy of the blind function is 5 μm, as shown in FIG. 3A, a pattern is formed using a reticle in which four 4 μm windows are arranged in the layer pattern 22b.

  With this configuration, since the layer pattern 22b is divided in accordance with the accuracy of the blind function, the size and the accuracy of the blind function are determined by reading the number of each layer as shown in FIG. Even when the relationship is unknown, the layer information can be easily read.

(Embodiment 3)
A third embodiment of the present invention will be described with reference to FIG. FIG. 4A is a plan view showing a reticle of each layer for forming a chip according to the present embodiment, and FIG. 4B is a plan view of the chip.

  The chip according to the present embodiment is characterized in that the individual data part 19c on which the individual management information is placed is formed so that the information description areas for each layer do not overlap as shown in FIG. 4B.

  As shown in FIG. 4A, the individual data portion 19c uses a reticle in which layer patterns 22c-1 to 22c-10 are formed in pattern areas 21c-1 to 21c-10, and uses a blind function of a stepper device. Formed using.

  With the configuration as described above, the chip according to the present embodiment can read the individual management information only by counting the number of external patterns without looking at the cross-sectional shape of the individual data portion 19c.

(Embodiment 4)
Embodiment 4 of the present invention will be described with reference to FIG. FIG. 5A is a plan view showing a reticle for each layer for forming a chip according to the present embodiment, and FIGS. 5B and 5C are plan views of the chip.

  The chip according to the present embodiment is characterized in that characters are arranged in each layer of the individual data portion 19d as shown in FIG.

  As shown in FIG. 5A, the individual data portion 19d uses a reticle in which layer patterns 22d-1 to 22d-10 are formed in pattern areas 21d-1 to 21d-10, and uses a blind function of a stepper device. Formed using.

  With the configuration as described above, the chip according to the present embodiment can read information only by looking at the appearance without looking at the cross-sectional shape of the individual data portion 19d. Furthermore, since it is easy to distinguish each layer in the case of a character, when the chip size and the arrangement area of the individual data portion of the chip are small in the vertical direction, the character is placed at one blind position as shown in FIG. A plurality of individual data sections 19e may be provided.

  In this embodiment, the alphabet is used as an example. However, the present invention is not limited to the alphabet, and may be a number. It is obvious that the same effect can be obtained if the divided patterns have different shapes.

  The present invention forms individual management information in the scribe section of the semiconductor device, and thus has the advantage of improving the traceability of the semiconductor device without increasing the size of the semiconductor device, and can be used in the semiconductor device manufacturing industry. .

(A) A diagram showing a relationship between a silicon wafer and a shot position for forming a chip of the present invention, (b) a diagram showing a relationship between a shot and a chip, and (c) a plan view showing a configuration of the chip. (A) The figure which shows the reticle for forming the chip | tip in Embodiment 1 of this invention, (b) The top view of the separate data part of a chip | tip, (c) Sectional drawing of the individual data part of a chip | tip (A) The figure which shows the reticle for forming the chip | tip in Embodiment 2 of this invention, (b) The top view of the separate data part of a chip | tip, (c) Sectional drawing of the individual data part of a chip | tip (A) The figure which shows the reticle for forming the chip | tip in Embodiment 3 of this invention, (b) The top view of the separate data part of a chip | tip. (A) The figure which shows the reticle for forming the chip | tip in Embodiment 2 of this invention, (b) (c) The top view of the separate data part of a chip | tip Plan view showing the configuration of a conventional chip

Explanation of symbols

1a, 1b Field oxide film 2a, 2b Gate electrode 3a, 3b First interlayer insulating film 4a, 4b First wiring layer 5a, 5b Second interlayer insulating film 6a, 6b Second wiring layer 7a, 7b Third interlayer insulating film 8a , 8b Third wiring layer 9a, 9b First protective film 10a, 10b Second protective film 11 Substrate 12a, 12b Active region 13a-1 to 13a-3, 13b-1 to 13b-3 Contact hole 14 Silicon wafer 15 Notch 16 Shot 17 Semiconductor integrated circuit 18 Scribe unit 18a Dicing line 19a, 19b, 19c, 19d, 19e Individual data unit 20 Product name display unit 21a, 21b, 21c-1 to 21c-10, 21d-1 to 21d-10 Pattern Region 22b, 22c-1 to 22c-10, 22d-1 to 22d-10 Layer pattern 23 Rind position setting

Claims (10)

In a semiconductor device comprising: a semiconductor integrated circuit portion in which an integrated circuit is formed on a rectangular substrate; and a scribe portion that is a dicing uncut region located around the semiconductor integrated circuit portion.
A semiconductor device, comprising: an information display unit that is provided in the scribe unit and displays individual management information in a manufacturing process by a combination of patterns of a plurality of layers.   The semiconductor device according to claim 1, wherein the information display unit displays the individual management information by a cross-sectional shape formed by a pattern of each stacked layer.   3. The semiconductor device according to claim 1, wherein the pattern of each layer is formed so as to be identifiable based on a physical shape.   The semiconductor device according to claim 3, wherein a pattern of each of the layers is visually identifiable.   5. The semiconductor device according to claim 3, wherein each layer has a constituent material different from that of an adjacent layer.   2. The semiconductor device according to claim 1, wherein the layers constituting the information display unit are stacked such that an information description area in which a pattern is formed does not overlap an information description area of another layer. The substrate has a shot edge on at least one side;
The semiconductor device according to claim 1, wherein the scribe unit includes the information display unit in a region in contact with the shot end. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 7,
A method of manufacturing a semiconductor device, wherein the information display unit is formed by forming and patterning a layer of the information display unit in the same process as the layer forming the semiconductor integrated circuit, and forming the layer by stacking layers. An individual management information recognition method for a semiconductor device according to any one of claims 1 to 5,
Identify the individual management information of each layer from the cross-sectional shape of the information display unit,
An individual management information recognition method for a semiconductor device that recognizes individual management information for the semiconductor device by combining individual management information for each layer. An individual management information recognition method for a semiconductor device according to claim 6 or 7,
Identify the individual management information of each layer from the surface shape of the information display unit,
A semiconductor device individual management information recognition method for recognizing the individual management information of the semiconductor device by combining the individual management information of each layer.

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