JP2007335459A - Semiconductor wafer, semiconductor device, and process for fabricating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer in which a plurality of alignment marks or inspection marks can be arranged more densely than before, and to provide a semiconductor device and its fabrication process. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for setting a plurality of area definition frames (virtual frame) 13 having four corners cut obliquely to one side of a chip C, in the free area E or the scribe area S of the chip C on a silicon (semiconductor) substrate 10; and a step for forming a plurality of alignment marks 12 being confined in the area definition frame 13 on the silicon substrate 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer, a semiconductor device, and a method for manufacturing a semiconductor device.

  In a manufacturing process of a semiconductor device such as an LSI, an exposure process is performed many times, whereby a semiconductor device having a multilayer device pattern is manufactured.

  In the exposure process, an alignment mark for aligning the exposure device such as a stepper and the semiconductor substrate, and an inspection mark for inspecting a positional deviation between the resist pattern obtained by the exposure and the semiconductor substrate are provided on the semiconductor substrate. It is necessary to form.

  FIG. 1 is a plan view of an inspection mark 2 according to a conventional example formed on a semiconductor substrate 1.

  When the inspection mark 2 is close to another pattern (for example, a device pattern), there arises a disadvantage that the circuit does not operate normally. Therefore, usually, an area definition frame 3 for isolating the inspection mark 2 from the surrounding pattern is provided at the design stage, and the inspection mark 2 is arranged inside the area definition frame 3. That is, the area inside the area definition frame 3 functions as a buffer area between the inspection mark and other patterns.

  As shown in FIG. 1, the region definition frame 3 according to the conventional example is a square whose side is L in length.

  On the other hand, FIG. 2 is a plan view of an alignment mark 6 according to a conventional example.

  As shown in FIG. 2, the area definition frame 7 is also given to the alignment mark 6 for the same reason as described above. In this example, the region definition frame 7 is a rectangle having a long side length L and a short side length 0.5L.

  Here, it is rare that only one inspection mark 2 or alignment mark 6 is formed on the semiconductor substrate 1, and the inspection mark is usually used for the purpose of measuring the rotation (rotation) or expansion of the semiconductor wafer. 2 and a plurality of alignment marks 6 are formed continuously.

  In this case, the extending direction of a plurality of formed marks includes a Y direction, an X direction, and an oblique direction.

  For example, in the example of FIG. 3, the two inspection marks 2 are continuously formed so as to extend in the Y direction.

  In the example of FIG. 4, four alignment marks 6 are continuously formed so as to extend in the X direction.

  By the way, these marks 2 and 6 are formed in an empty area of a chip formed on the semiconductor substrate 1 and a scribe area between the chips in order to prevent interference with a device pattern or the like. Since the empty area and the scribe area tend to decrease due to the recent high integration and complexity of semiconductor devices, it is necessary to densely place the marks 2 and 6 in these narrow areas.

  However, if the area definition frames 3 and 7 of the marks 2 and 6 are rectangular as described above, it is difficult to densely place the marks 2 and 6 in a narrow area.

  5 and 6 are plan views for explaining this problem.

  FIG. 5A is a plan view in the case where three alignment marks 6 according to the conventional example are arranged obliquely. In this case, since the arrangement pitch (arrangement period) of the alignment marks 6 in the Y direction is limited to 0.5 L, which is the length of the region definition frame 7 in the Y direction, the total length of the three alignment marks 6 in the Y direction. Cannot be shorter than 1.5 L (= 3 × 0.5 L).

  Similar inconveniences occur in the arrangement of FIG. In the example shown in the figure, the three alignment marks 6 are linearly arranged in the Y direction. Even in this case, the total length of the three alignment marks 6 in the Y direction is limited to 1.5L.

  Further, when the three alignment marks 6 are arranged obliquely as shown in FIG. 6A, the total length of these alignment marks 6 in the X direction cannot be shorter than 3L (= 3 × L).

  Similarly, even when three alignment marks 6 are linearly arranged in the X direction as shown in FIG. 6B, the total length of the three alignment marks 6 in the X direction is limited to 3L.

  As described above, in the conventional example in which the region defining frame 7 is rectangular, when the alignment marks 6 are to be arranged continuously, the total length of the plurality of alignment marks 6 is limited. Cannot be densely arranged, and it becomes difficult to cope with the recent high integration and complexity of semiconductor devices.

  In the above, the problem of the alignment mark 6 has been described, but the same problem also occurs in the inspection mark 2.

Moreover, the technique relevant to this invention is disclosed by the following patent documents 1-4.
JP 2005-277337 A JP 2004-134473 A JP-A-2-229419 Japanese Patent Laid-Open No. 62-112325

  An object of the present invention is to provide a conductor wafer, a semiconductor device, and a semiconductor device manufacturing method capable of arranging a plurality of alignment marks or inspection marks more densely than in the past.

  According to an aspect of the present invention, there is provided a semiconductor wafer having a semiconductor substrate on which a plurality of chips are formed and a plurality of marks formed in a vacant area in the chips or a scribe area of the semiconductor substrate in a staggered manner. Is done.

  According to another aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate and a plurality of marks formed in a staggered pattern in the empty area of the semiconductor substrate.

  According to still another aspect of the present invention, a plurality of virtual frames in which four corners are cut obliquely with respect to one side of the chip are formed in an empty area in the chip of the semiconductor substrate, or in a scribe area of the semiconductor substrate. There is provided a method for manufacturing a semiconductor device, comprising a step of setting, and a step of forming a plurality of marks within the virtual frame on the semiconductor substrate.

  Next, the operation of the present invention will be described.

  In the present invention, since the four corners of the virtual frame in which the mark is arranged are cut, it becomes possible to form a plurality of marks in a staggered manner while preventing the marks from overlapping each other, and the arrangement density of the marks is higher than before. Therefore, it is possible to cope with high integration and complexity of semiconductor devices that have been demanded in recent years.

  According to the present invention, since the four corners of the virtual frame in which the mark is arranged are cut, the mark can be arranged at a higher density than before, which contributes to higher integration and complexity of the semiconductor device. it can.

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(1) First Embodiment In this embodiment, an inspection mark for inspecting a positional deviation between a resist pattern obtained in an exposure process and a semiconductor substrate will be described.

  FIG. 7 is an enlarged plan view of a silicon (semiconductor) wafer W according to the present embodiment.

  The silicon wafer W defines a plurality of chips C on the semiconductor substrate 1, and each chip C has a vacant area E where a device pattern such as wiring is not formed. Further, a scribe region S is formed between the chips C.

  In each of the regions E and S, alignment marks as in the following first to fourth examples are arranged.

First Example FIG. 8A is a plan view of an inspection mark according to the first example, and FIG. 8B is a cross-sectional view taken along the line I-I in FIG. 8A.

  As shown in FIG. 8A, a plurality of inspection marks 12 are formed in the scribe area S together with other dummy patterns 14.

  In this embodiment, an area definition frame (virtual frame) 13 having four corners cut obliquely with respect to one side of the chip C is set on the semiconductor substrate 10, and the alignment mark 12 is placed within the area definition frame 13. Form. By adopting the region definition frame 13 with the four corners cut off in this way, a plurality of continuous inspection marks 12 can be arranged in a staggered manner while preventing the marks 12 from overlapping each other. Can be dense.

  The cross-sectional structure of the alignment mark 12 is not particularly limited. However, in this embodiment, as shown in FIG. 8B, a silicon oxide film 11 on the silicon substrate 10 is formed, and a conductive film such as an aluminum film formed on the silicon oxide film 11 is patterned. Inspection mark 12 is formed.

  FIGS. 9A and 9B are plan views for qualitatively explaining that the arrangement of the inspection marks 12 can be made dense in this example.

  In this example, an area definition frame 13 having dimensions as shown in FIG. Such an area definition frame 13 corresponds to the area definition frame 3 according to the conventional example shown in FIG. 1 which is cut from the four corners at a distance of {(1-√2) / 2} L.

  As shown in FIG. 9B, if the four inspection marks 12 are arranged in a staggered manner by adopting this region definition frame 13, the total length in the X direction can be suppressed to {(1 + 3√2) / 2} L. it can. This is shorter than the total length (4L) when the area definition frame 3 of FIG. 1 is adopted, and it can be seen that in this example, the inspection marks 12 are actually denser than in the prior art.

  FIG. 10 is a plan view showing an inspection mark arrangement method according to a comparative example.

  In this comparative example, six inspection marks 2 in FIG. 1 according to the conventional example are arranged in a straight line in the X direction. However, in this arrangement method, since the total length of each mark 2 in the X direction is longer than that of the present example in FIG. 8A, the two marks 2 on the right side overlap the other dummy patterns 14. Therefore, in this arrangement method, only four inspection marks 2 can be arranged in the scribe region S, and the number of inspection marks is reduced as compared with the present example (see FIG. 8A) in which six inspection marks can be arranged.

Second Example FIG. 11A is a plan view of an inspection mark according to a second example, and FIG. 11B is a cross-sectional view taken along the line II-II in FIG.

  This example is different from the first example in that the inspection mark 12 is configured by a groove of a conductive film 18 such as an aluminum film, as shown in FIG. In this case, the region definition frame 13 is configured by the contour of the conductive film 18.

  Further, as shown in FIG. 11B, the conductive film 18 on which the inspection mark 12 is formed is formed simultaneously with the other dummy patterns 14.

  Thus, even when the inspection mark 12 constituted by the groove of the conductive film 18 is used, the inspection mark 12 is removed for the same reason as in the first example by cutting off the four corners of the outline of the conductive film 18 that becomes the region definition frame 13. It becomes possible to arrange closely.

Third Example FIG. 12 is a plan view (part 1) of an inspection mark according to a third example.

  This example is different from the first example only in the shape of the region definition frame 13, and the inspection mark 12 itself is the same as the first example. In this example, the inspection mark 12 is arranged in the empty area E of the chip. However, the inspection mark 12 may be arranged in the scribe area S as in the first example.

  The inspection mark 12 is formed simultaneously with the wiring 15 by patterning a conductive film such as an aluminum film.

  In this example, all four corners of the region definition frame 3 (see FIG. 1) according to the conventional example are cut out to make the region definition frame 13 a diamond shape. As a result, a plurality of inspection marks 12 can be arranged in a staggered manner so as not to overlap the wiring 15, and the inspection marks 12 can be formed densely in the empty area E having a complicated shape.

  FIGS. 13A and 13B are plan views for qualitatively explaining that the arrangement of the inspection marks 12 can be made dense in this example.

  In this example, an area definition frame 13 having dimensions as shown in FIG. Such an area definition frame 13 corresponds to a part of the area definition frame 3 according to the conventional example shown in FIG.

  As shown in FIG. 13B, by adopting this area definition frame 13 and arranging the four inspection marks 12 in a staggered manner, the total length in the X direction can be suppressed to 2.5L. This is shorter than the total length (4L) when the area definition frame 3 of FIG. 1 is adopted, and it can be seen that in this example, the inspection marks 12 are actually denser than in the prior art.

  FIG. 14 is a plan view (part 2) of the inspection mark according to the third example.

  In this example, the shapes of the area definition frame 13 and the inspection mark 12 are the same as those in the previous example of FIG. 13, but the corners of the adjacent area definition frames 13 are in contact with each other. By arranging the area definition frame 13 in this way, it is possible to form a plurality of inspection marks 12 in the vacant space E having a complicated shape between the wirings 15 so as not to overlap the wirings 15.

Fourth Example FIG. 15 is a plan view (No. 1) of an inspection mark according to a fourth example. This example is different from the third example of FIG. 12 in that the inspection mark 12 is constituted by the groove of the conductive film 18 such as an aluminum film formed simultaneously with the wiring 15, and the outline of the conductive film 18 is defined as the region definition frame 13. This is the point.

  Even if such an inspection mark 12 is employed, a plurality of marks 12 can be densely arranged as in the third example.

  FIG. 16 is a plan view (part 2) of the inspection mark according to the fourth example. In this example, the shapes of the area definition frame 13 and the inspection mark 12 are the same as those in the example of FIG. 14, but the corners of the adjacent area definition frames 13 are in contact with each other. Thereby, a plurality of inspection marks 12 can be formed so as not to overlap the wiring 15.

Next, a method of using the above-described inspection mark 12 will be described. In the following description, the inspection mark 12 according to the first example will be described as an example, but the inspection marks 12 of the second to fourth examples are used in the same manner as described below.

  FIG. 17A is a plan view for explaining how to use the inspection mark 12 according to the present embodiment, and FIG. 17B is a cross-sectional view taken along line III-III in FIG. .

  The inspection mark 12 is for inspecting a positional deviation between the resist pattern obtained by exposure and the silicon substrate 10. The resist pattern is formed above the silicon substrate 10 and has an inspection pattern 30 similar to the inspection mark 12 as shown in FIG. 17A in addition to a pattern corresponding to a device pattern such as wiring.

In testing reads the inspection mark 12 and the pattern 30 on the optically with light for inspection, to detect the offset S _y offsets S _x and Y directions of the X direction. Then, whether or not there is a positional deviation between the resist pattern and the silicon substrate 10 is determined depending on whether or not the offsets S _x and S _y are out of the values when there is no positional deviation.

  By providing a plurality of inspection marks 12 as in this embodiment, it is possible to inspect the rotation and expansion of the silicon substrate 10 in addition to the positional deviation in the X direction and the Y direction.

(2) Second Embodiment In this embodiment, an alignment mark will be described.

  FIG. 18A is a plan view of the alignment mark according to the present embodiment, and FIG. 18B is a cross-sectional view taken along the line IV-IV in FIG.

  As shown in FIG. 18A, a plurality of alignment marks 16 according to the present embodiment are formed in the scribe region S of the silicon wafer W shown in FIG.

  And this alignment mark 16 is arranged inside the area definition frame 17, but since the four corners of the area definition frame 17 are cut obliquely with respect to one side of the chip C, it is continuous as in the first embodiment. A plurality of alignment marks 16 can be arranged in a staggered manner, and the arrangement of the marks 16 becomes dense.

  The cross-sectional structure of the alignment mark 16 is not particularly limited, but in this embodiment, as shown in FIG. 18B, a silicon oxide film 11 on the silicon substrate 10 is formed and formed on the silicon oxide film 11. An alignment mark 16 is formed by patterning a conductive film such as an aluminum film.

  FIGS. 19A and 19B are plan views for qualitatively explaining that the alignment marks 16 can be densely arranged in the present embodiment.

  As the dimension of the area definition frame 17, for example, a dimension as shown in FIG. This dimension is cut out from the four vertices of the region definition frame 7 according to the conventional example shown in FIG. 2 where the distance in the X direction is ((√3) / 8) L and the distance in the Y direction is 0.125L. It corresponds to a thing.

  By adopting such dimensions, as shown in FIG. 19B, the total length in the X direction of four consecutive inspection marks 16 can be suppressed to (1 + 3 (√2) / 2) L. Compared to the conventional example (see FIG. 4) in which the total length in the direction is 4L, the arrangement of the marks 16 is dense.

  Next, a method for using such an alignment mark 16 will be described.

  FIG. 20A is a plan view for explaining how to use the alignment mark 12 according to the present embodiment, and FIG. 20B is a cross-sectional view taken along the line V-V in FIG. .

  The alignment mark 12 is used for alignment between an exposure apparatus such as a stepper and the silicon substrate 10.

  In the alignment, as shown in FIG. 20A, a photoresist 31 is applied over the silicon substrate 10, and then the silicon substrate 10 is put into an exposure apparatus (not shown). Before the exposure of the photoresist 31, the alignment mark 12 is scanned in the X direction with alignment mark detection light (alignment light), and the alignment light reflected by the surface of the alignment mark 12 is returned. The position of the edge (step) of the alignment mark 12 is confirmed by detecting the change in the reflection intensity with respect to the scanning direction.

  As the alignment light, light having a wavelength that allows the photoresist 31 to pass through the photoresist without being exposed to light is used.

  Then, the position of the wafer stage on which the silicon substrate 10 is placed is finely adjusted while confirming the position of the edge of the alignment mark 12 as described above, thereby aligning the exposure apparatus and the silicon substrate 10 in the X direction. Done.

  In order to perform alignment in the Y direction, the same operation as described above may be performed using an alignment mark having a shape obtained by inverting the alignment mark 12 in FIG.

  When a plurality of alignment marks 12 are provided as in the present embodiment, rotation and expansion of the silicon substrate 10 can be found in addition to misalignment between the exposure apparatus and the silicon substrate 10 in the X direction and Y direction.

  The features of the present invention are added below.

(Supplementary note 1) a semiconductor substrate on which a plurality of chips are formed;
A plurality of staggered marks formed in empty areas in the chip or scribe areas of the semiconductor substrate;
A semiconductor wafer comprising:

  (Additional remark 2) The said mark consists of a film | membrane formed on the said semiconductor substrate, The semiconductor wafer of Additional remark 1 characterized by the above-mentioned.

  (Supplementary note 3) The semiconductor wafer according to supplementary note 1, wherein the mark is formed by forming a groove in a film formed on the semiconductor substrate.

  (Additional remark 4) The said mark aligns the inspection mark used when test | inspecting the position shift with the resist pattern formed above the said semiconductor substrate, and the said semiconductor substrate, or an exposure apparatus and the said semiconductor device. 2. The semiconductor wafer according to appendix 1, which is an alignment mark sometimes used.

(Appendix 5) a semiconductor substrate;
A plurality of staggered marks formed in empty areas of the semiconductor substrate;
A semiconductor device comprising:

  (Additional remark 6) The said mark consists of a film | membrane formed on the said semiconductor substrate, The semiconductor device of Additional remark 5 characterized by the above-mentioned.

  (Supplementary note 7) The semiconductor device according to supplementary note 5, wherein the mark is formed by forming a groove in a film formed on the semiconductor substrate.

  (Additional remark 8) The said mark aligns the inspection mark used when test | inspecting the position shift with the resist pattern formed above the said semiconductor substrate, and the said semiconductor substrate, or an exposure apparatus and the said semiconductor device. The semiconductor device according to appendix 5, which is an alignment mark used sometimes.

(Supplementary Note 9) A step of setting a plurality of virtual frames in which four corners are obliquely cut with respect to one side of the chip in an empty area in the chip of the semiconductor substrate or a scribe area of the semiconductor substrate;
Forming a plurality of marks on the semiconductor substrate within the virtual frame;
A method for manufacturing a semiconductor device, comprising:

  (Additional remark 10) The manufacturing method of the semiconductor device of Additional remark 9 characterized by setting the said some virtual frame in zigzag form.

(Appendix 11) A step of forming a resist pattern above the semiconductor substrate;
The method for manufacturing a semiconductor device according to appendix 9, further comprising a step of inspecting whether the semiconductor substrate and the resist pattern are aligned while using the mark as an inspection mark.

  (Additional remark 12) The manufacturing method of the semiconductor device of Additional remark 9 characterized by having the process of aligning the said semiconductor substrate and exposure apparatus, using the said mark as an alignment mark.

FIG. 1 is a plan view of an inspection mark according to a conventional example. FIG. 2 is a plan view of an alignment mark according to a conventional example. FIG. 3 is a plan view showing a method for arranging inspection marks according to a conventional example. FIG. 4 is a plan view showing a method for arranging alignment marks according to a conventional example. FIGS. 5A and 5B are plan views (part 1) for explaining that the alignment marks cannot be densely arranged in the conventional example. FIGS. 6A and 6B are plan views (part 2) for explaining that the alignment marks cannot be densely arranged in the conventional example. FIG. 7 is an enlarged plan view of a silicon wafer according to each embodiment of the present invention. FIG. 8A is a plan view of an inspection mark according to the first example of the first embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along the line I-I in FIG. . FIGS. 9A and 9B are plan views for qualitatively explaining that the inspection marks can be arranged densely in the first example of the first embodiment of the present invention. FIG. 10 is a plan view showing an inspection mark arrangement method according to a comparative example. FIG. 11A is a plan view of an inspection mark according to the second example of the first embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along the line II-II in FIG. . FIG. 12 is a plan view (No. 1) of an inspection mark according to the third example of the first embodiment of the present invention. FIGS. 13A and 13B are plan views for qualitatively explaining that inspection marks can be arranged densely in the third example of the first embodiment of the present invention. FIG. 14 is a plan view (part 2) of the inspection mark according to the third example. FIG. 15 is a plan view (part 1) of an inspection mark according to a fourth example of the first embodiment of the present invention. FIG. 16 is a plan view (part 2) of the inspection mark according to the fourth example of the first embodiment of the present invention. FIG. 17A is a plan view for explaining a method of using the inspection mark according to the present embodiment, and FIG. 17B is a cross-sectional view taken along the line III-III in FIG. FIG. 18A is a plan view of an alignment mark according to the second embodiment of the present invention, and FIG. 18B is a cross-sectional view taken along line IV-IV in FIG. FIGS. 19A and 19B are plan views for qualitatively explaining that the alignment marks can be arranged densely in the second embodiment of the present invention. FIG. 20A is a plan view for explaining a method of using the alignment mark according to the second embodiment of the present invention, and FIG. 20B is a cross-sectional view taken along the line V-V in FIG. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 10 ... Semiconductor substrate, 2, 12 ... Inspection mark, 3, 7, 13, 17 ... Area definition frame, 6, 16 ... Alignment mark, 11 ... Silicon oxide film, 14 ... Dummy pattern, 15 ... Wiring, 18 ... Conductive film, 30 ... pattern for inspection of resist pattern, 31 ... photoresist, C ... chip, E ... empty area of chip, S ... scribe area, W ... semiconductor wafer.

Claims (5)

A semiconductor substrate on which a plurality of chips are formed;
A plurality of staggered marks formed in empty areas in the chip or scribe areas of the semiconductor substrate;
A semiconductor wafer comprising:   The mark is an inspection mark used when inspecting misalignment between a resist pattern formed above the semiconductor substrate and the semiconductor substrate, or used when aligning an exposure apparatus and the semiconductor device. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is an alignment mark. A semiconductor substrate;
A plurality of staggered marks formed in empty areas of the semiconductor substrate;
A semiconductor device comprising:   The mark is an inspection mark used when inspecting misalignment between a resist pattern formed above the semiconductor substrate and the semiconductor substrate, or used when aligning an exposure apparatus and the semiconductor device. The semiconductor device according to claim 3, wherein the semiconductor device is an alignment mark. A step of setting a plurality of virtual frames in which four corners are obliquely cut with respect to one side of the chip in a vacant area in the chip of the semiconductor substrate, or a scribe region of the semiconductor substrate;
Forming a plurality of marks on the semiconductor substrate within the virtual frame;
A method for manufacturing a semiconductor device, comprising:

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