JP2007184345A - Semiconductor device, manufacturing method therefor, and alignment inspection mark - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, a manufacturing method therefor, and an alignment inspection mark wherein the alignment inspection mark formed on an interlayer insulating film, when forming an analog circuit, can be detected with higher accuracy, in the subsequent alignment inspection step of resist pattern. <P>SOLUTION: The semiconductor device, comprising an analog circuit further, includes a via hole formed to the interlayer insulating film 2 in a chip region, and the alignment inspection mark 30, formed to the interlayer insulating film 2 in a scribe line region together with the via hole, in order to inspect positioning accuracy for resist pattern formed on the interlayer insulating film 2 of the chip region, after the formation of the via hole. The alignment inspection mark 30 is formed of only four holes 3, respectively arranged at four corners of a rectangular shape (r) in plan view. Each hole 3 is formed in a shape that is a congruent square in the plan view, and the length of a side of the square shape is equal to or larger than 4.5[μm] but smaller than 7.0[μm]. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a method for manufacturing the same, and an alignment inspection mark, and in particular, an alignment inspection mark formed on an interlayer insulating film when an analog circuit is formed can be accurately detected in a subsequent resist pattern alignment inspection process. It relates to the technology.

Circuit patterns necessary for LSI manufacture are sequentially exposed on the wafer by a plurality of photomask patterns. For example, a reduction projection exposure apparatus on which a predetermined photomask is set projects and exposes a pattern repeatedly while moving the projection area on the wafer one after another in the horizontal direction. As a result, a predetermined number of chip areas are obtained in the wafer.
Adjacent chip regions are separated from each other with a scribe line region. In general, alignment marks (also referred to as “alignment marks”) for aligning a plurality of types of patterns to be exposed are provided in the scribe line area. When performing pattern exposure a plurality of times in one area of the chip area, the exposure apparatus positions individual masks using alignment marks.

  Further, after the exposure process, it is inspected by using a “alignment inspection mark” whether or not alignment of a plurality of types of patterns is correctly performed. In this alignment inspection, alignment inspection marks having predetermined dimensions and shapes are formed and arranged on the first layer formed in the scribe line region and the second layer exposed in the subsequent process, respectively, and their relative positions are arranged. By visually measuring the amount of deviation with a predetermined device, it has been determined whether or not the pattern misalignment is within an allowable range (see, for example, Patent Documents 1 and 2).

  5A and 5B are a plan view and a cross-sectional view taken along arrow X2-X'2 showing a configuration example of the alignment inspection mark according to the conventional example. As shown in FIG. 5, an interlayer insulating film 92 made of a silicon oxide film or the like is provided on a semiconductor substrate 91 made of silicon or the like, and a trench 93 having a wafer as a bottom surface is formed in the interlayer insulating film 92. ing. A wiring film 94 made of aluminum or the like is provided on the interlayer insulating film 92 so as to cover the bottom surface and side walls of the trench 93. Further, a photoresist 95 that selectively covers the wiring film 94 is formed on the wiring film 94.

  Here, the trench 93 is an alignment inspection mark formed in the interlayer insulating film 92 in the scribe line region when a via hole (not shown) as a device pattern is formed in the interlayer insulating film 92 in the chip region. . The photoresist 95 is an alignment inspection mark formed on the wiring film 94 in the scribe line region when a resist pattern (not shown) is formed as an etching mask on the wiring film 94 in the chip region. . In FIGS. 5A and 5B, the four trenches 93 are first arranged by the first photomask so as to form a square in plan view. Next, a photoresist 95 is selectively formed and arranged on the outside of the square by a second photomask.

As shown in FIGS. 5A and 5B, the trench 93 formed and disposed in the interlayer insulating film 92 has a rectangular shape in plan view, and the length of the long side is a ′, and the short side is When the length (that is, the dimension width) is b ′, a ′ = 15 [μm] and b ′ = 0.5 [μm].
JP 2002-64055 A JP 2004-273612 A

By the way, in a semiconductor device such as a logic IC or a memory IC, a wiring film, an interlayer insulating film, a via hole, and the like are formed with a thin film or a fine pattern of less than 1 [μm]. It was possible to detect with high sensitivity by performing inspection using the alignment inspection marks having the shapes and dimensions shown in 5 (A) and (B).
However, in a semiconductor device including an analog circuit such as an RF-IC (hereinafter referred to as “analog circuit device”), a wiring film functioning as an antenna coil and an interlayer insulating film are formed to be at least 2 [μm] thick. It is normal. Therefore, when the alignment inspection mark having the shape and dimensions shown in FIGS. 5A and 5B is applied as it is to the manufacturing method of the analog circuit device, the trench 93 is buried by the thick wiring film 94. .

When the trench 93 is buried by the wiring film 94, the surface of the wiring film 94 approaches to a flat surface, and the inside of the trench 93 that has been blackish due to the adjustment of light becomes white. As a result, since the black and white contrast of the wiring film 94 is lowered, the analog circuit device tends to have low accuracy in detecting the position of the trench 93 (first problem).
In order to solve such problems, the present inventor has come up with the idea of increasing the dimension width b ′ of the trench 93 that is the alignment inspection mark. Then, the dimension width of the trench 93 which is the alignment inspection mark was set in several stages, and an analog circuit device was prototyped with each setting. As a result, if the dimension width b ′ of the trench 93 is excessively increased, foreign matter (polishing waste or the like) generated in the CMP process for the interlayer insulating film 92 enters the trench 93 and clogs the trench 93. I understood. If the trench 93 is clogged with foreign matter, the detection of the trench 93 itself becomes difficult, and the alignment inspection may not be performed (second problem).

  Therefore, the present invention has been made in view of the first and second problems, and the alignment inspection mark formed on the interlayer insulating film when the analog circuit is formed is used as a resist pattern later. An object of the present invention is to provide a semiconductor device, a manufacturing method thereof, and an alignment inspection mark that can be accurately detected in the alignment inspection process.

[Invention 1-3] In order to achieve the above object, a semiconductor device according to Invention 1 is a semiconductor device including an analog circuit, and includes an opening formed in an interlayer insulating film in a chip region, and formation of the opening. In order to inspect the alignment accuracy with a resist pattern formed on the interlayer insulating film in the chip region later, the alignment inspection mark formed on the interlayer insulating film in the inspection region is provided together with the opening, and the alignment The inspection mark is composed of only four holes respectively arranged at the four corners of the rectangle in plan view. Each of the holes is a congruent square in plan view, and the length of one side of the square is 4.5 [μm. The above is less than 7.0 [μm].

  Here, the “opening” is, for example, a via hole or a contact hole. The “inspection area” is, for example, a scribe line area. In the “semiconductor device including an analog circuit”, the interlayer insulating film formed on the semiconductor substrate and the wiring layer formed thereon are both thick, and the interlayer insulating film is, for example, about 1.5 to 2.5 [μm] The wiring film is, for example, about 4.0 to 5.0 [μm].

The semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein a distance between one hole constituting the alignment inspection mark and the other hole adjacent to the one hole is 4.5 [μm] or more. , Less than 7.0 [μm].
A semiconductor device according to a third aspect of the invention is the semiconductor device according to the first or second aspect of the invention, wherein the rectangle is a square.

  According to the semiconductor devices of the first to third aspects, since the interlayer insulating film and the wiring film are thick because of having an analog circuit, the four holes constituting the alignment inspection mark are longer in the vertical direction and in the horizontal direction than in the conventional case. Since the width in the direction is wide, it is possible to prevent the hole from being filled with the wiring film. In addition, since the dimensions of the opening surfaces of the four holes are smaller than the majority of foreign matters generated in the CMP process, clogging of the holes due to the foreign matters can be prevented. Therefore, the alignment inspection mark can be accurately detected in the alignment inspection process.

[Invention 4, 5] A method of manufacturing a semiconductor device according to Invention 4 is a method of manufacturing a semiconductor device including an analog circuit, comprising: forming an interlayer insulating film on a semiconductor substrate; and forming the interlayer insulating film in a chip region. Forming an opening, forming an inspection mark in alignment with the interlayer insulating film in the inspection region, forming a resist pattern on the interlayer insulating film in the chip region after forming the opening, and the resist And a step of inspecting the alignment accuracy of the pattern and the alignment inspection mark using the inspection mark, and the alignment inspection mark is composed of only four holes respectively arranged at four corners of the rectangle in plan view. The holes are congruent squares in plan view, and the length of one side of the squares is 4.5 [μm] or more and less than 7.0 [μm].

  According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth aspect of the present invention, in the method for manufacturing a semiconductor device according to the fourth aspect, in the step of forming the resist pattern, The resist pattern is formed on the insulating film, and a second alignment inspection mark made of resist is formed on the interlayer insulating film in the inspection region, and the alignment accuracy between the resist pattern and the alignment inspection mark is inspected. In the process, a relative positional deviation amount of the second alignment inspection mark with respect to the first alignment inspection mark is measured.

  According to the method for manufacturing a semiconductor device of the inventions 4 and 5, the interlayer insulating film and the wiring film are formed thick in order to form an analog circuit. Since the width in the vertical and horizontal directions is wide, it is possible to prevent the hole from being filled with the wiring film. In addition, since the dimensions of the opening surfaces of the four holes are smaller than the majority of foreign matters generated in the CMP process, clogging of the holes due to the foreign matters can be prevented. Thereby, the alignment inspection mark can be accurately detected in the alignment inspection process.

[Invention 6] The alignment inspection mark of Invention 6 includes an opening formed in an interlayer insulating film in a chip region when a semiconductor device including an analog circuit is manufactured, and the interlayer in the chip region after the opening is formed. In order to inspect the alignment accuracy with the resist pattern formed on the insulating film, the alignment inspection mark is formed on the interlayer insulating film in the inspection region together with the opening. And each of the holes is a congruent square in plan view, and the length of one side of the square is 4.5 [μm] or more, 7.0. It is less than [μm].

  With such a configuration, even if the interlayer insulating film and the wiring film are formed thick for forming an analog circuit, the four holes constituting the alignment inspection mark are wider than the conventional one. It is possible to prevent the hole from being filled with the film. In addition, since the dimensions of the opening surfaces of the four holes are smaller than the majority of foreign matters generated in the CMP process, clogging of the holes due to the foreign matters can be prevented. Therefore, the alignment inspection mark can be accurately detected in the alignment inspection process.

Embodiments of the present invention will be described below with reference to the drawings.
FIGS. 1A and 1B are a plan view showing a configuration example of alignment inspection marks 30 and 60 according to the embodiment of the present invention, and a cross-sectional view taken along arrow X1-X′1. The alignment inspection marks 30 and 60 according to the present embodiment include a via hole (not shown) formed in the interlayer insulating film 2 in the chip region and a resist pattern formed on the wiring film 4 in the chip region after the via hole is formed. In order to inspect the alignment accuracy with (not shown), each is formed on the interlayer insulating film 2 in the scribe line region and on the interlayer insulating film 2. The thickness of the interlayer insulating film 2 shown in FIG. 1B is 2 [μm], for example, and the thickness of the wiring film 4 is 4.5 [μm], for example.

  In FIG. 1A, each first alignment inspection mark 30 is composed of only four holes 3 that are respectively arranged at the four corners of a rectangle (in this embodiment, a square) r in plan view. ing. These holes 3 have the same shape and dimensions in plan view, and the shape is square. That is, the four holes 3 constituting the alignment inspection mark 30 are configured as congruent squares in plan view. The length of one side of the square hole 3 is 4.5 [μm] or more and less than 7.0 [μm]. As shown in FIG. 2, a plurality of alignment inspection marks 30 are formed in the scribe line region S of the semiconductor substrate. Also, an analog circuit device is built in the chip area C.

  As shown in FIG. 1B, the second alignment inspection mark 60 is a resist pattern formed on the wiring film 4 in the scribe line region. As shown in FIG. 1A, the second alignment inspection mark 60 is disposed so as to surround the first alignment inspection mark 30 in plan view. As shown in FIG. 1A, the separation distance between the left hole 3 and the left alignment inspection mark 30 is a, the dimensional width of the left hole 3 (that is, the length of one side) is b, and the left hole 3 is When the distance between the right hole 3 and the right hole 3 is c, the width of the right hole 3 is d, and the distance e between the right hole 3 and the right alignment inspection mark is Each e is 5 [μm] as an example.

  In an experiment conducted by the present inventor, when the shape and dimensions of the first alignment inspection mark 30 are set as described above, the interlayer insulating film 2 is formed as thick as about 2 [μm] for forming an analog circuit, and the wiring Even if the film 4 is formed to be as thick as about 4.5 [μm], it is possible to prevent the hole 3 from being buried by the wiring film 4. Further, the majority of foreign matter generated in the CMP process for the interlayer insulating film 2 has a diameter of 7 [μm] or more, and the length of one side of the square hole 3 is less than 7.0 [μm]. It has also been found that clogging of the hole 3 due to can be prevented.

Next, a method for manufacturing a semiconductor device using the alignment inspection mark will be described.
3A to 3C are process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3A, after an analog circuit element (not shown) is formed on the semiconductor substrate 1 in the chip region (configured by MOS transistors, capacitors, resistors, etc.), the entire surface of the semiconductor substrate 1 (that is, An interlayer insulating film 2 is formed on both the semiconductor substrate 1 in the chip region and on the semiconductor substrate 1 in the scribe line region. The semiconductor substrate 1 is, for example, single crystal silicon, and the interlayer insulating film 2 is, for example, a silicon oxide film. The interlayer insulating film 2 is formed by, for example, CVD. Next, the entire surface of the interlayer insulating film 2 is planarized by, eg, CMP processing. The thickness of the interlayer insulating film 2 after planarization is, for example, 2 [μm] as described above.

  Next, a photoresist (not shown) is applied on the entire surface of the interlayer insulating film 2. Then, using a first photomask (not shown), the photoresist is exposed and developed to form a resist pattern 11. A via hole is formed in the interlayer insulating film 2 in the chip region exposed from below the resist pattern 11. Note that the first photomask is provided with a light-shielding pattern for exposing the photoresist so that the photoresist is removed from above the region to be the hole 3 (see FIG. 1B). By the exposure and development processing using the first photomask, the region to be the hole 3 is exposed from the bottom of the resist pattern 11.

Next, as shown in FIG. 3B, the interlayer insulating film 2 is dry-etched using the resist pattern 11 as a mask to form a via hole (not shown) in the interlayer insulating film 2 in the chip region, and at the same time, a scribe line. A hole 3 is formed in the interlayer insulating film 2 in the region. After the via hole and the hole 3 are formed, the resist pattern 11 is removed by ashing.
Next, as shown in FIG. 3C, a wiring film 4 is formed over the interlayer insulating film 2. The wiring film 4 is, for example, an aluminum film, and the thickness thereof is, for example, 4.5 [μm] as described above. The wiring film 4 is formed by sputtering, for example.

  Next, a photoresist (not shown) is applied to the entire surface of the wiring film 4. Then, using a second photomask (not shown), the photoresist is exposed and developed to form a resist pattern for patterning the wiring film 4. Here, since the second photomask is provided with a light-shielding pattern for exposing the photoresist so that the second inspection pattern 60 is formed in the scribe line region, the above-described pattern is formed on the wiring film 4 in the chip region. Simultaneously with the formation of the resist pattern, a second inspection pattern 60 is formed on the wiring film 4 in the scribe line region.

  Thereafter, alignment inspection of the resist pattern formed on the wiring film 4 with respect to the underlayer is performed using the first and second alignment inspection marks. For example, the coordinate α of the center position of the first alignment inspection mark 30 is recognized by a CCD camera or the like (not shown) attached to the exposure apparatus, as shown in FIG. Next, as shown in FIG. 4, the coordinate β of the center position of the second alignment inspection mark 60 is recognized. Then, the coordinate α and the coordinate β are compared, and the relative positional deviation amount of the second alignment inspection mark 60 with respect to the first alignment inspection mark 30 is calculated.

  As described above, according to the embodiment of the present invention, the interlayer insulating film 2 and the wiring film 4 are thick because of having an analog circuit, but the four holes 3 constituting the first alignment inspection mark 30 are Since the width in the vertical direction and the horizontal direction is wider in plan view than in the conventional trench, it is possible to prevent the hole 3 from being filled with the wiring film 4. Moreover, since the dimension of the opening surface of the four holes 3 is smaller than the majority of foreign matters generated in the CMP process, clogging of the holes 3 due to the foreign matters can be prevented. Thereby, the alignment inspection mark 30 can be detected with high accuracy in the alignment inspection step.

  In this embodiment, the alignment inspection mark 30 corresponds to the “(first) alignment inspection mark” of the present invention, and the alignment inspection mark 60 corresponds to the “second alignment inspection mark” of the present invention. The scribe line region S corresponds to the “inspection region” of the present invention.

The figure which shows the structural example of the alignment inspection marks 30 and 60 which concern on embodiment. The figure which shows the example of arrangement | positioning of the alignment inspection mark 30. FIG. 10A and 10B illustrate a method for manufacturing a semiconductor device according to an embodiment. The figure which shows typically the positional offset amount of the alignment inspection marks 30 and 60. FIG. The figure which shows the structural example of the alignment inspection mark which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 interlayer insulation film, 3 holes, 4 wiring films, 11 resist pattern, 30 1st inspection mark, 60 2nd alignment inspection mark, C chip area | region, S scribe line area | region, r rectangle (square), The coordinates of the center position of the α alignment inspection mark 30 and the coordinates of the center position of the β alignment inspection mark 60

Claims (6)

A semiconductor device including an analog circuit,
In order to inspect the alignment accuracy between the opening formed in the interlayer insulating film in the chip region and the resist pattern formed on the interlayer insulating film in the chip region after the opening is formed, together with the opening With alignment inspection marks formed on the interlayer insulating film in the inspection region,
The alignment inspection mark is composed of only four holes respectively arranged at the four corners of the rectangle in plan view, and each of the holes is a congruent square in plan view, and the length of one side of the square is 4.5. [Μm] or more and less than 7.0 [μm].   An interval between the one hole constituting the alignment inspection mark and the other hole adjacent to the one hole is 4.5 [μm] or more and less than 7.0 [μm], The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the rectangle is a square. A method of manufacturing a semiconductor device including an analog circuit,
Forming an interlayer insulating film on the semiconductor substrate;
Forming an opening in the interlayer insulating film in the chip region and forming an inspection mark in alignment with the interlayer insulating film in the inspection region;
Forming a resist pattern on the interlayer insulating film in the chip region after forming the opening; and
A step of inspecting the alignment accuracy of the resist pattern and the alignment inspection mark using the inspection mark,
The alignment inspection mark is
It consists of only four holes that are placed at the four corners of the rectangle in plan view,
Each of the holes is a congruent square in a plan view, and the length of one side of the square is 4.5 [μm] or more and less than 7.0 [μm]. When the alignment inspection mark is the first alignment inspection mark,
In the step of forming the resist pattern,
Forming the resist pattern on the interlayer insulating film in the chip region, and forming a second alignment inspection mark made of resist on the interlayer insulating film in the inspection region;
In the step of inspecting the alignment accuracy between the resist pattern and the alignment inspection mark,
5. The method of manufacturing a semiconductor device according to claim 4, wherein a relative displacement amount of the second alignment inspection mark with respect to the first alignment inspection mark is measured. Positions of an opening formed in an interlayer insulating film in a chip region and a resist pattern formed on the interlayer insulating film in the chip region after forming the opening when manufacturing a semiconductor device including an analog circuit In order to inspect the alignment accuracy, the alignment inspection mark formed in the interlayer insulating film in the inspection region together with the opening,
The alignment inspection mark is composed of only four holes respectively arranged at the four corners of the rectangle in plan view. Each of the holes is a congruent square in plan view, and the length of one side of the square is 4.5. The alignment inspection mark characterized by being [μm] or more and less than 7.0 [μm].

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