JP3583044B2 - Semiconductor device and method of controlling misalignment - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for controlling an alignment shift, and more particularly, to a semiconductor device having a multilayer wiring structure in which an alignment shift measuring mark for measuring an alignment shift in a photolithography process and an alignment shift control method. It relates to a control method.
[0002]
Problems to be solved by the prior art and the invention
When manufacturing a semiconductor device having a multilayer wiring structure, as shown in FIGS. 2A and 2B, first, an interlayer insulating film 20 in which lower metal wiring layers 21b and 21a and an interlayer insulating film 22 are sequentially formed is formed. A wiring layer material is deposited thereon. Next, in a photolithography process, alignment is performed using a stepper, exposure and development are performed to form a resist pattern (not shown) having a predetermined shape, and the wiring layer material is patterned using the resist pattern as a mask. Then, the upper metal wiring layer 23a is formed, and the alignment deviation measurement mark 23b is formed from the wiring layer material. Thereafter, an interlayer insulating film 24 is formed on these layers, and when a via hole is formed in the interlayer insulating film 24, the alignment shift is measured by the alignment shift inspection device using the alignment shift measuring mark 23b. .
[0003]
That is, the measurement of the alignment deviation is performed by using the alignment deviation measurement mark 23b as a main scale and using the mark 26 of the resist pattern 25 formed thereon as a sub-scale, and using the midpoint of the main scale and the midpoint of the sub-scale. From the coordinate difference with Since this measurement is usually performed in image recognition, if there is another pattern near the misalignment measurement mark 23b, the misalignment inspection apparatus may erroneously recognize the other pattern as the misalignment measurement mark. Therefore, usually, the misalignment measurement mark 23b is formed in the other pattern prohibition region III where no pattern other than the mark is arranged, and no other pattern is arranged in the vicinity thereof.
[0004]
However, if there is a large area without any wiring layer, an interlayer insulating film is deposited thereon and when planarization is performed by a CMP (Chemical Mechanical Polishing) method, the interlayer insulating film on a region where no wiring layer is present is removed. A dishing occurs that is thinner than the interlayer film on the region where the wiring layer exists. In particular, in a semiconductor device using a multilayer wiring, the influence of the dishing is accumulated, and a height difference between a region where a wiring layer exists and a region where the wiring layer does not exist becomes remarkable. As a result, when processing is performed under processing conditions suitable for a region where a wiring layer exists, a pattern formation defect due to a focus shift occurs in a region where a wiring layer does not exist.
[0005]
Therefore, in order to prevent such an influence of dishing, as shown in FIGS. 2A and 2B, the metal wiring layer 21b below the misalignment measurement mark 23b is replaced with the misalignment measurement mark 23b. A method of arranging a pattern in the vicinity of another pattern under the prohibited area III has been proposed.
[0006]
However, when the image of the misalignment measurement mark 23b formed of the metal wiring layer is image-recognized, if the pattern of the metal wiring layer 21b formed of the same material exists behind the mark, the recognition of the misalignment measurement mark 23b is not performed. The problem that it becomes difficult to perform arises.
[0007]
As another method for preventing the influence of dishing, as shown in FIG. 3A, a method of regularly arranging a plurality of metal wiring layers 31b below the misalignment measurement mark 33b in a rectangular parallelepiped shape is proposed. (JP-A-5-94933).
[0008]
According to this method, the flatness of the interlayer insulating film can be maintained, dishing can be prevented, and the misalignment can be prevented by using a portion where the misalignment measurement mark 33b does not overlap the lower metal wiring layer 31b. It can be measured visually.
[0009]
However, in order to measure the alignment deviation with high accuracy, it is difficult to perform the measurement visually, and automatic measurement by an alignment deviation inspection device is indispensable. Therefore, this method has a problem that measurement accuracy is limited.
[0010]
In addition, when the visual measurement is applied to the automatic measurement, as shown in FIG. 3B, the portion α where the metal wiring layer 31b is located below and the portion β where the metal wiring layer 31b is not located are measured similarly, Therefore, due to the unevenness due to the presence or absence of the lower metal wiring layer 31b, the misalignment measurement mark 33b is not accurately detected (X in FIG. 3B), and as a result, the measurement accuracy is reduced. There is a problem that it decreases.
[0011]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is possible to prevent the interlayer insulating film from being thinned due to the formation of the alignment deviation measurement mark, and to improve the recognition accuracy of the alignment deviation measurement mark, thereby improving metal interconnection. It is an object of the present invention to provide a highly reliable semiconductor device by preventing the occurrence of pattern formation failure, and to provide a method for controlling misalignment for manufacturing a highly reliable semiconductor device.
[0012]
[Means for Solving the Problems]
According to the present invention, there is provided a multilayer wiring structure including a plurality of metal wiring layers formed on a semiconductor substrate and an interlayer insulating film disposed between the metal wiring layers. A semiconductor device having a formed misalignment measurement mark, wherein the misalignment measurement mark is formed in a pattern prohibited area other than the misalignment measurement mark, and a metal wiring layer is formed below the pattern prohibited area. Ri but Na is removed, surrounding the misalignment measurement mark, from the alignment in the displacement region other than the pattern prohibition region other than the measurement marks, the interlayer insulating film formed a mark for the misalignment measurements including an outer peripheral region on the lower interlayer insulating film, a semiconductor device is provided a metal wiring layer ing arranged.
[0013]
Further, according to the present invention, the position of the alignment deviation measurement mark in the semiconductor device is recognized by an optical signal output, and the alignment deviation in the photolithography process is controlled based on the position of the alignment deviation measurement mark. And a method for controlling the misalignment.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
The semiconductor device of the present invention has a multilayer wiring structure formed on a semiconductor substrate.
[0015]
The semiconductor substrate in the present invention includes, for example, elemental semiconductors such as silicon and germanium, compound semiconductors such as GaAs, InGaAs, and ZnSe, and further includes an SOI substrate or a multilayer SOI substrate. Among them, a silicon substrate is preferable.
[0016]
The plurality of metal wiring layers may be a layer formed as an electrode of a semiconductor element such as a transistor or a capacitor, or may be a wiring layer for connecting these elements, It may be a wiring layer formed of a so-called dummy that does not function as an electrode or a wiring of this type, or may be a plug or the like buried in a contact hole, a via hole, or the like. The material constituting the metal wiring layer is not particularly limited, and is a material usually used for electrodes and wirings, for example, metals such as gold, platinum, silver, copper, and aluminum; titanium, tantalum, tungsten, and the like. High melting point metal: It can be formed by a single layer film or a laminated film of a high melting point metal such as silicide and polycide. The thickness of the metal wiring layer is not particularly limited, and may be, for example, about 100 to 10000 °.
[0017]
Among the plurality of metal wiring layers, the lowermost metal wiring may be formed immediately above the semiconductor substrate as described above, or may be formed via an interlayer insulating film. The term “plurality” means two or more layers, but in the present invention, it is effective to form the third and subsequent wiring layers (upper layer than the second layer). Is preferred.
[0018]
The interlayer insulating film is provided between the metal wiring layers as described above in order to secure the insulating property of the metal wiring layer. For example, a silicon oxide film, a silicon nitride film, a SOG film, and a doped silicon oxide film are provided. A single-layer film such as a film, HSQ, HOSP, FLARE, or a laminated film of two or more of these. The thickness of the interlayer insulating film is not particularly limited, and may be, for example, about 5000-10000 °.
[0019]
The misalignment measurement mark is formed by the second or higher metal wiring layer so as to be electrically independent, that is, to float. The metal wiring constituting this mark can be formed with the above-mentioned material and film thickness. In addition, the shape is not particularly limited, and examples thereof include a circle; a polygon such as a triangle and a square; and a substantially polygon having rounded corners. Among them, a square shape such as a square or a rectangle is preferable. The size is, for example, an area of about 1 to 160 μm ² , and particularly about 5 μm × 5 μm to 40 μm × 40 μm in the case of a square shape.
[0020]
Further, the alignment deviation measurement mark is formed in the other pattern prohibited area. Here, the other pattern prohibited area means an area where no wiring pattern other than the mark is formed, for example, between a circuit area and a circuit area on a semiconductor substrate, between a circuit area and a memory area, Examples include a region arranged on an edge of a semiconductor substrate, a dicing line, and the like. The other pattern prohibited area is set to such an extent that an alignment deviation inspection device that can recognize this mark by an optical signal output (image), which is generally used, does not erroneously recognize a wiring pattern located near this mark as this mark. Must be large enough to surround this mark. Specifically, depending on the size of the mark, the mark may be surrounded by a width of about 10 μm or more from the outer periphery of the mark, or may be surrounded by the mark at a size of about 50% of the mark. Preferably, it is set.
[0021]
In the other pattern prohibition region, the metal wiring layer is not present below the other pattern prohibition region, that is, in the projection region below the other pattern prohibition region. Specifically, when the alignment deviation measurement mark is formed by the second metal wiring layer, the first metal wiring layer does not exist at all in the projection area below the other pattern prohibited area. However, when the misalignment measurement mark is formed by the third metal wiring layer, the first and second metal wiring layers do not exist in the projection area below the other pattern prohibited area. do not do. Thus, when the alignment deviation measurement mark is recognized by an optical signal output from above, an error caused by the presence of the metal wiring layer near the alignment deviation measurement mark can be prevented.
[0022]
It is preferable that a metal wiring layer below the metal wiring layer constituting the misalignment measurement mark is disposed below the outer peripheral area of the other pattern prohibited area.
[0023]
Here, the outer peripheral region of the other pattern prohibition region depends on the size and shape of the other pattern prohibition region, but, for example, a size surrounding this region with a width of about 1 μm or more from the outer periphery of the other pattern prohibition region, or It is preferable that the area is set to be about 10% of the other pattern prohibited area so as to surround this area.
[0024]
The metal wiring layer disposed below the outer peripheral region of the other pattern prohibition region is a layer lower than the metal wiring layer forming the misalignment measurement mark, preferably a layer immediately below the metal wiring layer forming the mark. Is preferred. This metal wiring layer may be a metal wiring layer constituting an electrode or a wiring layer in a circuit below the alignment deviation measurement mark, a so-called dummy wiring layer, or a floating wiring layer. It is preferable that the metal wiring layers disposed below the outer peripheral region of the other pattern prohibited region are arranged regularly and in an island shape below the outer peripheral region of the other pattern prohibited region. The shape of the island here is not particularly limited, and may be a shape that integrally surrounds the outer periphery of the other pattern prohibition region, or may be the same shape as the shape of the alignment deviation measurement mark. The size is preferably, for example, about 1 to 100 μm ² , particularly about 1 μm × 1 μm to 10 μm × 10 μm in the case of a square shape. It is preferable that a plurality of islands are arranged in the outer peripheral region of the alignment deviation measurement mark.
[0025]
To be regularly arranged means that islands having the same shape and the same size are arranged at the same interval. Specifically, in the case of the shape and size as exemplified above, it is preferable that the islands are regularly arranged at intervals of about 2 to 20 μm. As described above, when the island is smaller than the misalignment measurement mark and regularly surrounds the outer periphery of the other pattern prohibition region, the island is formed by these metal wiring layers as compared with the shape that surrounds integrally. This is because the parasitic capacitance can be reduced.
[0026]
The method for controlling alignment displacement according to the present invention is a method for accurately measuring a displacement of an object to be aligned on an upper layer thereof by using an alignment displacement measurement mark and controlling the displacement in a semiconductor device manufacturing process. . Specifically, in a semiconductor device manufacturing process, a resist layer is formed by a photolithography process on a semiconductor substrate on which the above-described misalignment measurement marks have been formed, and a misalignment inspection pattern having a predetermined shape is formed. After exposing and developing a desired mask shape including the resist pattern on the resist layer, the position of the alignment measurement mark is recognized by an optical signal output. At the same time, the position of the misalignment inspection pattern formed on the resist layer is similarly recognized. Then, the two positions are compared, for example, by detecting the difference between the center coordinates of the alignment deviation measurement mark and the alignment deviation inspection mark, and determining whether there is any deviation in the alignment of the mask shape with the resist layer. Measure for any deviation.
[0027]
If the misalignment is detected to cause circuit operation failure or the like, the resist layer is removed, a resist layer is formed again, pattern correction is performed based on the detected misalignment value, and patterning is performed. In the same manner as in the above, measurement is made to see if any misalignment has occurred.
Thus, the misalignment in the photolithography process can be minimized.
[0028]
In the present invention, the alignment deviation measurement mark can be used not only for alignment deviation measurement, but also as an alignment mark in a photolithography process on a layer above the mark. It may be formed in advance and used for alignment of a metal wiring layer in the same layer with reference to this mark.
[0029]
Hereinafter, a semiconductor device and a method for controlling an alignment shift according to the present invention will be described with reference to the drawings.
[0030]
In the semiconductor device of this embodiment, as shown in FIGS. 1A and 1B, the lower metal wiring layer 11a is provided in the circuit region I on the interlayer insulating film 10 and the other pattern prohibited region III and the circuit region I are provided. The lower metal wiring layer 11b is formed in a region II other than the above, and no metal wiring layer is formed below the other pattern prohibition region III corresponding to a region where a misalignment measurement mark will be formed later. On these lower metal wiring layers 11a and 11b, a lower metal wiring layer 13a is formed in the circuit region I and an alignment deviation measurement mark 13b is formed in the other pattern prohibition region III via the interlayer insulating film 12.
[0031]
The lower wiring layer 11b is regularly arranged in an island shape in the outer peripheral area of the other pattern prohibited area III.
[0032]
The semiconductor device as described above can be manufactured by the following method.
[0033]
First, a metal film having a thickness of about 5000 ° is formed on the interlayer insulating film 10 by a sputtering method, and the metal film is patterned into the lower metal wiring layer 11a in the circuit region I by a photolithography and dry etching process. At this time, the lower metal wiring layer 11b is also formed in the region II other than the circuit region I and the other pattern prohibition region III with a shape that can be stably processed, for example, L / W = about 4 μm / 4 μm. Note that a metal wiring layer is not formed below the other pattern prohibition region III.
[0034]
Next, an interlayer insulating film 12 having a thickness of about 15000 ° is deposited, and then flattened by a CMP method. At this time, since the lower metal wiring layer 11b is also arranged in the region II which is the outer peripheral region of the other pattern prohibition region III, the dishing caused by the absence of the metal wiring layer in the region below the other pattern prohibition region III. This prevents the interlayer insulating film 12 from becoming thinner.
[0035]
Further, a metal film having a thickness of about 5000 ° is formed on the interlayer insulating film 12 by a sputtering method, and the metal film is patterned into an upper metal wiring layer 13a in the circuit region I by a photolithography and dry etching process. In the other pattern prohibition region III, for example, the alignment deviation measurement mark 13b having a size of about L / W = 25 μm / 25 μm is formed. At this time, even in the circuit region I near the other pattern prohibition region III, since the thickness of the interlayer insulating film 12 is kept uniform with the other regions, the formation failure of the upper wiring layer 13a does not occur.
[0036]
Subsequently, an interlayer insulating film 14 having a thickness of about 15000 ° is deposited, and the surface of the interlayer insulating film 14 is planarized by a CMP method.
[0037]
Next, a resist layer 15 is formed on the interlayer insulating film 14, and an opening (not shown) for forming a via hole in the interlayer insulating film 14 in the circuit region I is formed in the resist layer 15 by photolithography and dry etching. Then, a mark 16 for alignment deviation inspection is formed on the alignment deviation measurement mark 13b. Thereafter, using the mark 13b for alignment deviation measurement as a main scale, the coordinates of the midpoint are detected by a commercially available automatic measuring device for alignment deviation inspection, and the mark 16 for alignment deviation inspection of the resist layer 15 is used as a vernier scale. The coordinates of the midpoint are detected, and the alignment deviation is determined from the difference between the two coordinates. At this time, since no metal wiring is formed behind (below) the misalignment measurement mark 13b, the position of the misalignment measurement mark 13b can be accurately detected, and the misalignment is measured with high accuracy. It becomes possible.
[0038]
That is, if the measurement of the misalignment is such that the misalignment causes a circuit operation failure, for example, 0.05 μm to 0.2 μm or more, the resist layer 15 is removed, and a resist layer is formed again. Patterning is performed by performing position correction based on the detected misalignment value, similarly detecting the coordinates of the midpoint of the misalignment measurement mark 13b using the misalignment measurement mark 13b as the main scale, and further detecting misalignment of the resist layer 15 for misalignment. Using the mark 16 as a vernier scale, the coordinates of the midpoint are detected, the alignment deviation is determined from the difference between the two coordinates, and this is repeated until the alignment deviation is tolerable, and the photolithography process for forming a via hole is repeated. The misalignment can be reduced.
[0039]
【The invention's effect】
According to the present invention, the misalignment measurement mark composed of either the second layer or the upper metal wiring layer is formed in the other pattern prohibited area, and the metal wiring layer is formed below the other pattern prohibited area. Since it has been removed, it is easy to detect the boundary of the alignment deviation measurement mark, and the alignment deviation in the photolithography process can be measured with high accuracy.
[0040]
In particular, since the metal wiring layer lower than the metal wiring layer forming the misalignment measurement mark is arranged below the outer peripheral area of the other pattern prohibition area, the interlayers arranged above and below the misalignment measurement mark are arranged. A highly reliable semiconductor device that can prevent thinning due to dishing of an insulating film, suppress a focus shift at the time of exposure in photolithography, and prevent a defective formation of a pattern of a metal wiring layer in a circuit. Can be provided.
[Brief description of the drawings]
FIGS. 1A and 1B are a schematic plan view of a main part and a schematic cross-sectional view of a main part, for explaining an embodiment of a semiconductor device of the present invention.
2A and 2B are a schematic plan view of a main part and a schematic cross-sectional view of a main part, for explaining an example of a conventional semiconductor device.
FIG. 3 is a schematic plan view of a main part for describing another embodiment of a conventional semiconductor device.
[Explanation of symbols]
10, 13, 14 Interlayer insulating films 11a, 11b Lower metal wiring layer 13a Upper gold image wiring layer 13b Alignment misalignment measurement mark 15 Resist layer 16 Alignment misalignment inspection mark I Circuit area II Other than circuit area and other pattern prohibited area Area III other pattern prohibited area

Claims (3)

It has a multilayer wiring structure including a plurality of metal wiring layers formed on a semiconductor substrate and an interlayer insulating film disposed between the metal wiring layers, and has a misalignment measurement formed by a second or higher metal wiring layer. a semiconductor device having a use mark, the alignment displacement measuring mark is formed in the pattern prohibition region other than the mark for misalignment measurement, Ri Na and the metal wiring layer is removed at the lower of the pattern prohibition region In an area other than the pattern inhibition area other than the alignment shift measurement mark including the outer peripheral area, surrounding the alignment shift measurement mark, on an interlayer insulating film below the interlayer insulating film on which the alignment shift measurement mark is formed. , a semiconductor device metal wiring layers ing arranged. 2. The semiconductor device according to claim 1 , wherein the lower metal wiring layers are arranged regularly and in an island shape. The position of the mark for misalignment measurement in the semiconductor device according to claim 1 or 2 recognizes by the optical signal output, consists in controlling the misalignment in the photolithography process with respect to the position of the mark for the misalignment measurement How to control misalignment.

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