JP2001176780A - Semiconductor device and method for displacement of alignment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent failures in the formation of a metallic wiring pattern and provide a highly reliable semiconductor device by preventing thinning of an interlayer insulation film, due to the formation of marks for measuring displacements in alignment and improving the recognition accuracy of the mark thereof. SOLUTION: This semiconductor device has a multilayer wiring structure, formed by laminating a plurality of metallic wiring layers 11a, 11b and 13a and a plurality of interlayer insulation films 10, 12 and 14. A mark 13b for measuring displacement of alignment, which is formed of a metal wiring layer on the second layer or on the upper layer, is formed in other pattern inhibited region III, and the metal wiring layer is removed in the lower side within the other pattern inhibited region III.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for controlling an alignment shift, and more particularly, to a multilayer wiring structure having an alignment shift measuring mark for measuring an alignment shift in a photolithography process. And a method of controlling alignment deviation.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device having a multilayer wiring structure, FIG.
And (b), first, the lower metal wiring layer 21
A wiring layer material is deposited on the interlayer insulating film 20 on which b, 21a and the interlayer insulating film 22 are sequentially formed. Next, in a photolithography process, alignment is performed using a stepper, exposure and development are performed to form a resist pattern (not shown) having a predetermined shape, and the wiring layer material is patterned using the resist pattern as a mask. Then, the upper metal wiring layer 23a is formed, and the alignment deviation measurement mark 23b is formed from the wiring layer material. Thereafter, an interlayer insulating film 24 is formed on these upper layers, and when forming a via hole in the interlayer insulating film 24, the alignment deviation measurement mark 23b is used.
The misalignment is measured by the misalignment inspection apparatus.

In other words, alignment misalignment is measured using the alignment misalignment measurement mark 23b as a main scale, and the mark 26 of the resist pattern 25 formed thereover.
Is used as the vernier scale, and is obtained from the coordinate difference between the midpoint of the main scale and the midpoint of the vernier scale. Since this measurement is usually performed in image recognition, the alignment deviation measurement mark 23b
If there is another pattern near the mark, the misalignment inspection apparatus may erroneously recognize the other pattern as the misalignment measurement mark. Formed in the other pattern prohibition region III that is not arranged,
No other pattern is arranged in the vicinity thereof.

However, if there is a large area without any wiring layer, an interlayer insulating film is deposited thereon, and the
When flattening is performed by the physical polishing method, dishing occurs in which the interlayer insulating film on the region where the wiring layer does not exist is thinner than the interlayer film on the region where the wiring layer exists.
In particular, in a semiconductor device using a multilayer wiring, the effect of the dishing is accumulated, and a height difference between a region where a wiring layer exists and a region where the wiring layer does not exist becomes remarkable. As a result, when processing is performed under processing conditions suitable for a region where a wiring layer exists, pattern formation failure due to a focus shift occurs in a region where a wiring layer does not exist.

Therefore, in order to prevent the influence of dishing, as shown in FIGS. 2 (a) and 2 (b),
The metal wiring layer 21b lower than the alignment deviation measurement mark 23b is moved to the alignment deviation measurement mark 23b.
There has been proposed a method of arranging it in the vicinity of another pattern below the prohibited area III.

However, when recognizing an image of the misalignment measuring mark 23b formed of the metal wiring layer, if the pattern of the metal wiring layer 21b formed of the same material exists behind the mark, the misalignment measuring mark 23b is not recognized.
There is a problem that it becomes difficult to recognize the image.

As another method for preventing the influence of dishing, as shown in FIG. 3A, a plurality of metal wiring layers 31b below the alignment deviation measuring mark 33b are regularly arranged in a rectangular parallelepiped shape. A method has been proposed (JP-A-5-94933).

According to this method, the flatness of the interlayer insulating film can be maintained, dishing can be prevented, and at the same time, the position where the misalignment measuring mark 33b does not overlap the lower metal wiring layer 31b is used. The misalignment can be measured visually.

However, in order to measure the alignment deviation with high accuracy, it is difficult to perform the measurement visually, and automatic measurement by an alignment deviation inspection device is indispensable. Therefore, this method has a problem that measurement accuracy is limited.

When the visual measurement is applied to the automatic measurement, as shown in FIG. 3 (b), a portion α where the metal wiring layer 31b is located below and a portion β where the metal wiring layer 31b is not located are similarly measured. Is averaged, so that the lower metal wiring layer 31b
Due to the unevenness due to the presence or absence of the mark, the detection of the alignment deviation measurement mark 33b is not accurately performed (FIG. 3B,
X) As a result, there is a problem that the measurement accuracy is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is intended to prevent the interlayer insulating film from being thinned due to the formation of the alignment deviation measurement mark and to improve the recognition accuracy of the alignment deviation measurement mark. It is another object of the present invention to provide a highly reliable semiconductor device by preventing the occurrence of a formation failure of a metal wiring pattern, and to provide a method of controlling an alignment shift for manufacturing a highly reliable semiconductor device.

[0012]

According to the present invention, there is provided a multilayer wiring structure comprising a plurality of metal wiring layers formed on a semiconductor substrate and an interlayer insulating film disposed between the metal wiring layers.
A semiconductor device having a misalignment measurement mark formed by a layer or an upper metal wiring layer, wherein the misalignment measurement mark is formed in another pattern prohibition region, and the misalignment measurement mark is formed in the other pattern prohibition region. A semiconductor device in which a metal wiring layer is removed below the semiconductor device.

According to the present invention, the position of the alignment deviation measurement mark in the semiconductor device is recognized by an optical signal output, and the alignment deviation in the photolithography process is determined with reference to the position of the alignment deviation measurement mark. , And a method for controlling the misalignment, comprising:

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention has a multilayer wiring structure formed on a semiconductor substrate.

The semiconductor substrate according to the present invention includes, for example, elemental semiconductors such as silicon and germanium, GaAs and In.
Compound semiconductors such as GaAs and ZnSe, and SO
An I substrate, a multilayer SOI substrate, or the like can be given. Among them, a silicon substrate is preferable.

Further, the plurality of metal wiring layers may be layers formed as electrodes of semiconductor elements such as transistors and capacitors, or wiring layers for connecting these elements. However, it may be a wiring layer formed as a so-called dummy that does not function as a normal electrode or wiring, or may be a plug or the like buried in a contact hole, a via hole, or the like. The material constituting the metal wiring layer is not particularly limited, and materials usually used for electrodes and wiring, for example, gold, platinum, silver,
Metals such as copper and aluminum; refractory metals such as titanium, tantalum and tungsten; and single-layer films or laminated films such as silicide and polycide with high-melting metals. The thickness of the metal wiring layer is not particularly limited, and is, for example, about 100 to 10000 °.

[0017] Of the plurality of metal wiring layers, the lowermost metal wiring may be formed immediately above the semiconductor substrate as described above, or may be formed via an interlayer insulating film. Note that the term “plurality” means two or more layers. In the present invention, three or more layers are required because they are effective for forming the third and subsequent wiring layers (upper layers than the second layer). Is preferred.

The interlayer insulating film is provided between the metal wiring layers as described above to ensure the insulating property of the metal wiring layer. For example, a silicon oxide film, a silicon nitride film, a SOG film, a doped Silicon oxide film, HSQ,
A single-layer film such as HOSP or FLARE, or a laminated film of two or more of these films may be used. The thickness of the interlayer insulating film is not particularly limited, and is, for example, 5,000 to 10,000.
Å degree.

The misalignment measurement mark is formed by the second or higher metal wiring layer so as to be electrically independent, that is, to be floating. The metal wiring forming this mark can be formed with the above-mentioned material and film thickness. The shape is not particularly limited, and examples thereof include a circle; a polygon such as a triangle and a square; and a substantially polygonal shape having rounded corners. Among them, a square shape such as a square or a rectangle is preferable. The size is, for example, an area of about 1 to 160 μm ² , and particularly about 5 μm × 5 μm to 40 μm × 40 μm in the case of a square shape.

Further, the alignment deviation measuring mark is
It is formed in another pattern prohibited area. Here, the other pattern prohibited area means an area where no wiring pattern other than the mark is formed, for example, between a circuit area and a circuit area on a semiconductor substrate, between a circuit area and a memory area, Examples include a region disposed on an edge of a semiconductor substrate, a dicing line, and the like. The other pattern prohibited area is set to such an extent that an alignment misalignment inspection apparatus that can recognize this mark by optical signal output (image), which is generally used, does not mistakenly recognize a wiring pattern located near this mark as this mark. Must be large enough to surround this mark. More specifically, depending on the size of the mark, the mark may be surrounded by a width of about 10 μm or more from the outer periphery of the mark, or may be surrounded by a size of about 50% of the mark. Preferably, it is set.

In the other pattern forbidden area, the metal wiring layer is not present below the other pattern forbidden area, that is, in the projected area below the other pattern forbidden area. In particular,
When the misalignment measurement mark is formed by the second metal wiring layer, the first metal wiring layer does not exist at all in the projection area below the other pattern prohibited area, and the misalignment measurement is performed. When the use mark is formed by the third metal wiring layer, the first and second metal wiring layers do not exist at all in the projected area below the other pattern prohibited area. As a result, the misalignment measurement mark
When the recognition is performed by an optical signal output from above, it is possible to prevent an error caused by the presence of the metal wiring layer in the vicinity of the alignment deviation measurement mark.

It is preferable that a metal wiring layer lower than the metal wiring layer forming the misalignment measurement mark be disposed below the outer peripheral area of the other pattern prohibited area.

Here, the outer peripheral area of the other pattern prohibited area depends on the size and shape of the other pattern prohibited area.
For example, it is preferable that the area is set so as to surround this area with a width of about 1 μm or more from the outer periphery of the other pattern prohibited area, or to surround this area with a size of about 10% of the other pattern prohibited area.

The metal wiring layer disposed below the outer peripheral region of the other pattern prohibition region is lower than the metal wiring layer forming the misalignment measurement mark, preferably, a layer immediately below the metal wiring layer forming the mark. It is preferred that The metal wiring layer may be a metal wiring layer that forms an electrode or a wiring layer in a circuit below the alignment deviation measurement mark, a so-called dummy wiring layer, or a floating wiring layer. It is preferable that the metal wiring layers arranged below the outer peripheral area of the other pattern prohibited area are arranged regularly and in an island shape below the outer peripheral area of the other pattern prohibited area. The shape of the island here is not particularly limited,
A shape that integrally surrounds the outer periphery of the other pattern prohibition region may be used, or a shape similar to that exemplified as the shape of the alignment deviation measurement mark may be used. The size is preferably, for example, about 1 to 100 μm ² , particularly about 1 μm × 1 μm to 10 μm × 10 μm in the case of a square shape. Preferably, a plurality of islands are arranged in the outer peripheral region of the alignment deviation measurement mark.

To be regularly arranged means that islands having the same shape and the same size are arranged at the same interval. Specifically, in the case of the shape and size as exemplified above, it is preferable that the islands are regularly arranged at intervals of about 2 to 20 μm. in this way,
If the island is smaller than the misalignment measurement mark and regularly surrounds the periphery of the other pattern prohibited area,
This is because the parasitic capacitance formed by these metal wiring layers can be reduced as compared with a shape in which the metal wiring layers are integrally surrounded.

The method for controlling the misalignment according to the present invention comprises:
In a manufacturing process of a semiconductor device, a method is used in which a misalignment measurement mark is used to accurately measure a misalignment of an object to be aligned on an upper layer and to control the misalignment. Specifically, in a semiconductor device manufacturing process, a resist layer is formed by a photolithography step on a semiconductor substrate on which the above-described misalignment measurement marks are formed, and a misalignment inspection pattern having a predetermined shape is formed. After exposing and developing a desired mask shape including the resist pattern on the resist layer, the position of the alignment measurement mark is recognized by an optical signal output. At the same time, the position of the misalignment inspection pattern formed on the resist layer is similarly recognized. Then, the two positions are compared, for example, by detecting the difference between the coordinates of the center point of the alignment deviation measurement mark and the alignment deviation inspection mark, to determine whether there is any deviation in the alignment of the mask shape with this resist layer. Measure for any deviation.

If the misalignment is detected to a degree that causes a circuit operation failure or the like, the resist layer is removed, a resist layer is formed again, and position correction is performed based on the detected misalignment value to perform patterning. Then, similarly to the above, it is measured whether or not an alignment shift has occurred.
Thereby, the misalignment in the photolithography process can be minimized.

In the present invention, the misalignment measurement mark can be used not only for the misalignment measurement, but also as an alignment mark in a photolithography process in a layer above the mark. This mark may be formed in advance and used for alignment of the metal wiring layer in the same layer based on the mark.

Hereinafter, a semiconductor device and a method of controlling an alignment deviation according to the present invention will be described with reference to the drawings.

The semiconductor device of this embodiment is similar to that of FIG.
As shown in (a) and (b), the lower metal wiring layer 11a is provided in the circuit region I on the interlayer insulating film 10 and the lower metal wiring layer 11b is provided in the region II other than the other pattern prohibited region III and the circuit region I. Are formed, and no metal wiring layer is formed below the other pattern prohibition region III corresponding to the region where the misalignment measurement mark will be formed later.
On the lower metal wiring layers 11a and 11b, the lower metal wiring layer 13
As for a, the misalignment measurement mark 13b is formed in the other pattern prohibited area III.

The lower wiring layer 11b is regularly arranged in an island shape in the outer peripheral region of the other pattern prohibition region III.

The semiconductor device as described above can be manufactured by the following method.

First, a metal film having a thickness of about 5000 ° is formed on the interlayer insulating film 10 by a sputtering method, and the metal film is patterned into the lower metal wiring layer 11a in the circuit region I by a photolithography and dry etching process. I do. At this time, the circuit area I and the other pattern prohibited area
In the region II other than the region III, a shape that can be stably processed, for example, L / W = about 4 μm / 4 μm and the lower metal wiring layer 11
b is formed. It should be noted that no metal wiring layer is formed below the other pattern prohibition region III.

Next, an interlayer insulating film 12 having a thickness of about 15000 ° is deposited, and then flattened by a CMP method. At this time, the area II which is the outer peripheral area of the other pattern prohibited area III
Also, since the lower metal wiring layer 11b is arranged,
The thinning of the interlayer insulating film 12 due to dishing due to the absence of the metal wiring layer in the region below the other pattern prohibited region III can be avoided.

Further, a metal film having a thickness of about 5000 ° is formed on the interlayer insulating film 12 by a sputtering method, and the metal film is patterned into an upper metal wiring layer 13a in the circuit region I by a photolithography and dry etching process. At the same time, in the other pattern prohibition region III, for example, the alignment deviation measurement mark 13b having a size of about L / W = 25 μm / 25 μm is formed. At this time, even in the circuit region I near the other pattern prohibition region III, since the thickness of the interlayer insulating film 12 is kept uniform with the other regions, the formation failure of the upper wiring layer 13a does not occur.

Subsequently, an interlayer insulating film 14 having a thickness of about 15000 ° is deposited, and the surface of the interlayer insulating film 14 is planarized by the CMP method.

Next, the resist layer 1 is formed on the interlayer insulating film 14.
5, an opening (not shown) for forming a via hole in the interlayer insulating film 14 in the circuit region I, and an alignment on the misalignment measurement mark 13b in the resist layer 15 by photolithography and dry etching processes. A mark 16 for displacement inspection is formed. Thereafter, the coordinates of the center point of the alignment deviation measurement mark 13b are detected using a commercially available automatic measurement device for alignment deviation inspection, and the alignment deviation inspection mark 16 of the resist layer 15 is used as a vernier scale. The coordinates of the midpoint are detected, and the alignment deviation is determined from the difference between the two coordinates. At this time, the alignment deviation measurement mark 13b
Since no metal wiring is formed behind (below) the position of the misalignment measurement mark 13b can be accurately detected, and the misalignment can be measured with high accuracy.

That is, if the misalignment is detected to a degree that causes a circuit operation failure, for example, 0.05 μm to 0.2 μm or more, the resist layer 15 is removed, and the resist layer is removed again. Formed, patterning is performed by performing position correction based on the detected misalignment value, similarly, the coordinates of the midpoint are detected using the misalignment measurement mark 13b as a main scale, and furthermore, misalignment of the resist layer 15 is detected. Using the inspection mark 16 as a vernier scale, the coordinates of the midpoint are detected, the alignment deviation is determined from the difference between the two coordinates, and this is repeated until the alignment deviation is tolerable.
The misalignment in the photolithography process for forming a via hole can be reduced.

[0039]

According to the present invention, the misalignment measuring mark formed of either the second layer or the metal wiring layer above the second layer is formed in the other pattern prohibited area, and the lower mark in the other pattern prohibited area is formed. Since the metal wiring layer is removed in the above, it is easy to detect the boundary of the alignment deviation measurement mark, and the alignment deviation in the photolithography process can be measured with high accuracy.

In particular, since the metal wiring layer lower than the metal wiring layer forming the misalignment measurement mark is arranged below the outer peripheral area of the other pattern prohibition area, the metallization layer is arranged above and below the misalignment measurement mark. It is possible to prevent thinning due to dishing of the inter-layer insulating film to be arranged, suppress a focus shift during exposure in photolithography, prevent a pattern formation failure of a metal wiring layer in a circuit, and improve reliability. A high semiconductor device can be provided.

[Brief description of the drawings]

FIGS. 1A and 1B are a schematic plan view of a main part and a schematic cross-sectional view of a main part, for explaining an embodiment of a semiconductor device of the present invention.

2A and 2B are a schematic plan view of a main part and a schematic cross-sectional view of a main part, for explaining an example of a conventional semiconductor device.

FIG. 3 is a schematic plan view of a main part for describing another embodiment of a conventional semiconductor device.

[Explanation of symbols]

 10, 13, 14 Interlayer insulating film 11a, 11b Lower metal wiring layer 13a Upper gold image wiring layer 13b Alignment misalignment measurement mark 15 Resist layer 16 Alignment misalignment inspection mark I Circuit area II Other than circuit area and other pattern prohibited area Area III Other pattern prohibited area

Continued on front page F-term (reference)

Claims (4)

[Claims] 1. A multilayer wiring structure comprising a plurality of metal wiring layers formed on a semiconductor substrate and an interlayer insulating film disposed between the metal wiring layers, and formed by a second or higher metal wiring layer. A semiconductor device having a misalignment measurement mark formed therein, wherein the misalignment measurement mark is formed in another pattern prohibited area, and a metal wiring layer is removed below the other pattern prohibited area. apparatus. 2. The semiconductor device according to claim 1, wherein a metal wiring layer lower than a metal wiring layer forming the misalignment measurement mark is arranged below an outer peripheral region of the other pattern prohibition region. 3. The semiconductor device according to claim 2, wherein the lower metal wirings are arranged regularly and in an island shape below an outer peripheral region of the other pattern prohibited region. 4. A semiconductor device according to claim 1, wherein the position of the alignment deviation measurement mark is recognized by an optical signal output, and the alignment deviation in a photolithography process is determined based on the position of the alignment deviation measurement mark. A method for controlling an alignment deviation, which comprises controlling the alignment.