TWI703701B - Wafer having mini identification mark and forming method of identification mark - Google Patents

Abstract

A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.

Description

Semiconductor wafer with miniature identification mark and method for forming identification mark

The embodiment of the present invention relates to a semiconductor wafer with a miniature identification mark and a method for forming the identification mark.

Semiconductor fabrication facilities (fab) are factories that manufacture integrated wafers. By using multiple processing steps (such as etching steps, patterning steps, deposition steps, implantation steps, etc.) to manipulate semiconductor wafers to form millions or billions of semiconductor components on and in the semiconductor wafer To perform the manufacturing of integrated wafers. The semiconductor wafer is then divided to form a plurality of integrated wafers from a single wafer. Semiconductor manufacturing facilities often have a throughput rate of thousands of wafers a month. Due to processing changes, the quality of different wafers may vary. Therefore, in order to track the wafers and their associated wafers through the manufacturing process, an identification mark that uniquely identifies the wafer is formed on each wafer. The identification mark promotes the traceability of the wafer in the manufacturing and testing process.

A semiconductor wafer according to an embodiment of the present invention includes a first surface with a first center, a second surface with a second center, alignment notches arranged along the circumferential edge, a die area, and a series of The first identification mark of a character. The first center and the second center are each arranged on a center axis of the semiconductor wafer passing through the first surface and the second surface, and the first surface and the second surface Adjacent to each other at the circumferential edge. The alignment notch extends inward from the circumferential edge by a radial distance of the alignment notch, and the radial distance of the alignment notch is smaller than a wafer radius measured from the first center to the circumferential edge. The crystal grain area includes an array of crystal grains arranged on the first surface in columns and rows and is bounded by a non-crystal grain area without crystal grains on the circumference. The first identification mark is completely arranged in the die-free area, facing the first side of the alignment notch.

A semiconductor wafer with a circumferential edge according to an embodiment of the present invention includes a die area, an alignment notch, a first identification mark and a second identification mark. The crystal grain area includes an array of crystal grains arranged in columns and rows and is bounded by a non-crystal grain area without crystal grains on the circumference, wherein the substantially circular crystal grain area edge connects the crystal grain area and the crystal grain area. Said no grain area separation. The alignment notch is arranged along the circumferential edge of the semiconductor wafer, and the alignment notch extends inwardly from the circumferential edge by a radial distance of the alignment notch. The first identification mark is completely arranged in the die-free area, facing the first side of the alignment notch. The second identification mark is completely arranged in the die-free area, facing the second side of the alignment notch.

An identification mark forming method according to an embodiment of the present invention includes the following steps. Receive semiconductor wafers. A first identification mark is formed on the front side of the semiconductor wafer or on a layer above the front side of the semiconductor wafer. At least one dielectric layer and at least one conductive layer are formed above the semiconductor wafer and above the first identification mark. After the at least one dielectric layer and the at least one conductive layer have been formed, it is determined whether the first identification mark is readable. Based on whether the first identification mark is readable, a second identification mark is selectively formed in or on the at least one dielectric layer and the at least one conductive layer.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these components and arrangements are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed on the first feature An embodiment is formed with the second feature such that the first feature and the second feature may not directly contact. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatial relative terms, such as "below", "below", "lower", "above", "upper" and the like are used in this article to describe as shown in the figure. Describe the relationship between one or more elements or features and another element or feature. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article can also be interpreted accordingly.

The identification mark is often formed in the semiconductor wafer before the semiconductor element is formed, and is used as a device to identify the wafer when the wafer moves through the manufacturing facility. In a typical process of forming identification marks, the surface of a semiconductor wafer is etched, burned, imprinted or otherwise patterned with identification marks. In some embodiments, the identification mark can be placed directly on the upper surface of the semiconductor wafer, while in other embodiments, the identification mark can be placed on the dielectric layer directly above the upper surface of the semiconductor wafer (such as two Silicon oxide layer) on the upper surface. The openings or recesses in the upper surface of the semiconductor wafer and/or the dielectric layer thus correspond to the identification marks. The openings or recesses may be formed, for example, by focusing or pulsed laser beams in a mode that penetrates the surface of the semiconductor wafer and/or the dielectric layer to form a plurality of discrete pits in the shape of identification marks. For example, the previous identification mark is 14 millimeters (mm) wide and 16 millimeters high, and therefore covers an area of 22.4 square millimeters on the wafer surface, and is spaced directly above the wafer notch so that the identification The notch is centered above the alignment notch. In addition, in some cases when the wafer identification mark is degraded and/or unreadable (for example, due to the peeling of photoresist and/or other features near the edge of the wafer), it can be directly above the first wafer identification mark A second wafer mark that is also 14 mm wide and 16 mm high is formed.

These conventional identification marks are too large in many respects, and therefore, this disclosure is about miniature identification marks, the size and arrangement of which are very suitable for increasing the number of dies per wafer, while outsourcing assembly and testing to manufacturing facilities and The (outsourced assembly and test; OSAT) facility provides identification marks in an easily accessible/readable position on the wafer. Furthermore, in some cases, the micro-identification marks are arranged sufficiently close to the edge of the wafer so that peeling is not a problem, which is advantageous in some embodiments.

FIG. 1 illustrates a semiconductor wafer 100 according to some embodiments. The semiconductor wafer 100 includes a first side 102 with a first center 102c and a second side 104 with a second center (not visible). The central axis 105 of the semiconductor wafer 100 passes through the first surface 102 at the first center 102c and passes through the second surface 104 at the second center. The first surface 102 and the second surface 104 adjoin each other at a circumferential edge 106 which is circular only when the alignment notch 108 is present. The alignment notch 108 is provided at a position along the circumferential edge 106 of the wafer. The alignment notch 108 extends inwardly from the circumferential edge 106 by a radial distance of the alignment notch. In some embodiments, the radial distance of the alignment notch is less than 10% of the wafer radius as measured from the first center 102c to the circumferential edge 106. In some embodiments, the alignment notch 108 has a rounded edge, wherein the innermost curved area of the rounded edge corresponds to the innermost point (for example, a circular shape), while in other embodiments, the alignment The notch has two linear or planar surfaces that meet at the innermost point of the aligned notch (for example, a triangle or a pie shape). In some embodiments, the die region edge 114 is spaced apart from the innermost tip of the alignment recess 108, so that the die region edge 114 is spaced from the circumferential edge 106 in the radial direction slightly less than the alignment recess radial direction. The distance is within five times the radial distance of the alignment notch.

Referring now to FIGS. 1 and 2 at the same time, FIG. 2 illustrates a top view of the semiconductor wafer 100 consistent with FIG. 1. We can see that the semiconductor wafer 100 includes a central die region 110, which is formed on the circumference by not containing crystals. The grain-free region 112 is delimited. As illustrated in FIG. 2, the die region 110 includes an array of individual die 116 arranged in columns and rows. The individual dies 116 are separated from each other by the dicing lane 118, and the wafer 100 is subsequently singulated (eg, diced or divided) into individual dies along the dicing lane 118. In FIG. 2 for simplicity and clarity, only three individual dies 116 and three dicing lanes 118 are marked, but it should be understood that there are additional dies and dicing lanes. Each individual die 116 includes a functional circuit, which usually includes semiconductor elements, such as diodes, resistors, capacitors, memory cells, and/or transistors (eg, metal oxide semiconductor field effect transistors). transistors; MOSFET), bipolar junction transistors (BJT), fin field effect transistor (FINFET), etc.). The scribe lane 118 may contain no functional circuits and/or may include test structures or test circuits that are usually removed by singulation before the final integrated circuit is divided and sold.

The substantially circular die region edge 114 separates the die region 110 from the non-die region 112.

As can be seen from the section line II' of FIG. 2 and FIG. 3 depicting a cross-sectional view of the wafer 100, the die-free region 112 includes a roll-off in which the first surface 102 and the second surface 104 are inclined to abut the circumferential edge 106 Area 124.

The wafer edge exposed area 126 separates the roll-off area 124 from the die area 110. Because when the photoresist is coated (for example, spin-coated) on the first side 102 of the wafer during manufacturing, the outermost peripheral edge of the photoresist is often thicker than the central area of the photoresist (which can cause focusing during lithography Problems and/or other problems), so an exposed area 126 at the edge of the wafer is generated. Therefore, it is expected that the wafer edge exposed area 126 that covers any area of the "thicker" photoresist is processed by, for example, a separate radiation treatment that is not applied to the central area of the photoresist to remove and/or modify the thicker light. The thickness of the resistance and thus improve the yield of the wafer. In some embodiments, the circular die area edge 114 is spaced from the circumferential edge 106 by approximately 3 mm in the radial direction, so as to provide sufficient spacing for the wafer edge exposed area 126 and the roll-off area 124.

The first identification mark 120 is completely disposed in the die-free area 112 and faces the first side of the alignment notch 108. In contrast to the conventional method of placing the identification mark of the wafer on the y-axis 134 (see the hash area 132) directly above the alignment notch 108, the first identification mark 120 is offset relative to the alignment notch 108 And its size is smaller than the conventional identification mark, so the available size of the die area 110 is increased compared with the conventional method. Therefore, in some embodiments, since the conventional method may include the identification mark between the innermost top of the alignment notch 108 and the center of the first surface, the semiconductor wafer 100 exhibits the top of the alignment notch 108. There is no identification mark between the inner top and the bottom edge of a column of the die in the die region 110 (for example, the semiconductor wafer 100 exhibits no identification mark between the innermost top of the alignment recess 108 and the center of the first surface Identification mark). Alternatively, the identification mark can be reduced in size compared to the conventional method, and can be placed between the innermost top of the alignment notch 108 and the bottom edge of a row of dies, as long as the reduced identification mark does not intersect the die area 110 Just stack up.

The first identification mark 120 can also avoid overlapping with the roll-off area 124 (and/or crossing the boundary between the roll-off area 124 and the wafer edge exposed area 126), because the first identification mark 120 may be formed in the roll-off area This may cause laser defocusing problems or other problems that may cause illegibility of parts of the first identification mark 120.

For example, consider the case of a conventional 200 mm wafer, where the conventional identification mark is 22 mm wide and 1.84 mm high, and is arranged such that the center axis of the conventional 200 mm wafer is aligned along the Position the y-axis directly above the notch (see hash area 132). Due to this arrangement, the central die area may have the lowest edge that is 9 mm apart from the circumferential edge of the wafer under the alignment notch. In contrast, the first identification mark 120 is 4 mm wide by 0.6 mm high and is arranged to be offset from the y-axis 134 and the alignment notch 108 and move in the y direction to a 200 mm crystal closer to the circumferential edge 106 In the case of a circle, the die region 110 can now extend relative to the conventional arrangement, so the lowest edge of the die region 110 is now only 3 mm away from the circumferential edge of the wafer. This provides a small but important increase in the die area (and corresponding die yield) of the wafer 100, which increases the value of each wafer in a meaningful way.

As another example, consider the case of a conventional 300 mm wafer, where the conventional identification mark is 14 meters wide and 1.6 mm high, and is arranged such that the center axis of the conventional 300 mm wafer is aligned The y-axis positioning directly above the quasi-notch. Due to this arrangement, the die region 110 may have the lowest edge that is spaced 7.75 mm from the circumferential edge of the wafer. In contrast, the first identification mark 120 is 4 mm wide by 0.6 mm high and is arranged to be offset from the y-axis 134 and the alignment notch 108 and move in the y direction to a 300 mm crystal that is closer to the circumferential edge 106 In the case of a circle, the die region 110 can now extend relative to the conventional arrangement, so the lowest edge of the die region 110 is now only 3 mm away from the circumferential edge of the wafer. This provides a small but important increase in the die area of the wafer (and the corresponding die yield), which increases the value of each wafer in a meaningful way.

In some embodiments, the second identification mark 122 that is also completely disposed in the die-free region 112 is disposed toward the second side of the alignment notch 108. In some embodiments, such as the one shown in FIG. 2, the second identification mark 122 may be formed at a higher level than the first identification mark 120 (for example, formed in the back-end-of-line process). ; BEOL) in the metallization structure 166 or formed in the passivation layer 168 above the BEOL metallization structure). In some embodiments, the positions of the first identification mark 120 and the second identification mark 122 are symmetrical to the y-axis 134. However, in other embodiments, the positions of the first identification mark 120 and the second identification mark 122 are symmetrical to the x-axis 136, and/or not symmetrical to the y-axis 134, and/or not symmetrical to the x-axis 136. More than two identification marks can also be completely disposed in the non-crystalline area 112.

For example, in many examples, the diameter of the semiconductor wafer 100 can be 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm) ) Or 125 mm (4.9 inches); 150 mm (5.9 inches, usually called "6 inches"); 200 mm (7.9 inches, usually called “8 inches”); 300 mm (11.8 inches, usually called "12 inches"); or 450 mm (17.7 inches, usually referred to as "18 inches"). In some embodiments, the semiconductor wafer 100 is a monocrystalline silicon bulk substrate, but in other embodiments, the semiconductor wafer may be made of group III elements and/or group V elements (such as GaAs, InGaAs, etc.). In still other embodiments, the semiconductor wafer 100 is a semiconductor-on-insulator (SOI) substrate, which includes a handle substrate and epitaxial growth vertically stacked on opposite sides of the insulating layer Component layer. The processing substrate and the device layer include, for example, single crystal silicon and/or group III elements and/or group V elements; and the insulating layer includes dielectric materials such as silicon nitride, silicon dioxide or silicon oxynitride; and epitaxial growth The device layer includes semiconductor materials, such as single crystal silicon and/or group III elements and/or group V elements.

FIG. 4 illustrates an example of the first identification mark 120 according to some embodiments. The first identification mark 120 is bounded by an outer periphery 150 and has a first width w ₁ in the plane of the first face 102 and a first height h ₁ in the plane of the first face 102. In some embodiments, the first width w ₁ is within a range between 3 millimeters (mm) and 5 millimeters, and the first height h ₁ is within a range between 0.25 millimeters and 0.75 millimeters. The first identification mark 120 includes a plurality of first characters. For example, in FIG. 4, the first identification mark 120 is in the form of an alphanumeric string, which consists of the following: a first group of six alphanumeric characters 152, followed by a dash 154, and then The second set of four alphanumeric characters is 156.

FIG. 5 illustrates an example of the second identification mark 122 according to some embodiments. The second identification mark 122 is bounded by a second outer periphery 158 having a second width w ₂ in the plane of the first face 102 and a second height h ₂ in the plane of the first face 102. In some embodiments, the width w _{2 of the} second identification mark is within a range between 3 millimeters (mm) and 5 millimeters, and the height h _{2 of the} second identification mark is within a range between 0.25 mm and 0.75 mm. The second identification mark includes a plurality of second alphanumeric characters, which in some embodiments may consist of the following: a first group of six alphanumeric characters 160, followed by a dash 162, and then a second group of four alphanumeric characters 164. The alphanumeric value of a plurality of first alphanumeric characters is often the same as that of a plurality of second alphanumeric characters, but in other embodiments, the alphanumeric element values may be different. In addition, the length of the outer periphery of the first identification mark is generally equal to the length of the outer periphery of the second identification mark, but in other embodiments, the length of the periphery may be different.

It should be understood that although the first outer periphery 150 and the second outer periphery 158 are illustrated as lines surrounding the first identification mark 120 and the second identification mark 122 in the drawings, in a typical embodiment, the outer periphery is merely a concept A geometric or virtual structure, which connects the edges of the text element and does not actually stamp on the surface of the wafer.

As illustrated in FIG. 6A, in some embodiments, the first identification mark 120 includes a plurality of first alphanumeric characters whose outermost edges fall on the periphery 602 of the first rectangle. The first center point in the first rectangular periphery 602 is located on the first radial axis 604 passing through the first center 102c, and is parallel to the first tangent line segment intersecting the first radial axis 604 at the circumferential edge 106 The first line 606 of 608 passes through the respective centers of the plurality of first alphanumeric elements and intersects the first center point.

The second identification mark 122 includes a plurality of second alphanumeric characters whose outermost edge falls on the second rectangular periphery 610. The second center point in the second rectangular periphery 610 is located on the second radial axis 612 passing through the second center and is parallel to the second tangent segment 616 that intersects the second radial axis 612 at the circumferential edge 106 The second line 614 passes through the respective centers of the plurality of second alphanumeric characters and intersects the second center point. The angle θ ₁ and angle θ ₂ from the y-axis 134 (passing through the center of the alignment notch 108) to the first radial axis 604 and the second radial axis 612 are respectively measured. In some embodiments, θ ₁ and θ ₂ are equal, but in other embodiments, θ ₁ and θ ₂ may be different. In some embodiments, θ ₁ and/or θ _{2 are} within a range between 3 degrees and about 30 degrees, which keeps the first identification mark 120 and the second identification mark 122 very close to the alignment notch 108.

6B illustrates another embodiment in which the first identification mark 120a and the second identification mark 122a are far apart from the notch 108. For example, in some embodiments, the center of the first identification mark 120a is positioned along the first radial axis 604a and is radially offset from the notch 108 by an angle θ _1a , where θ _{1a is} between -90 ^° and -180 ^In the range between ^° and in some cases approximately -135 ^° . The center of the second identification mark 122a is positioned along the second radial axis 612a and is radially offset with respect to the notch 108 by an angle θ _2a , where θ _{2a is} in the range between +90 ^° and +180 ^° and in some cases The bottom is approximately +135 ^° .

In addition, as shown in FIG. 6C (which is an enlarged view of area A in FIG. 6B), the center of the first identification mark 120a may be relative to the outermost edge of the outermost die 116 in the central die region 110. The defined corner (or notch) is centered. Therefore, in FIG. 6C, the corner is a right angle, which is defined by the edge 116' and the edge 116", and the first radial axis 604a bisects the right angle. Therefore, the first identification mark 120a whose characters are located on the first line 606 is also equally divided by the first radial axis, so that the first identification mark 120a extends relative to either side of the first radial axis 604a. The distance is equal. It should be noted that this configuration and the other configurations described in this article can be used for wafers of any size.

FIG. 7 shows another arrangement of the first identification mark 120 and the second identification mark 122. As illustrated in FIG. 7, the first axis (for example, the x-axis 136) extends along the first surface 102 and passes through the first center 102c, and the second axis (for example, the y-axis 134) extends along the first surface 102 and passes through the first center. One center 102c. The second axis is perpendicular to the first axis. The first identification mark 120 has a first rectangular perimeter 702 that has a first set of edges (edges 704a, 704b) running parallel to a first axis (for example, the x-axis 136) and parallel to A second set of edges (edges 706a, 706b) along which the second axis (for example, y-axis 134) extends, wherein the first edge in the second set of edges and the second axis (for example, y-axis 134) are separated by a first distance.

The second identification mark 122 has a second rectangular periphery 708 with a first set of edges (edges 710a, 710b) extending parallel to the first axis (for example, the x-axis 136) and parallel to the second axis A second set of edges (edges 712a, 712b) extending (eg, y-axis 134), wherein the first edge in the second set of edges is separated from the second axis (eg, y-axis 134) by a second distance. The second distance is often equal to the first distance, but can also be different from the first distance. In many embodiments consistent with FIG. 7, a column of die in the die region has a bottom edge arranged parallel to the first set of edges 704a, 704b, 710a, 710b. In some cases, the first distance is less than the minimum width of the first identification mark 120, as measured between the edges of the second set.

In addition, in some embodiments, such as illustrated by the alternate positions of the first identification mark 720 and the second identification mark 722, a tangent segment 724 to the first surface 102 exists between the circumferential edge 106 at the alignment notch 108 Virtual extension 726. A line 728 parallel to the tangent segment 724 passes through each of the alignment notch 108, the first identification mark 720 and the second identification mark 722. Similar alternate positions can be applied to the embodiment of FIG. 6A and other embodiments disclosed herein.

FIGS. 8A to 8B to FIGS. 11A to 11B illustrate the sample manufacturing process, which can be particularly consistent with, for example, part of the 200 mm wafer manufacturing process. 8B, 9B, 10B, and 11B depict the cross-sectional portion of the wafer along the section line I-I' in FIGS. 8A, 9A, 10A, and 11A, respectively.

In FIGS. 8A to 8B, the manufacturing process starts with the semiconductor wafer 100.

In FIGS. 9A to 9B, the first identification mark 120 is formed on the front side of the wafer 100. During the typical process of forming the first identification mark 120, the surface of the semiconductor wafer is etched, burned, embossed or otherwise patterned with the first identification mark 120. In some embodiments, the first identification mark 120 may be directly placed on the upper surface of the semiconductor wafer 100, while in other embodiments, the identification mark may be placed on the dielectric directly above the upper surface of the semiconductor wafer. Layer (eg silicon dioxide layer) on the upper surface. The openings or recesses in the upper surface of the semiconductor wafer and/or the dielectric layer thus correspond to the first identification mark. The openings or recesses can be formed, for example, by focusing or pulsed laser beams in a mode that penetrates the surface of the semiconductor wafer and/or the dielectric layer to form a plurality of the first identification marks 120 in common. Discrete pits. In other embodiments, the photoresist layer can be spin-coated and patterned to have an opening corresponding to the shape of the identification mark and have a photoresist pattern at an appropriate position, and can be etched to imprint the first identification mark on the semiconductor crystal. In the upper surface of circle 100. In other embodiments, other techniques (such as electron beam writing or die stamping, among others) may be used to form the first identification mark 120.

In FIGS. 10A to 10B, device features (such as transistor structures including gate 1002, source/drain regions 1004) and BEOL metallization structures 166 (such as metal layers and extending through interlayer dielectrics; ILD) layer vias) are formed above the semiconductor wafer 100. In some cases, the first identification mark 120 naturally carries the surface contours of one layer up to the next layer without the first identification mark 120 being newly formed on the upper layer. The first identification mark 120 can be checked at each layer, and if the first identification mark 120 becomes unrecognizable or is expected to become unrecognizable (due to the thickness of the next layer or other characteristics of one or more layers), it is visible The situation forms a supplementary identification mark (for example, the second identification mark 122).

In FIGS. 11A to 11B, the passivation layer 168 is formed on the semiconductor wafer 100, in which the first identification mark and/or the second identification mark 122 (supplementary identification mark), which may also be called the main identification mark, are formed on the passivation layer 168 It is still visible on the upper surface. The passivation layer 168 may include epoxy, silicon nitride, and/or ceramic materials.

FIG. 12 shows a flowchart consistent with some embodiments of the manufacturing process illustrated in FIGS. 8A to 8B to 11A to 11B.

At step 1202, a semiconductor wafer is received. In some embodiments, N layers including at least one dielectric layer, at least one conductive layer, and at least one semiconductor layer will be formed on the semiconductor wafer. In the flowchart of Figure 12, the index variable (i) is initialized to one (i=1) and will be updated during the manufacturing process to track each layer as it is formed. 8A to 8B show examples of some ways in which step 1202 can be implemented.

At step 1204, a first identification mark is formed on the front side of the wafer or a layer above the front side of the wafer. For example, the first identification mark may be directly imprinted on the front side of the wafer, or may be directly imprinted on the dielectric layer (such as the SiO ₂ layer) directly above the front side of the wafer. The first identification mark can be expressed in various forms, but in a typical embodiment, the first identification mark 120 is expressed in the form of a string of letters and numbers composed of a predetermined number of letters and/or numbers. For example, in some cases, the first identification mark consists of the following: a first group of six alphanumeric characters, followed by a dash, and then a second group of four alphanumeric characters. In some embodiments, the first identification mark is formed by pulsing a laser to form a plurality of first discrete pits, wherein the plurality of first discrete pits jointly create a first identification mark corresponding to the first A series of characters and figures. 9A-9B show examples of some ways in which step 1204 may be implemented.

At step 1206, at least one dielectric layer and/or at least one conductive layer and at least one optional semiconductor layer are formed above the semiconductor wafer and above the first identification mark. These layers help build one or more semiconductor components (such as transistors) and/or back-end-of-line (BEOL) metallization structures on the front side of the wafer. 10A to 10B show examples of some ways in which step 1206 may be implemented.

More precisely, in step 1206, at step 1208, the i-th layer (for example, the first time through step 1206, i=1, and the i-th layer is the first layer; and for the second time through step 1206, i=2 and the i-th layer is the second layer; etc.) is formed on the wafer. At step 1210, the method determines whether the first identification mark is still readable/identifiable from above the first layer. The method can make this determination by optical devices, such as acquiring a digital image from above the first layer and determining whether the edges of characters or other signs are sufficiently obvious to distinguish the value of the characters. In other embodiments, instead of acquiring the actual image, the method has been programmed to anticipate that the character value will become indistinguishable at a certain predetermined level. For example, the method can determine that the metal 3 BEOL metal layer or the ILD4 layer will make the characters indistinguishable based on the experimental results and/or the modeling results of the previous manufacturing facility sample. If the identification mark is no longer discernible due to the formation of the i-th layer (ie, no at step 1210), the method proceeds to step 1212 and a second identification mark is formed on the i-th layer. On the other hand, if the identification mark is still discernible after the formation of the i-th layer (that is, yes at step 1210), the method continues to step 1214 and a determination is made whether all layers have been processed ( Is it i>N?). If there are still layers to be processed (ie, no at step 1214), i is incremented (i=i+1), and the method returns to step 1208 and the next layer is formed on the wafer. Each layer is evaluated to determine whether its formation caused (and/or whether it is expected that the imminent formation will cause) the identification mark is not discernible, and if so, a second identification mark can be formed when the determination is made.

If all layers have been processed (ie, yes at step 1214), then the method proceeds to step 1218 and a passivation layer is formed over the structure. 11A-11B show examples of some ways in which step 1218 may be implemented.

At step 1220, after the passivation layer has been formed, the processed wafer for testing can be sent out, and finally the wafer is singulated into individual dies that are packaged and sold.

13A to 13D to 16A to 16C illustrate a sample manufacturing process, such as a 300mm wafer manufacturing process. Figures 13A, 14A, 15A, and 16A depict the front side of the wafer, Figures 13B, 14B, 15B, and 16B depict the back side of the wafer, and Figures 13C, 14C, 15C, and 16C are respectively along the view 13A, FIG. 14A, FIG. 15A, and FIG. 16A depict a cross-sectional portion of the wafer through the section line II', and FIG. 13D is a partial enlarged view of FIG. 13B.

In FIGS. 13A to 13D, the method starts with a semiconductor wafer 100. In some cases, when received from a wafer manufacturer, the wafer already contains a two-dimensional matrix code symbol 1302 on the back side of the wafer and a separate substrate identification code 1304 on the back side of the wafer . The two-dimensional matrix code symbol 1302, which may be composed of, for example, an array of dot positions of thirty-two dots wide and eight dots high may be added by the wafer manufacturer (for example, before distribution to a semiconductor manufacturing facility). The two-dimensional matrix code symbol 1302 does not actually appear in the form of alphanumeric elements, but can specify information such as the following: whether the substrate is P-type or N-type, the resistivity of the substrate, and the ingots that generate individual wafers (ingot) ID, the unique individual identification mark in the ingot and the name of the wafer manufacturer, and other information. The two-dimensional matrix code symbol 1302 can be formed by laser, etching process, electron beam writing, ink printing, die stamping, or sticking pre-made identification marks on paper or plastic labels, among others. The base identification code 1304 may be composed of twelve alphanumeric elements, and each of the twelve alphanumeric elements is composed of a dot position array of nine dots high and five dots wide. In some embodiments, the base identification code 1304 may contain the same information as the two-dimensional matrix code symbol 1302, wherein the base identification code 1304 is in a self-font format and the two-dimensional matrix code symbol 1302 is in a 2D matrix code format. The substrate identification code 1304 can be formed by laser, etching process, electron beam writing, ink printing, die stamping, or sticking prefabricated identification marks on paper or plastic labels, and other forms; and can be combined with two-dimensional matrix code symbols 1302 The same or different technology is formed.

In FIGS. 14A to 14C, the element features and the BEOL metallization structure 166 are formed above the front side of the wafer, where the two-dimensional matrix code symbol 1302 and the substrate identification code 1304 are still visible on the back side of the wafer. Since each layer is formed to establish device features and BEOL metallization structure 166, the substrate identification code 1304 is read from the backside of the wafer by a processing tool.

In FIGS. 15A to 15C, the passivation layer 168 is formed on the wafer, and the two-dimensional matrix code symbol 1302 and the substrate identification code 1304 are still visible on the back side of the wafer. A supplementary identification mark 122 visible from the front side of the wafer is formed in the upper surface of the passivation layer 168. The supplementary identification mark 122 may include a series of alphanumeric elements, for example, as previously described in FIGS. 4 to 5, and the value of the alphanumeric element of the supplementary identification mark 122 is usually different from that of the base identification code 1304. However, the supplementary identification mark 122 is usually related to the base identification code 1304 in the computer database maintained by the manufacturer, so these identifiers are related to each other.

In Figures 16A to 16C, the wafers are sent to another facility for outsourced assembly and testing (OSAT). In OSAT, the back side of the wafer is polished to reduce the thickness of the wafer and the two-dimensional matrix code symbol 1302 and the base identification code 1304 are removed. The supplementary identification mark 122 continues to be effective for OSAT. The OSAT facility uses supplementary identification marks 122 visible from the passivation layer to perform die testing and/or packaging.

FIG. 17 shows a flowchart consistent with some embodiments of the manufacturing process described in FIGS. 13A to 13B to 16A to 16B.

At step 1702, a semiconductor wafer on which N layers will be formed is received. The wafer has a 2D matrix code symbol and a separate backside identification mark on the backside of the wafer. In the flowchart of FIG. 17, the subscript variable (i) is initialized to one (i=1) and will be updated during the manufacturing process to track each layer as it is formed. 13A to 13D show examples of some ways in which step 1702 can be implemented.

At step 1704, a continuous layer of semiconductor, conductive material (such as metal or doped polysilicon), and/or dielectric is formed on the semiconductor wafer to use the components on the semiconductor wafer. 14A to 14C show examples of some ways in which step 1704 can be implemented. For each layer, the process forms the i-th layer (step 1706), evaluates whether all layers have been formed (step 1708), and moves to form another layer by incrementing i (step 1710), or when all layers have been processed, A passivation layer is formed over the structure (step 1712). 15A-15C show examples of some ways in which step 1712 may be implemented.

After the passivation layer has been formed, the method proceeds to step 1714, where supplementary identification marks are formed in the upper surface of the passivation layer above the front side of the wafer. 15A-15C show examples of some ways in which step 1714 may be implemented.

At step 1716, the processed wafer may be sent out for outsourced assembly and test (OSAT), where the supplemental identification mark will be used to track the wafer during the test. During OSAT, a grinding operation is performed on the back side of the wafer to thin the wafer, thereby removing the 2D matrix code symbols and the back side identification marks. 16A to 16C show examples of some ways in which step 1712 may be implemented.

At step 1718, a test is performed. After testing, the wafer is singulated into dies that are packaged and sold.

Although the disclosed method may be described and/or illustrated herein as a series of actions or events, it should be understood that the illustrated sequence of such actions or events should not be interpreted in a restrictive sense. For example, in addition to the actions or events illustrated and/or described herein, some actions and other actions or events may occur in a different order and/or at the same time. In addition, not all illustrated actions may be required to implement one or more aspects or embodiments described herein. In addition, one or more of the actions described herein may be performed in one or more separate actions and/or stages. In addition, although the method is described in conjunction with FIGS. 8 to 11 and FIGS. 13 to 16, it should be understood that the method is not limited to such a structure, but can instead be used as a method independent of the structure.

Therefore, some embodiments are related to a semiconductor wafer. The wafer includes a first side with a first center and a second side with a second center. The first center and the second center are respectively arranged on the central axis of the semiconductor wafer passing through the first surface and the second surface. The first surface and the second surface adjoin each other at a circumferential edge. An alignment notch extending inward from the circumferential edge to a radial distance of the alignment notch is provided at a position along the circumferential edge. The radial distance of the alignment notch is smaller than the wafer radius as measured from the first center to the circumferential edge. The crystal grain area including the array of crystal grains arranged in columns and rows on the first surface is bounded on the circumference by a non-crystal grain area without crystal grains. The first identification mark including a string of characters is completely arranged in the die-free area, facing the first side of the alignment notch.

Some other embodiments relate to semiconductor wafers with circumferential edges. The wafer includes an array of dies arranged in columns and rows and a die region bounded by a die-free region that does not contain a die on the circumference. The substantially circular edge of the crystal grain area separates the crystal grain area from the non-crystal grain area. The alignment notch is provided at a position along the circumferential edge of the semiconductor wafer. The alignment notch extends inward from the circumferential edge by a radial distance of the alignment notch. The first identification mark is completely arranged in the die-free area, facing the first side of the alignment notch. The second identification mark is completely arranged in the die-free area, facing the second side of the alignment notch.

Other embodiments relate to semiconductor wafers, which include a first side with a first center and a second side with a second center. The first center and the second center are respectively arranged on the central axis of the semiconductor wafer passing through the first surface and the second surface. The first surface and the second surface are adjacent to each other at the circumferential edge. The alignment notch is provided at a position along the circumferential edge. The alignment notch extends inward from the circumferential edge by a radial distance of the alignment notch. The radial distance of the alignment notch is smaller than the wafer radius as measured from the first center to the circumferential edge. The crystal grain area includes an array of crystal grains arranged in columns and rows on the first surface and is bounded by a non-crystal grain area without crystal grains on the circumference. The main identification mark is arranged directly above the first surface completely in the no-die area, facing the first side of the alignment notch. The supplementary identification mark is arranged in the layer above the first surface. The supplementary identification mark has the same value as the main identification mark, but is set at a height above the first surface, which is higher than the height of the main identification mark.

Some other embodiments relate to methods of receiving semiconductor wafers. The first identification mark is formed on the front side of the wafer or a layer above the front side of the wafer. At least one dielectric layer and at least one conductive layer are formed above the semiconductor wafer and above the first identification mark. After at least one dielectric layer and at least one conductive layer have been formed, the method determines whether the first identification mark is readable. Based on whether the first identification mark is readable, the second identification mark is selectively formed in or on the at least one dielectric layer and the at least one conductive layer.

Other embodiments relate to a method of receiving a semiconductor wafer on which N layers will be formed. The wafer has two-dimensional matrix code symbols on the back side of the wafer and identification marks spaced from the matrix code symbols on the back side of the wafer. At least one dielectric layer and at least one conductive layer are formed above the semiconductor wafer to build a semiconductor element above the front side of the semiconductor wafer. The passivation layer is formed on the at least one dielectric layer and the at least one conductive layer. After the passivation layer has been formed, a supplementary identification mark is formed above the front side of the wafer, in the upper surface of the passivation layer.

Yet other embodiments relate to a method. In this method, a semiconductor wafer including a front side with a first center and a back side with a second center is received. The front side surface includes a crystal grain area that includes an array of crystal grains arranged in columns and rows and is bounded by a non-crystal grain area without crystal grains on the circumference. The first center and the second center are respectively arranged on the center axis passing through the front side and the back side of the semiconductor wafer. The front side and the back side adjoin each other at the circumferential edge. The back side does not contain semiconductor components, but contains the back side identification mark. The alignment notch is provided at a position along the circumferential edge. The alignment notch extends inward from the circumferential edge by a radial distance of the alignment notch. The first front side identification mark is formed on the front side of the semiconductor wafer, and a layer is formed above the front side and above the first front side identification mark. After the layer has been formed, the method determines whether the first front side identification mark is readable. Based on whether the first identification mark is readable, the second front side identification mark is selectively formed in or above the layer.

In some embodiments, the first identification mark is bounded by an outer periphery, and the width of the outer periphery in the plane of the first surface is within a range between 3 millimeters (mm) and 5 millimeters. The height in the plane of the first surface is within a range between 0.25 mm and 0.75 mm.

In some embodiments, the first identification mark is a string of characters and numerals whose characters are recognized on a wafer in an integrated circuit manufacturing facility, wherein the characters have the first rectangle that falls on the periphery of the first rectangle. A set of edges and the upper and outer edges of the second set of edges.

In some embodiments, the first distance is less than the minimum length of the first identification mark measured between the second set of edges.

In some embodiments, the semiconductor wafer further includes: a second identification mark, which is completely disposed in the die-free area, facing the second side of the alignment notch; and wherein the second identification mark The sign has a second rectangular periphery, and the second rectangular periphery has a third set of edges extending parallel to the first axis and a fourth set of edges extending parallel to the second axis.

In some embodiments, the first edge of the third set of edges is spaced from the second axis by the first distance, so that the first rectangular periphery and the second rectangular periphery are symmetrical to the first Two axis.

In some embodiments, a column of die has a bottom edge arranged parallel to the first edge.

In some embodiments, the semiconductor wafer exhibits no identification mark between the innermost end of the alignment recess and the bottom edge of the column of dies along the second axis.

In some embodiments, the semiconductor wafer further includes: a backside identification mark on the backside of the semiconductor wafer.

In some embodiments, the semiconductor wafer further includes: a two-dimensional matrix code symbol on the back side of the semiconductor wafer, wherein the two-dimensional matrix code symbol and the back side of the semiconductor wafer The back side identification marks above are spaced apart.

In some embodiments, the first identification mark and the second identification mark each exhibit the same alphanumeric character string, and the backside identification mark has the same character as the first identification mark and the second identification mark. Identify different characters of the mark.

The foregoing summarizes the characteristics of several embodiments, so that those with ordinary knowledge in the field can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other manufacturing processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those with ordinary knowledge in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and various changes and substitutions can be made in this text without departing from the spirit and scope of the present invention. And change.

100: wafer 102: first side 102c: first center 104: second side 105: central axis 106: circumferential edge 108: notch 110: die area 112: no die area 114: die area edge 116: Die 116', 116'', 704a, 704b, 706a, 706b, 710a, 710b, 712a, 712b: edge 118: cutting track 120, 122, 120a, 122a, 720, 722: identification mark 124: roll-off area 126 : Wafer edge exposed area 132: Hash area 134: Y-axis 136: X-axis 150, 158: Outer periphery 152, 156, 160, 164: Number elements 154, 162: Dash line 166: Back-end process metallization structure 168 : Passivation layer 602, 702: first rectangular periphery 610, 708: second rectangular periphery 604, 604a, 612, 612a: radial axis 606, 614, 728: lines 608, 616, 724: tangent segment 726: virtual extension 1002 : Gate 1004: source/drain regions 1202, 1204, 1206: step 1302: two-dimensional matrix code symbol 1304: substrate identification code A: area w ₁ , w ₂ : width h ₁ , h ₂ : height θ ₁ , θ ₂ , θ _1a , θ _2a : angles 1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216, 1218, 1220, 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, 1718: steps

The aspects of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily. FIG. 1 illustrates a perspective view of a semiconductor wafer including identification marks according to some embodiments. Figure 2 illustrates a top view of a semiconductor wafer containing identification marks according to some embodiments. FIG. 3 illustrates a cross-sectional view of a semiconductor wafer including identification marks according to some embodiments. Figure 4 illustrates a top view of the main identification marks according to some embodiments. Figure 5 illustrates a top view of a supplementary identification mark according to some embodiments. FIG. 6A illustrates a top view of a semiconductor wafer including identification marks according to some embodiments. FIG. 6B illustrates a top view of a semiconductor wafer including identification marks according to other embodiments. Figure 6C illustrates an enlarged top view of a portion of the semiconductor wafer of Figure 6B. FIG. 7 illustrates a top view of a semiconductor wafer including identification marks according to some embodiments. 8A to 8B to 11A to 11B show a sample manufacturing process, such as a 200 mm wafer manufacturing process, in which one or more identification marks are separately formed on the front side of the wafer. FIG. 12 illustrates some embodiments of the manufacturing process in a flow chart format, which is consistent with some embodiments of FIGS. 8A to 8B to 11A to 11B. Figures 13A to 13D to 16A to 16C show the sample manufacturing process, such as a 300mm wafer manufacturing process, in which the main identification mark is separately formed on the back side of the wafer, and the identification mark is supplemented after the component features have been formed Formed on the front side of the passivation layer. FIG. 17 shows some embodiments of the manufacturing process in a flow chart format, which is consistent with some embodiments of FIGS. 13A to 13D to 16A to 16C.

100: Wafer

102: first side

102c: First Center

104: second side

105: central axis

106: circumferential edge

108: Notch

110: Grain area

112: No grain area

114: Edge of the grain area

120, 122: identification mark

134: y axis

136: x axis

Claims (8)

A method for forming an identification mark includes: receiving a semiconductor wafer; forming a first identification mark on the front side of the semiconductor wafer or on a layer above the front side of the semiconductor wafer, wherein the first identification mark is formed The identification mark includes: forming a plurality of first discrete pits, wherein the plurality of first discrete pits collectively establish a first series of alphanumeric elements corresponding to the first identification mark; combining at least one dielectric layer and at least A conductive layer is formed above the semiconductor wafer and the first identification mark; after the at least one dielectric layer and the at least one conductive layer have been formed, it is determined whether the first identification mark is readable And based on whether the first identification mark is readable, selectively forming a second identification mark in or above the at least one dielectric layer and the at least one conductive layer, wherein the second identification is formed The mark includes forming a plurality of second discrete pits, wherein the plurality of second discrete pits collectively establish a second series of alphanumeric elements corresponding to the second identification mark. The method for forming the identification mark as described in item 1 of the scope of patent application further includes: if the second identification mark is not formed, forming a passivation layer on top of the at least one dielectric layer and the at least one conductive layer The second identification mark is not formed; and if the second identification mark is formed, a passivation layer is formed on top of the second identification mark. The formation method of the identification mark as described in item 2 of the scope of patent application: Wherein the laser is sent by pulse to form the plurality of first discrete pits; and where the laser is sent by pulse to form the plurality of second discrete pits. According to the method for forming the identification mark described in item 1 of the scope of patent application, the first series of alphanumeric elements are the same as the second series of alphanumeric elements. A method for forming an identification mark includes: receiving a semiconductor wafer on which N layers will be formed, wherein the wafer has a two-dimensional matrix code symbol on the back side of the wafer and An identification mark on the back side spaced apart from the two-dimensional matrix code symbol; at least one dielectric layer and at least one conductive layer are formed on the semiconductor wafer so as to be established above the front side of the semiconductor wafer A semiconductor element; forming a passivation layer over the at least one dielectric layer and the at least one conductive layer; after the passivation layer has been formed, on the upper surface of the passivation layer above the front side of the wafer Forming a supplementary identification mark in the middle; and performing grinding on the back side of the wafer to reduce the thickness of the wafer, thereby removing the two-dimensional matrix code symbol and the identification mark. The method for forming the identification mark described in item 5 of the scope of the patent application further includes: after the backside of the wafer has been polished to remove the two-dimensional matrix code symbol, the wafer Sent for outsourced assembly and testing (OSAT), where the supplementary identification mark is used to track the wafer during testing. A method for forming an identification mark includes: receiving a semiconductor wafer, the semiconductor wafer including: a front side with a first center, the front side including a substantially circular Die region, the die region includes an array of dies arranged in columns and rows and is bounded by a region without dies without dies on the circumference; a back side with a second center, the first center and The second centers are each arranged on a central axis of the semiconductor wafer passing through the front side and the back side, and the front side and the back side are adjacent to each other at a circumferential edge, wherein the back The side surface does not contain semiconductor components, but contains the first backside identification mark; the alignment notch is provided at a position along the circumferential edge, and the alignment notch extends inward from the circumferential edge to reach the alignment concave The radial distance of the mouth; a first front side identification mark is formed on the front side of the semiconductor wafer; a layer is formed above the front side and above the first front side identification mark; after the layer has been formed, it is determined Whether the first front side identification mark is readable; and based on whether the first identification mark is readable, a second front side identification mark is selectively formed in or above the layer, wherein the first front side The identification mark and the second front side identification mark include the same alphanumeric character string, and the first back side identification mark is different from the first front side identification mark and the second front side identification mark. The method for forming an identification mark according to item 7 of the scope of patent application, wherein the first front side identification mark is delimited by a first outer periphery, and the first outer periphery has a range between 3 mm and 5 mm Width and height in the range between 025 mm and 0.75 mm.

Images