CN112820717A - Chip cross section identification mark and manufacturing method thereof - Google Patents
Chip cross section identification mark and manufacturing method thereof Download PDFInfo
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- CN112820717A CN112820717A CN202011615608.7A CN202011615608A CN112820717A CN 112820717 A CN112820717 A CN 112820717A CN 202011615608 A CN202011615608 A CN 202011615608A CN 112820717 A CN112820717 A CN 112820717A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000003780 insertion Methods 0.000 claims abstract description 16
- 230000037431 insertion Effects 0.000 claims abstract description 16
- 238000013461 design Methods 0.000 abstract description 10
- 238000012790 confirmation Methods 0.000 abstract description 3
- 238000012795 verification Methods 0.000 description 6
- 238000010923 batch production Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000003086 colorant Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a chip cross section identification mark and a manufacturing method thereof, wherein the chip cross section identification mark comprises a plurality of metal layers and metal through hole layers arranged between the metal layers, and all the metal layers and the metal through hole layers jointly form the shape of the whole identification mark; the identification mark is inserted in the position which does not influence the original function and performance of the chip in the cross-sectional view of the chip into which the identification mark is to be inserted. Firstly, determining a preset identification mark; determining the insertion position of the preset identification mark by combining all cross-sectional views of the chip; combining the determined insertion positions, combining the layers of the chip and the layers of the preset identification mark together, storing the combined layers in a GDSII file, and delivering the file to a process plant to produce the chip containing the identification mark. The mark of the invention has hiding property, and can carry out ownership confirmation under the condition that chip design ownership generates disputes; by fusing the mark with the original circuit, any erase operation may disable the circuit logic and render the mark non-erasable.
Description
Technical Field
The invention relates to a chip cross section identification mark and a manufacturing method thereof, belonging to the technical field of chip marking.
Background
Generally speaking, the physical design of a chip is often completed through a top view of the chip, and the chip is physically divided into different layers, and if there is a logical relationship between the layers, the circuit connection is completed through a perforation. The bottom layers of the chip are logic devices such as nand gates and the like as shown in fig. 1; while the other layers of the chip complete the circuit connections to these logic devices to achieve their functionality (as shown in fig. 2, the circuit connections are implemented through multiple layers, with different layers being represented by different colors in the design tool). When viewed in cross-section, the chip will appear as the schematic diagram shown in fig. 3.
At present, after the chip design is completed, the chip design information is stored in a GDSII file for storing the chip design information in a layered manner, and then the GDSII file is delivered to a process factory for production. To facilitate the discrimination of the chips, identification marks are usually added to the chips. Most of the existing identification marks exist on the plane of the chip. In particular, such indicia, typically a company logo or a specific character, may be inserted directly into one or more layers of the chip. In the actual use process, the following problems exist:
1. the method has no hiding property and can be easily found;
2. can be easily erased, and if a competitor steals the GDSII file, the mark can be easily erased.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a chip cross section identification mark and a manufacturing method thereof, which can solve the problem that the original mark does not have hiding property and can carry out ownership confirmation under the condition that chip design ownership is disputed; by fusing the mark with the original circuit, any erase operation may disable the circuit logic and render the mark non-erasable.
In order to achieve the purpose, the invention adopts the following technical scheme: a chip cross section identification mark comprises a plurality of metal layers and metal through hole layers arranged among the metal layers, wherein all the metal layers and the metal through hole layers form the shape of the whole identification mark; the identification mark is inserted in the position which does not influence the original function and performance of the chip in the cross-sectional view of the chip into which the identification mark is to be inserted.
Further, the identification mark is inserted in the form of layers in each layer of the chip into which the identification mark is to be inserted.
Furthermore, each metal layer in the identification mark corresponds to a metal layer to be inserted into the identification mark chip.
Further, the shape of the identification mark is a character or a special figure.
A method for manufacturing a chip cross section identification mark comprises the following steps:
step S1, determining a preset identification mark, and designing each corresponding layer according to the preset identification mark;
step S2, determining the insertion position of the preset identification mark by combining the cross-sectional view of the chip to be inserted with the identification mark;
step S3, combining each layer of the identification mark chip to be inserted and each layer of the preset identification mark together by combining the determined insertion position, and storing the combined layers into a GDSII file;
step S4, the GDSII file is delivered to a process factory for production, and a chip with an identification mark is formed.
Further, the identification mark preset in the step S1 is a character or a special figure.
Further, the insertion position of the identification mark in the step S2 is preset as a position in the cross-sectional view of the chip where the identification mark is to be inserted, where the original function and performance of the chip are not affected.
Further, the preset identification mark comprises a plurality of metal layers and metal through hole layers arranged between the metal layers, and all the metal layers and the metal through hole layers jointly form the shape of the whole identification mark.
Furthermore, the metal layers in the preset identification mark are positioned on the metal layers to be inserted into the identification mark chip.
Further, the chip formed in step S4 can be longitudinally sliced to reveal the inserted identification mark through a microscope.
Compared with the prior art, the invention has the following advantages:
1. the identification mark is split into a plurality of layers and inserted into the position of the cross section of the chip, which does not influence the original function and performance of the chip; the inserted position is only known by a designer and cannot be known by other people, so that the problem that the original mark is not hidden is solved, and ownership can be confirmed under the condition that ownership of the chip design is disputed;
2. by fusing the mark with the original circuit, any erase operation may disable the circuit logic and render the mark non-erasable.
Drawings
FIG. 1 is a logic device at the bottom of a chip;
FIG. 2 is a schematic diagram of a circuit connection of a chip;
FIG. 3 is a schematic cross-sectional view of a chip;
FIG. 4 is an example of a special pattern of the present invention;
FIG. 5 is a cross-sectional view of an actual chip under a viewing device;
FIG. 6 is a top view of a multi-layer design of a character A of the present invention;
FIG. 7 is a schematic view of layer 6 of character A;
FIG. 8 is a schematic view of the hole 5 of character A;
FIG. 9 is a schematic view of layer 5 of character A;
FIG. 10 is a schematic view of the hole 4 of character A;
FIG. 11 is a schematic view of layer 4 of character A;
FIG. 12 is a schematic view of the hole 3 of character A;
FIG. 13 is a schematic view of layer 3 of character A;
FIG. 14 is a schematic view of hole 2 of character A;
FIG. 15 is a layer 2 diagram of character A;
fig. 16 is a cut-away cross-sectional view of C-C in fig. 6.
Detailed Description
The technical solutions in the implementation of the present invention will be made clear and fully described below with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 4 to 16, the chip cross-section identification mark provided by the present invention includes a plurality of metal layers and metal via layers disposed between the metal layers, all the metal layers and the metal via layers together form the shape of the entire identification mark; the identification mark is inserted in the position which does not influence the original function and performance of the chip in the cross-sectional view of the chip into which the identification mark is to be inserted. There may be a plurality of identification marks that can be inserted on the same chip. The position in the cross-sectional view of the chip, which does not affect the original function and performance of the chip, may be a non-critical timing path, a metal filling region or a gap, as long as it does not affect the original function and performance of the chip. In the actual operation process, after the identification mark is inserted into the preset position, the chip finally formed and containing the identification mark is verified, and the chip is put into batch production after the verification is passed; if the verification fails, the insertion position needs to be readjusted, so that the chip is not influenced.
Further, the identification mark is inserted in the form of layers in each layer of the chip into which the identification mark is to be inserted.
Furthermore, each metal layer in the identification mark corresponds to a metal layer to be inserted into the identification mark chip.
Further, the shape of the identification mark is a character or a special figure, which can be shown in fig. 4.
A method for manufacturing a chip cross section identification mark comprises the following steps:
step S1, determining a preset identification mark, and designing each corresponding layer according to the preset identification mark;
step S2, determining the insertion position of the preset identification mark by combining the cross-sectional view of the chip to be inserted with the identification mark;
step S3, combining each layer of the identification mark chip to be inserted and each layer of the preset identification mark together by combining the determined insertion position, and storing the combined layers into a GDSII file;
step S4, the GDSII file is delivered to a process factory for production, and a chip with an identification mark is formed.
Further, the identification mark preset in the step S1 is a character or a special figure.
Further, the insertion position of the identification mark in the step S2 is preset as a position in the cross-sectional view of the chip where the identification mark is to be inserted, where the original function and performance of the chip are not affected. The position in the cross-sectional view of the chip, which does not affect the original function and performance of the chip, may be a non-critical timing path, a metal filling region or a gap, as long as it does not affect the original function and performance of the chip. In the actual operation process, after the identification mark is inserted into the preset position, the chip finally formed and containing the identification mark is verified, and the chip is put into batch production after the verification is passed; if the verification fails, the insertion position needs to be readjusted, so that the chip is not influenced.
Further, the preset identification mark comprises a plurality of metal layers and metal through hole layers arranged between the metal layers, and all the metal layers and the metal through hole layers jointly form the shape of the whole identification mark.
Furthermore, the metal layers in the preset identification mark are positioned on the metal layers to be inserted into the identification mark chip.
Further, the chip formed in step S4 can be longitudinally sliced to reveal the inserted identification mark through a microscope.
Examples
Taking character A as an identification tag
As shown in fig. 6 to 16, the character a is first split into a plurality of layers, i.e., into 5 metal layers, the upper and lower two adjacent metal layers are communicated with each other through metal via layers, and all the metal layers and the metal via layers form an a-shape together; determining the insertion position of the preset identification mark by combining the cross-sectional view of the chip into which the identification mark is to be inserted; then, combining each layer of the chip to be inserted with the identification mark with each layer of the preset identification mark by combining the determined insertion position, and storing the combined layers into a GDSII file; finally, the GDSII file is delivered to a process factory for production, and a chip containing the identification mark is formed. Verifying the finally formed chip containing the identification mark, and putting the chip into batch production after the verification is passed; if the verification fails, the insertion position needs to be readjusted, so that the chip is not influenced.
The identification marks hidden in the chip can be displayed through longitudinal slicing by observation equipment such as a microscope after being produced by a process plant, so that the purpose of ownership confirmation is achieved.
In summary, the identification mark is divided into multiple layers, and the identification mark is inserted into the position of the cross section of the chip, which does not affect the original functions and performances of the chip; the inserted position is only known by a designer and cannot be known by other people, so that the problem that the original mark does not have hiding performance is solved, and ownership can be confirmed under the condition that chip design ownership is disputed. Meanwhile, the mark is fused with the original circuit, any erasing operation can cause the logic of the circuit to be invalid, and the mark is non-erasable.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the embodiments may be appropriately combined to form other embodiments understood by those skilled in the art.
Claims (10)
1. A chip cross section identification mark is characterized by comprising a plurality of metal layers and metal through hole layers arranged among the metal layers, wherein all the metal layers and the metal through hole layers form the shape of the whole identification mark; the identification mark is inserted in the position which does not influence the original function and performance of the chip in the cross-sectional view of the chip into which the identification mark is to be inserted.
2. A chip cross-section identification tag as claimed in claim 1, wherein the identification tag is inserted in layers in the chip into which the identification tag is to be inserted.
3. A chip cross-section identification tag as claimed in claim 2, wherein each of said metal layers in the identification tag corresponds to a metal layer to be inserted into the identification tag chip.
4. A chip cross-section identification mark as claimed in claim 1, wherein the identification mark is in the shape of a character or a special figure.
5. A method for manufacturing a chip cross section identification mark is characterized by comprising the following steps:
step S1, determining a preset identification mark, and designing each corresponding layer according to the preset identification mark;
step S2, determining the insertion position of the preset identification mark by combining the cross-sectional view of the chip to be inserted with the identification mark;
step S3, combining each layer of the identification mark chip to be inserted and each layer of the preset identification mark together by combining the determined insertion position, and storing the combined layers into a GDSII file;
step S4, the GDSII file is delivered to a process factory for production, and a chip with an identification mark is formed.
6. The method for manufacturing an identification mark of a chip cross section as claimed in claim 5, wherein the identification mark preset in the step S1 is a character or a special figure.
7. The method as claimed in claim 5, wherein the insertion position of the identification mark in step S2 is preset as a position in the cross-sectional view of the chip where the identification mark is to be inserted, which does not affect the original function and performance of the chip.
8. The method as claimed in claim 5, wherein the predetermined identification mark comprises a plurality of metal layers and metal via layers disposed between the metal layers, and all the metal layers and the metal via layers together form the shape of the entire identification mark.
9. The method as claimed in claim 8, wherein each of the metal layers in the predetermined identification mark is located in a metal layer to be inserted into the chip of the identification mark.
10. The method as claimed in claim 5, wherein the chip formed in step S4 is longitudinally sliced to reveal the inserted identification mark through a microscope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011615608.7A CN112820717A (en) | 2020-12-30 | 2020-12-30 | Chip cross section identification mark and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011615608.7A CN112820717A (en) | 2020-12-30 | 2020-12-30 | Chip cross section identification mark and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN112820717A true CN112820717A (en) | 2021-05-18 |
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| CN202011615608.7A Pending CN112820717A (en) | 2020-12-30 | 2020-12-30 | Chip cross section identification mark and manufacturing method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256376A (en) * | 2017-07-14 | 2019-01-22 | 台湾积体电路制造股份有限公司 | Semiconductor crystal wafer and its manufacturing method with miniature identification label |
| CN110993586A (en) * | 2018-10-02 | 2020-04-10 | 三星电子株式会社 | Semiconductor package |
| TWI714419B (en) * | 2020-01-06 | 2020-12-21 | 力晶積成電子製造股份有限公司 | Semiconductor stack structure with concealed identifier |
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2020
- 2020-12-30 CN CN202011615608.7A patent/CN112820717A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109256376A (en) * | 2017-07-14 | 2019-01-22 | 台湾积体电路制造股份有限公司 | Semiconductor crystal wafer and its manufacturing method with miniature identification label |
| CN110993586A (en) * | 2018-10-02 | 2020-04-10 | 三星电子株式会社 | Semiconductor package |
| TWI714419B (en) * | 2020-01-06 | 2020-12-21 | 力晶積成電子製造股份有限公司 | Semiconductor stack structure with concealed identifier |
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