TW447109B - Method for protecting the wafer mark - Google Patents

Abstract

The present invention provides a method for protecting the wafer mark which at least comprises: providing a substrate having a plurality of chips and at least one mark in which these chips and the mark are not overlapped; uniformly covering a base layer on the substrate and covering the mark; forming a passivation layer on the base layer such that the passivation layer only covers the mark but not covering the chips; processing the base layer and the passivation layer with planarization procedure so that the portion of the base layer on the mark is covered by the passivation layer without being damaged; and, removing the passivation layer. Obviously, the basic concept of the present invention is to employ the passivation layer to protect part of the base layer on the mark so that the surface profile of the portion of the base layer is the same as the surface profile of the mark. The so-called mark may be at least the alignment mark or wafer identification.

Description

447 1 .09 Description of the Invention (1) Field of the Invention The present invention relates to a method for protecting a label on a wafer, and in particular, β is used to prevent the utility of the label on the wafer from being affected by, for example, a chemical and mechanical polishing process planarization process. Failure method. Xun 5_2 Background of the Invention: In the semiconductor factory, because there are many wafers corresponding to different products or different process sections being processed at the same time, and the differences of these wafers are often not discernable by the human eye. The wafer will have a wafer identification code (wafer i den tifi cat i on) for identification. In addition, because in the lithography process, not only the wafer position must be broken, but also each wafer on the wafer must be in the correct position, otherwise the mask pattern will be transferred to the wafer. The correct pattern cannot be obtained, so there are also alignment marks (usually two) at the edge of the wafer to provide a basis for calibrating the wafer position and angle before performing lithography and other procedures. Incidentally, the wafer identification code is composed of a plurality of holes located on the wafer surface, and the alignment target is composed of a plurality of lines on the wafer surface, and the wafers are aligned. Both the identification code and the alignment standard can be used as a wafer label. Obviously, the damage or failure of the wafer tag brings many disadvantages.

447109 ~ --------- V. Description of the invention (2) ^ ^ '$ The damage is caused by the wafer identification mother, which will cause the wafer to be unrecognizable. When producing: (especially the machine in the reaction) When the machine crashes and cannot be performed as scheduled, the disadvantage is even more serious. In contrast, when the failure is the alignment target, it is either that the lithography machine cannot correctly position the wafer and the pattern transferred to the wafer is in the wrong position, or the machine cannot determine how to position the wafer and refuses to process it. This chip. There may be many reasons for the damage or failure of the Japanese and Japanese round labels, and the most common is the wafer surface deformation caused by the processing of the wafer surface during the planarization process. Although the planarization process is to planarize the surface of each chip in the wafer, the entire wafer surface is usually processed during the process', so the wafer label is always unavoidable. Especially when chemical mechanical polishing is widely used, 'due to the fact that the polishing process will remove parts of the wafer surface that have formed structures', and the dish effect often caused by the difference in the structure density of the wafer label and the die. Therefore, the damage and failure of wafer tags will be more obvious. Please refer to Figure A and Figure B for the changes before and after the mechanical polishing process. Please pay attention to the surface of the surface layer 12 on the original wafer label 11 on the substrate 10, before polishing The contour of the surface is the same as that of the original wafer label 11 (excluding some inevitable errors in production) and can be used as a new wafer label 1 3, but the original wafer label 11 cannot be correctly displayed due to deformation after grinding. Surface contour. For example, in the process of staggering the formation of a general dielectric layer (transparent) and a metal ’layer (opaque), theoretically, each metal layer is on the wafer label of the substrate.

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Above, the surface contour should be the same as the surface of the wafer label of the substrate. The surface contour should be the same so that the opaque metal layer can be used as a new wafer label. However, the dielectric layer may be deformed and deformed during the planarization process, so that the surface profile of the dielectric layer above the substrate A is different from the surface profile of the substrate wafer label. The metal layer can completely replicate the surface profile of the dielectric layer, nor can it obtain the same surface profile as the substrate wafer label. There are two common methods to deal with this problem in the conventional technology: one is the method proposed by us 5, 456, 756 'by modifying the machine that forms the metal layer (such as sputter), cover it with a gasket before forming the metal layer On the wafer label, the metal layer will not cover the wafer label. At this time, regardless of whether the surface profile of the transparent dielectric layer is the same as the surface profile of the wafer label on the substrate, the subsequent process steps can directly see the wafer label on the substrate without being covered by the opaque metal layer. Disturbance, that is, the lithography machine can always align the target and the operator can always identify the wafer identification code; the other is the method proposed by ^ 8 ^ 5, 801, 〇90, in a flat Process (such as grinding process

After the sequence I is completed, the layers on the wafer label (such as a transparent dielectric layer) are removed by additional lithography and etching procedures, and then the wafer label is used as the standard, so that the original is located on the wafer label. The surface contours of the layers on the upper layer will not affect the subsequent processes, that is, the lithography machine can always produce an alignment target and the operator can always identify the wafer identification code. In any case, these two methods are also accompanied by some unavoidable or completely overcome disadvantages: As far as the former method is concerned, the etiquette becomes complicated, and the existence of the gasket also makes it necessary to operate;

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When a multi-layered structure (such as a multilayer metal interconnect) is used, it must be performed on the part above the wafer label after the formation—two lithography and one etching. The original wafer label can not be covered and can perform its function correctly. At this time, in addition to increasing the process time (cy cie inline) and the possibility of errors due to operating errors, the layers are peeled from each other due to peeling. Pollution caused by the particles is a major cause. From the discussion above, we can see that how to ensure that the wafer label (regardless of the standard or wafer identification code) is not damaged and can be straightened normally. It is a process of C in the semiconductor process, especially a chemical mechanical polishing process ') A rather important topic. In addition, because the two methods commonly used in conventional technology are facing the defects of "# 法 克 月", and will increase with the number of multiple structural layers, it is necessary to develop a new method, especially not Method 5-3 Method Inferior in Power Due to Increase in Multiple Structure Layers Aim and Summary of the Invention: A main object of the present invention is to provide a method for protecting wafers, especially to prevent the effectiveness of labels on wafers from being flat. Method of deterioration or failure of the program.

Page 7 44 * n 〇9 V. Description of the invention (5) 'I Another object of the present invention is to make a layer f * newly formed on the surface of the wafer have the same surface profile as the layer below it, thereby ensuring the wafer The utility of the label is equal at each level. Another object of the present invention is to provide a device that does not need to modify the conventional semiconductor process (especially development and etching) and does not need to be large. It is necessary to modify the steps of the conventional semiconductor process. Utility method. Inventor-A preferred embodiment is a method for protecting a wafer tag

Second, this embodiment includes at least the following basic steps: first, a substrate having a plurality of particles and at least one label is provided, wherein these particles are not heavy with this label ^ ', and the following sentences cover a base layer on the substrate and Cover this label; then form a protective layer on the base layer, where the protective layer only covers the label and does not cover the grains and minerals. The base layer and the protective layer are processed at the same time by a flattening process, so that the root cause of injury in the standard layer Covered with a protective layer without being damaged; finally the protective layer is removed.

Another preferred embodiment of KI / μ is a method for protecting wafer labels from mechanical failure and failure. The basic process of the method A is as follows: With: a plurality of crystal grains and at least one label substrate, these crystal grains are formed with the label; and a base layer is formed on the substrate and the label is uniformly covered; a negative first layer is formed on the base layer; The negative photoresist layer is processed by the wafer edge exposure program so that the negative photoresist layer covers only the label; the base layer and the negative photoresist layer are ground during the chemical mechanical polishing process R, where the part above the label

Page 8 447109 Five 'invention description (6), the layer will not be polished because it is covered by the negative photoresist layer, so the base and surface profile of this part are the same as the top surface profile of the label; and the negative photoresist layer is removed . Party 2 naturally said that the basic concept of the present invention is to use a protective layer to protect the label ^ σ 卩 damage base layer ', so that the contour of the surface of this part of the base layer is the same as that of the defined surface. 5-4 Detailed description of the invention: A preferred embodiment of the invention is a method for protecting the target bismuth (to package: 'target or wafer identification chip) of the wafer, as shown in the figure to the second. The method proposed in this embodiment includes at least the following basic steps. First, provide these crystals on the two end labels of the bit label 22, and depict the top view of the crystals, as shown in Figure 4 on the right and 22 on the right. Schematic diagram: The substrate M grain 21 and the label 22 of several grains 21 and at least one iron 22 are not heavy, and the surfaces of the grains 21 are lumped. When the “Crane Crane”: the surface of 2? 22 is not higher than the edge of the wafer: when the sign is the wafer identification code, the label 22 is the number when the target is aligned; and when the two sets of pictures U sign circle 23 are the same on the surface -Diameter so this subsequent illustration will mostly only focus on the label of the circle and no more grains.

447109 V. Description of the invention (7) " Then, as shown in the second diagram B, first form the base layer 24 on the substrate 23 and uniformly cover the label 22 'so that the portion of the base layer 24 above the label 22 The top surface contour is the same as the top surface contour of the label 22, and then a protective layer 25 is formed on the base layer 24. Here, the base layer 24 may be at least a metal layer or a dielectric layer. The metal layer includes at least a tungsten layer and the dielectric layer includes at least an oxide layer. At the same time, it must be emphasized that the protective layer 25 only covers the label 22 and does not cover the crystal grains 21, as shown in the schematic plan view shown in FIG. 2C. In addition, the possible types of protective layer holders include at least a photoresist layer, and when the protective layer 25 is a negative photoresist layer, the protective layer 25 is passed through a wafer edge exposure process (wafer to exposure PrOCess) and A portion of the base layer ^ above the label 22 is formed. Mechanical research 2 As shown in the second D figure, 'Li Liang' uses a flattening process (for example, chemically treats both the base layer 24 and the protective layer 25. At this time, the base layer 24 above the pole label 23 is not bad. Therefore, this part is covered by the 厣 94 玷 phase master 5 without being damaged. The top surface profile of the base layer 24 and the top surface of the label 23 are shown, and the protective layer 25 is removed. No doubt the ground The wheel ^ η part of the force hurts the surface of the base layer 24 and the top surface gallery of the label 23 _ 1 This can be a part of the base layer 24 above the label 23 as a new ^ i

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The use of the signature 26 can ensure that the effectiveness of the label 23 will not be invalidated by the progress of the chemical conversion. Another preferred embodiment of the present invention is a method for protecting a wafer tag from chemical mechanical polishing, which is proposed for a semiconductor process that requires high surface flatness or damascene technology, and includes at least the following basic steps: First, as shown in FIG. 3A, a substrate 30 is provided. Here, the substrate 30 has at least a plurality of crystal grains 31 and at least one label 32. These crystal grains 31 and the label 32 not only do not overlap with each other, but the height of the top surface of the label 32 is lower than the top surface of the crystal grain 31. height. The possible types of label 32 include at least the alignment target and the wafer identification code 'wherein the alignment target is an array of lines composed of a plurality of lines' and its side length is about 400 microns, and the wafer identification code is composed of The dot array composed of a plurality of holes has a width of about 9 mm and a length of about 20 mm. It must be emphasized that the series of diagrams used to explain the invention are only schematic diagrams. The exact geometric dimensions and relative positions must depend on the actual wafer configuration. Then, as shown in Fig. 23B, a base layer 33 is formed on the substrate 30 and uniformly covers the die 31 and the label 32. Here, the base layer 33 may be at least a metal layer or a dielectric layer. The metal layer includes at least a tungsten layer and the dielectric layer includes at least an oxide layer. 0 447109 V. Description of the invention (9) The photoresist layer 34 is on the base layer 33, such as the third one; and then a negative photoresist is applied to the developing machine to perform a wafer edge exposure process, and the photoresist layer 34 is not negative, so that the negative photoresist layer 34 covers only Daniel's three D picture. E ', the second step is to grind the base layer 33 and minus 34 at the same time by the CMP process. The base layer 33 above the label 32 is not covered by the CMP process because it is covered by the negative photoresist layer. Grinding, so the top surface contour of the base layer 33 of 3 j and the top surface contour of the label 32 are similar to each other, as shown in the figure III. &Quot; Eye question, of course, this implementation is uniformly formed, and finally, as shown in the third figure F. The negative photoresist layer 34 is removed. The example can further include a metal layer on the base layer 33 after the negative photoresist layer 34 is removed. In summary, as can be seen from the previous discussion, as shown in the fourth figure The basic process of the present invention includes: as shown in the protection block 41, a base layer above the label is protected by a protective layer located above the standard iron; as shown in the flattened block 42, 'the base layer and the protective layer are flattened at the same time, but At this time, a part of the base layer located on the protective layer ^ will not be affected and changed, so that the surface and surface profile of this part of the base layer are the same as the surface contour of the label. In other words, the basic spirit of the present invention is to form the label uniformly on the label. The top part of the base layer is Mushroom overlying sheath, so that by a planarization process (chemical mechanical polishing) of the top label portion of the surface profile 'layer is not changed. Soil

447109 V. Description of the invention (ίο) Comparing this invention with the two conventional methods commonly used in the prior art, we can see that the invention has several significant advantages: First, because the invention uses the protective layer to make the original wafer label The top surface of the top substrate is the same as the top surface of the original wafer label, so it can ensure that the effectiveness of the wafer label will not be damaged. 'Second', as each new substrate is formed, the original crystal can be replaced. The top surface of the round label is correctly copied to the base of the wound directly above the original wafer label, so it is not necessary to remove the original crystal as in conventional techniques (U.§. 5, go〗, 〇〇〇). The base layer above the circular label can use the original wafer label continuously. At this time, not only the extra lithography process and extra etching process required by the conventional technology can be saved, but also the impurities generated by peeling can be reduced. The possibility of reducing the yield rate. Third, although the present invention does not specifically limit the protection layer, if a negative photoresist layer is used as the protective layer, the wafer label covered by the negative photoresist layer is located at the edge of the wafer. , This can be achieved using the wafer edge exposure procedure provided by the photoresist coating developer, without the need to use a machine with a pad to form a metal layer (such as conventional technology (US 5, 456, 756)) (such as sputter), it is necessary to modify the structure of the machine. The above description is only a preferred embodiment of the present invention, and is not the scope of the patent application for the invention; any other changes or modifications that do not depart from the invention disclosed herein should be included in the patent application Within range. Jiaming

447109 on page 13 Schematic illustration of the first diagram A A diagram B is a schematic cross-sectional diagram illustrating the damage to the label of the wafer before and after the chemical mechanical polishing process; second diagram A to second E The figures are a series of schematic diagrams for explaining a preferred embodiment of the present invention; Figures A to F are a series of schematic diagrams for explaining another preferred embodiment of the present invention; and the fourth The figure is a basic flowchart of the present invention. Symbols of the main parts: 10 substrates 11 original wafer labels 12 base layers 13 new wafer labels 21 die 22 labels 23 substrates 24 base layers 25 protective layers 26 new labels 30 substrates

Page 14 447109 Brief description of the diagram 31 Die 32 Label 33 Base layer 34 Negative photoresist layer 41 Protective block 42 Flattened block

Claims (1)

447 1 〇9. Patent Application Fanyuan 1.-A method for protecting the label of a wafer, including at least the following basic steps: Ganzhan = supply-bottom seal 'The substrate has a plurality of grains and at least one Lu Rui among them The f particles do not overlap with the reading label; "Sign, evenly; ί on the substrate and cover the standard iron ... The base layer = a protective layer on the base layer, the protective layer only covers β and does not cover the Some grains; the label is duplicated in Ai e 1 and the base layer and the protective layer are damaged, so that the part is damaged; the protective layer is covered by the same surface profile, and the top surface of the layer The contour and the top of the label remove the protective layer. 2 The method described in item 1 of the patent fan park is composed of a plurality of lines, and the above-mentioned label in M is an alignment target. For example, the first method of the patent application park, which includes the above-mentioned base layer to 447709 6. The patent application park does not contain a metal layer. 6. The method described in item 5 of the patent application scope, wherein the gold on the upper side includes at least the crane layer β ^ As described in item 1 of the scope of patent application, The above-mentioned base layer includes a dielectric layer. ^ ^ The method described in item 7 of the scope of the patent application, wherein the upper layer includes at least an oxide layer. Electricity 9. The method described in the scope of the patent application , Where the above-mentioned at least includes a photoresist layer. Μ 10. The method as described in item 9 of the patent application scope, wherein the above-mentioned photoresist layer includes at least a negative photoresist layer. 11. As described in item 10 of the patent application scope Method, wherein the above-mentioned negative photoresist layer is formed by the base layer β 12 above the label through a wafer edge exposure process. The method as described in item 1 of the patent application range, wherein the above-mentioned planarization process Contains at least chemical mechanical grinding procedures. Page 17.4471 09 Γ ^ -—______ Patent application Fan Yuan, 3 · A method to protect wafer labels from failure due to chemical mechanical polishing 'This method includes at least the following basic steps: & supply a substrate The substrate has a plurality of crystal grains and at least one label, wherein the crystal grains and the label do not overlap; a base layer is formed on the substrate and the label is uniformly covered; and a negative photoresist layer is formed on the substrate. On the base layer; the negative photoresist layer is processed by a wafer edge exposure program so that the negative photoresist layer covers only the label; the base layer and the negative photoresist layer are simultaneously polished by a chemical mechanical polishing program where the label is The top part of the base layer is not covered by the CMP process because it is covered by the negative photoresist layer, so that the top surface profile of the base layer of the part is the same as the top surface profile of the label; and Remove the negative photoresist layer. 14. The method according to item 13 of the scope of patent application, wherein the above-mentioned label includes at least an alignment mark. 16. The method according to item 13 of the scope of patent application, wherein the above j includes at least a combination of a " '^ 乂 taken from—a wafer identification code 4471〇9 6. Scope of patent application 1 7. The method described in item 13 of the patent application park, wherein the above-mentioned wafer identification code has a width of about 9 mm and a length of about 20 mm. 18. A method according to item 13 of the scope of patent application, wherein said base layer includes at least a metal layer. 19. The method according to item 18 of the scope of patent application, wherein said metal layer includes at least a tungsten layer. 20. The method according to item 13 in the scope of the patent application, wherein the above-mentioned base 暦 includes at least a dielectric layer. 21. The method according to item 20 in the scope of the patent application, wherein the above-mentioned dielectric layer includes at least oxidation. Physical layer. 22. The method according to item 丨 3 of the scope of patent application, wherein the wafer edge exposure process described above is performed using a photoresist coating and developing machine. 23. The method according to item 13 of the scope of patent application, further comprising uniformly forming a samarium metal layer on the base layer after the negative photoresist layer is removed, so that the surface of the metal layer above the label The outline is the same as the surface profile of the label.