CN111415881A - Chip marking method, wafer and chip - Google Patents

Chip marking method, wafer and chip Download PDF

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Publication number
CN111415881A
CN111415881A CN201910058383.0A CN201910058383A CN111415881A CN 111415881 A CN111415881 A CN 111415881A CN 201910058383 A CN201910058383 A CN 201910058383A CN 111415881 A CN111415881 A CN 111415881A
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Prior art keywords
coordinate
wafer
symbols
symbol
forming
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车行远
吕景元
吕美蓉
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Powerchip Technology Corp
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Powerchip Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

A method for marking a wafer includes the following steps. A wafer is provided, wherein the wafer includes a plurality of chips. A plurality of exposure areas are divided on the wafer, wherein each exposure area corresponds to at least one of the plurality of chips. A plurality of first symbols on a first coordinate axis and a plurality of second symbols on a second coordinate axis in each wafer are formed using a first mask. And forming a coordinate symbol representing the coordinate of the exposure area in each wafer of each exposure area by using a second mask and an overlapped offset exposure mode, wherein different coordinate symbols in different exposure areas have different coordinates in a coordinate system formed by the first coordinate axis and the second coordinate axis.

Description

Chip marking method, wafer and chip
Technical Field
The present invention relates to a semiconductor process and structure, and more particularly, to a method for marking a chip, a wafer and a chip.
Background
In the chip testing stage before the wafer is not cut, the position information of each chip on the wafer can be clearly known, so that the relevant information in the manufacturing process can be easily grasped. However, if a problem occurs in the final test after the dicing and packaging of the wafer, it is difficult to grasp the relevant information.
Although the package can be numbered by the present package tester, the huge data generated by the package tester is often inconvenient to trace because each chip has a data record.
Disclosure of Invention
The invention provides a method. The present invention provides a marking method of chip, wafer and chip, which can easily grasp the relevant information of chip in the manufacturing process.
The invention provides a marking method of a wafer, which comprises the following steps. A wafer is provided, wherein the wafer includes a plurality of chips. A plurality of shot areas are divided on the wafer, wherein each shot area corresponds to at least one of the plurality of chips. A plurality of first symbols on a first coordinate axis and a plurality of second symbols on a second coordinate axis in each wafer are formed using a first mask. And forming a coordinate symbol representing the coordinates of the exposure area in each wafer of each exposure area by using a second mask and overlay shift (overlay shift) exposure manner, wherein different coordinate symbols in different exposure areas have different coordinates in a coordinate system formed by the first coordinate axis and the second coordinate axis.
According to an embodiment of the present invention, in the marking method for a wafer, the first symbol, the second symbol and the coordinate symbol may be located in a same layer in the wafer.
According to an embodiment of the present invention, in the marking method of the wafer, the first symbol and the second symbol may be located in the same layer in the wafer, and the first symbol and the coordinate symbol may be located in different layers in the wafer.
According to an embodiment of the present invention, in the above method for marking a wafer, the coordinate symbol can be located in a coordinate system as viewed from above.
According to an embodiment of the present invention, in the marking method of the wafer, the first symbol and the second symbol may be formed first, and then the coordinate symbol may be formed.
According to an embodiment of the present invention, in the marking method of the wafer, the coordinate symbol may be formed first, and then the first symbol and the second symbol may be formed.
According to an embodiment of the invention, in the marking method of the wafer, the forming method of the first symbol and the second symbol may include performing a patterning process on the film by using a first mask.
According to an embodiment of the invention, in the marking method of the wafer, the method for forming the coordinate symbol may include performing a patterning process on the film using a second mask.
According to an embodiment of the present invention, in the marking method of the wafer, the first mask may include a pattern for forming the first symbol and a pattern for forming the second symbol.
According to an embodiment of the present invention, in the method for marking a wafer, the first mask may further include at least one of a pattern for forming a wafer number and a pattern for forming an element.
According to an embodiment of the present invention, in the marking method of a wafer, the second mask may include a pattern for forming a coordinate symbol.
According to an embodiment of the present invention, in the marking method of the wafer, the device may be formed by a film for forming a coordinate symbol, and the photolithography process for forming the coordinate symbol and the device may include the following steps. A photoresist layer is formed on the film layer. The photoresist layer is exposed using a second mask for forming a coordinate symbol and a mask for forming a device, respectively. And developing the photoresist layer after the exposure process.
According to an embodiment of the present invention, in the marking method of the wafer, the first symbol and the second symbol may include a plurality of numbers which are incremented.
According to an embodiment of the present invention, in the marking method of the wafer, the number of the coordinate symbols may be one.
According to an embodiment of the present invention, in the marking method of the wafer, the number of the coordinate symbols may be plural.
According to an embodiment of the present invention, in the marking method of the wafer, the shape of the coordinate symbol is, for example, L shape, dot shape, polygon shape, or a combination thereof.
According to an embodiment of the invention, in the marking method of the wafer, the first symbol, the second symbol and the coordinate symbol may be located in an open area of the wafer.
According to an embodiment of the present invention, in the marking method of the wafer, the coordinate system may be a rectangular coordinate system.
The invention provides a wafer, which comprises a plurality of chips. The wafer has a plurality of exposure areas, and each exposure area corresponds to at least one of the plurality of dies. In each wafer, there are a plurality of first symbols on a first coordinate axis, a plurality of second symbols on a second coordinate axis, and a coordinate symbol representing the coordinates of the exposure area. The different coordinate symbols in the different exposure areas have different coordinates in a coordinate system formed by the first coordinate axis and the second coordinate axis.
The invention provides a wafer. In each wafer, there are a plurality of first symbols on a first coordinate axis, a plurality of second symbols on a second coordinate axis, and a coordinate symbol representing the coordinates of the exposure area.
Based on the above, in the marking method for wafer provided by the present invention, the first mask is used to form the first symbol on the first coordinate axis and the second symbol on the second coordinate axis, and the second mask and the overlay offset exposure method are used to form the coordinate symbol representing the coordinate of the exposure area in the wafer of the exposure area, and different coordinate symbols in different exposure areas have different coordinates in the coordinate system. Therefore, even after the chip is cut and packaged, the position information of the corresponding exposure area can be known from the exposure area coordinate of the chip, thereby easily grasping the relevant information of the chip in the manufacturing process. In addition, the marking method of the wafer can omit the step of marking numbers on the package, thereby saving the cost of entrusting a package testing factory to mark numbers on the package. In addition, the wafer and the chip provided by the invention have the first symbol on the first coordinate axis, the second symbol on the second coordinate axis and the coordinate symbol representing the coordinate of the exposure area, thereby easily grasping the relevant information of the chip in the manufacturing process.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a flowchart illustrating a method for marking a wafer according to an embodiment of the invention.
Fig. 2A to 2C are diagrams of an exposure region (shop map) of a wafer during an exposure process according to an embodiment of the invention.
Fig. 3 is an enlarged view of the exposure area in fig. 2A to 2C.
Fig. 4A to 4C are enlarged views of an empty region in a wafer.
FIGS. 5A and 5B are enlarged views of an open region in a wafer according to another embodiment of the present invention.
Detailed Description
Fig. 1 is a flowchart illustrating a method for marking a wafer according to an embodiment of the invention. Fig. 2A to 2C are exposure area diagrams of a wafer undergoing an exposure process according to an embodiment of the invention. Fig. 3 is an enlarged view of the exposure area in fig. 2A to 2C. Fig. 4A to 4C are enlarged views of an empty region in a wafer. FIGS. 5A and 5B are enlarged views of an open region in a wafer according to another embodiment of the present invention.
Referring to fig. 1, step S100 is performed to provide a wafer W, wherein the wafer W includes a plurality of chips 100.
Step S102 is performed to divide a plurality of exposure regions S on the wafer W, wherein each exposure region S corresponds to at least one of the plurality of dies 100. In the present embodiment, the exposure region S is defined as a region where a single exposure is performed on the wafer W through the mask. In the exposure field diagram 200 of fig. 2A to 2C, each exposure field S is set to correspond to eight wafers 100 for illustration, but the invention is not limited thereto. It is within the scope of the present invention that the exposure area S corresponds to at least one wafer 100. In addition, each exposure area S has corresponding exposure area coordinates on the exposure area map 200, and the exposure area coordinates of the exposure area S can be used to represent the position of the exposure area S on the wafer W.
For example, referring to fig. 2A, in the exposure area diagram 200, the X coordinate of the exposure area coordinate of the circled exposure area S is 4 and the Y coordinate is 2. On the exposure region map 200 of fig. 2B, the exposure region coordinates of the circled exposure region S have an X coordinate of 9 and a Y coordinate of 3. On the exposure region diagram 200 of fig. 2C, the exposure region coordinates of the circled exposure region S have an X coordinate of 10 and a Y coordinate of 6. In addition, the wafers 100 in a single exposure area S may be numbered. Taking FIG. 3 as an example, the numbers of the wafers 100 in the exposure area S may be respectively one of "A" to "H".
Referring to fig. 1 and fig. 4A to 4C, step S104 is performed to form a plurality of first symbols S1 on the first coordinate axis and a plurality of second symbols S2 on the second coordinate axis in each wafer 100 by using a first mask. The first mask may include a pattern for forming the first symbol S1 and a pattern for forming the second symbol S2. In addition, the first mask may further include at least one of a pattern for forming the wafer number SS and a pattern for forming the elements.
In addition, the forming methods of the first symbol S1, the second symbol S2, the wafer number SS and the device may include performing a patterning process on the film using a first mask. For example, the patterning process may include performing a photolithography process and an etching process on the film. In some embodiments, the patterning process may further include performing an ion implantation process on the film to assist the etching process. The layer may be any layer in the wafer 100, such as a top metal layer (top metal layer), a silicon oxide layer, or a passivation layer (passivation layer). The first symbol S1, the second symbol S2, the chip number SS and the device can be formed by the same layer. The first symbol S1, the first symbol S2 and the chip number SS may be an opening or a solid pattern formed by patterning the film layer. In addition, the device may be in the form of a solid pattern or an opening formed by patterning the film.
Referring to fig. 3, each wafer 100 may include an open region R1 and a device region R2. The open region R1 is, for example, a region of the wafer 100 having no elements. The first symbol S1, the second symbol S2, and the chip number SS may be located in the open region R1 of the chip 100, and a device (not shown) may be located in the device region R2 of the chip 100.
FIGS. 4A-4C show the open region R1 of the wafer 100 in the exposure area S selected in FIGS. 2A-2C, and the open region R1 of the wafer 100 numbered "A" is taken as an example for explanation.
Referring to fig. 4A to 4C, the first coordinate axis and the second coordinate axis may form a coordinate system. For example, the coordinate system may be a rectangular coordinate system, and the first coordinate axis and the second coordinate axis may be one and the other of an X axis and a Y axis of the rectangular coordinate system, respectively, but the invention is not limited thereto. In the present embodiment, the first coordinate axis is an X axis, and the second coordinate axis is a Y axis.
Further, the first symbol S1 may include a plurality of numbers increasing on the X-axis, and may further include a letter "X" for representing the X-axis. The second symbol S2 may be an increasing number of digits on the Y-axis, and may further include the word "Y" for representing the Y-axis. The wafer number SS includes numbers corresponding to the wafers 100 in the exposure field S, such as letters "a" to "H". In fig. 4A to 4C, the wafer number SS is described by taking the character "a" as an example. That is, in FIGS. 4A to 4C, the wafer 100 numbered "A" in the exposure region S is taken as an example. The elements may comprise wires or openings etc.
Referring to fig. 1 and fig. 4A to 4C, step S106 is performed to form a coordinate symbol SC representing coordinates of the exposure area in each wafer 100 of each exposure area S by using a second mask and an overlay offset exposure method, wherein different coordinate symbols SC in different exposure areas S have different coordinates in a coordinate system formed by a first coordinate axis and a second coordinate axis. The second mask is different from the first mask. The coordinate symbol SC may be located in the open region R1 of the wafer 100. The second mask may comprise a pattern for forming the coordinate symbol SC.
In addition, the method for forming the coordinate symbol SC includes using a second mask to perform a patterning process on the film. For example, the patterning process may include performing a photolithography process and an etching process on the film. In some embodiments, the patterning process may further include performing an ion implantation process on the film to assist the etching process. The film layer may be any film layer in the wafer 100, such as the uppermost metal layer, a silicon oxide film layer, or a passivation layer. Further, the element may be formed by a film layer for forming the coordinate symbol SC. The type of the coordinate symbol SC may be an opening or a solid pattern formed by patterning the film. In addition, the device may be in the form of a solid pattern or an opening formed by patterning the film.
In addition, the photolithography process for forming the coordinate symbols SC and the device may include the following steps. A photoresist layer is formed on the film layer. Then, the photoresist layer is exposed using a second mask for forming the coordinate symbol SC and a mask for forming the elements, respectively. In one embodiment, the photoresist layer may be exposed using the second mask for forming the coordinate symbol SC, and then the photoresist layer may be exposed using the mask for forming the device. In another embodiment, the photoresist layer may be exposed using a mask for forming the device, and then the photoresist layer may be exposed using a second mask for forming the coordinate symbol SC. Then, the photoresist layer after the exposure process is developed.
Referring to fig. 2A to 2C and 4A to 4C, when the photoresist layer is exposed using a mask for forming devices, the photoresist layer in each exposure region S on the wafer W may be exposed in a conventional manner. In addition, when the photoresist layer is exposed using the second mask for forming the coordinate symbol SC, the photoresist layer in each exposure region S on the wafer W may be exposed using an overlay shift exposure method. In detail, the exposure mode of the overlay shift refers to that after one exposure region S is exposed, the position of the second mask relative to the exposure region S is changed, and then the next exposure region S is exposed.
For example, when the exposure regions S having the same Y coordinate are exposed, the second mask is set so as to be shifted by one unit line by line in the X direction with respect to the position of the exposure region S. When exposure regions S having the same X coordinate are exposed, the second mask is set so as to be shifted by one unit line by line in the Y direction with respect to the position of the exposure regions S. Therefore, after the second mask is used for patterning the film layer, different coordinate symbols SC in different exposure areas S can have different coordinates.
In addition, in the above-mentioned manner, the coordinate symbol SC can be located in the coordinate system, so that the exposure area coordinates of each wafer 100 can be obtained. As shown in the circles of fig. 2A and 4A, a coordinate symbol SC may be formed in the wafer 100 in the exposure region S having an X coordinate of 4 and a Y coordinate of 2 by using the second mask and the overlay offset exposure method, and the X coordinate of the coordinate symbol SC is 4 and the Y coordinate is 2. As shown in the circles of fig. 2B and 4B, a second mask and an overlay offset exposure method may be used to form a coordinate symbol SC with an X coordinate of 9 and a Y coordinate of 3 in the wafer 100 of the exposure region S, and the X coordinate of the coordinate symbol SC is 9 and the Y coordinate is 3. As shown in the circles of fig. 2C and 4C, a second mask and an overlay offset exposure method may be used to form a coordinate symbol SC with an X coordinate of 10 and a Y coordinate of 6 in the wafer 100 of the exposure region S, and the X coordinate of the coordinate symbol SC is 10 and the Y coordinate is 6.
In addition, the number of the coordinate symbols SC may be one or more, the shape of the coordinate symbols SC is, for example, L-shaped, dotted, polygonal or a combination thereof, but the present invention is not limited thereto, as long as the shape of the coordinate symbols SC can clearly indicate that the X-coordinate and the Y-coordinate belong to the scope covered by the present invention, in the present embodiment, the coordinate symbols are one, and the shape of the coordinate symbols SC is L-shaped, in the case that the shape of the coordinate symbols SC is L-shaped, both sides of the coordinate symbols SC of L-shaped can respectively point to a first symbol S1 (e.g., the number "4" in FIG. 4A) and a second symbol S2 (e.g., the number "2" in FIG. 4A) on the X-axis, and the number of the coordinate symbols SC2 on the Y-axis, in some embodiments, the number of the coordinate symbols SC1 and SC2 can have different shapes (e.g., the triangle and the rectangle shown in FIG. 5A) or the number of the coordinate symbols SC1 and SC2 can have the same shape (e.g., the same coordinate symbols shown in FIG. 5B) and the coordinates of X-coordinate symbols SC 5A, the coordinate symbols, e.g., the coordinates of SC 5B, the coordinates can be indicated as SC 5A, and the coordinates indicated by numeral "5B", and the coordinates indicated by numeral coordinates indicated by SC 5B, and coordinates indicated.
In one embodiment, the first symbol S1 and the second symbol S2 are formed first, and then the coordinate symbol SC is formed. In another embodiment, the coordinate symbol SC may be formed first, and then the first symbol S1 and the second symbol S2 may be formed. That is, the above steps S104 and S106 are not in a certain sequence, and the technical field can be adjusted according to the process design.
In addition, the first symbol S1, the second symbol S2, and the coordinate symbol SC may be located in the same layer in the wafer 100. For example, the first symbol S1, the second symbol S2, and the coordinate symbol SC may be located in the uppermost metal layer of the wafer 100 at the same time. In addition, at least one of the wafer number SS and required elements (e.g., wires) may be further included in the uppermost metal layer. The first symbol S1, the second symbol S2, the coordinate symbol SC, and the chip number SS may be located in the open region R1 of the chip 100, and the device may be located in the device region R2 of the chip 100.
In this case, the first symbol S1, the second symbol S2, the coordinate symbol SC, the wafer number SS and the method for forming the device may include the following steps, but the invention is not limited thereto. First, an uppermost metal layer is formed. Then, a photoresist layer is formed on the uppermost metal layer. Then, an exposure process is performed on the photoresist layer through a first mask. The first mask may include a pattern for forming the first symbol S1 and a pattern for forming the second symbol S2, and may further include a pattern for forming the wafer number SS and a pattern for forming elements. Then, an exposure process is performed on the photoresist layer by using a second mask and an exposure method with overlay offset. The second mask may comprise a pattern for forming the coordinate symbol SC. Then, the photoresist layer after the exposure process is developed to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask, an etching process is performed on the uppermost metal layer to form a first symbol S1, a second symbol S2, a coordinate symbol SC, a wafer number SS and a device. Then, the patterned photoresist layer is removed.
In some embodiments, the first symbol S1 and the second symbol S2 may be located in the same layer in the wafer 100, and the first symbol S1 and the coordinate symbol SC may be located in different layers in the wafer 100. In one embodiment, the first symbol S1 and the coordinate symbol SC may be located at a lower layer, and the coordinate symbol SC may be located at an upper layer. In another embodiment, the first symbol S1 and the coordinate symbol SC may be located at an upper layer, and the coordinate symbol SC may be located at a lower layer.
For example, the first symbol S1 and the second symbol S2 may be located in the uppermost metal layer of the wafer 100 at the same time, and the coordinate symbol SC may be located in the passivation layer above the uppermost metal layer, but the invention is not limited thereto. In addition, at least one of the wafer number SS and the required first elements (e.g., conductive lines) may be further included in the uppermost metal layer, and the required second elements (e.g., openings) may be further included in the protection layer. The first symbol S1, the second symbol S2, the coordinate symbol SC, and the chip number SS may be located in the open region R1 of the chip 100, and the first element and the second element may be located in the element region R2 of the chip 100.
In this case, the first symbol S1, the second symbol S2, the coordinate symbol SC, the wafer number SS, the first element and the second element may be formed by the following steps, but the invention is not limited thereto. First, an uppermost metal layer is formed. Then, a patterning process is performed on the uppermost metal layer using a first mask to form a first symbol S1, a second symbol S2, a wafer number SS and a first element. The patterning process is, for example, a photolithography process and an etching process performed on the uppermost metal layer. The first mask may include a pattern for forming the first symbol S1 and a pattern for forming the second symbol S2, and may further include a pattern for forming the wafer number SS and a pattern for forming the first element. Then, a protective layer is formed on the patterned uppermost metal layer. Then, a photoresist layer is formed on the protective layer. Then, an exposure process is performed on the photoresist layer through a mask for forming the second element. The mask may include a pattern for forming the second element. Then, an exposure process is performed on the photoresist layer by using a second mask and an exposure method with overlay offset. The second mask may comprise a pattern for forming the coordinate symbol SC. That is, the exposure process for forming the second element and the exposure process for forming the coordinate symbol SC are performed using different masks. Then, the photoresist layer after the exposure process is developed to form a patterned photoresist layer. Then, using the patterned photoresist layer as a mask to perform an etching process on the passivation layer to form a coordinate symbol SC and a second element. Then, the patterned photoresist layer is removed.
As can be seen from the above embodiments, in the marking method of the wafer 100, the first symbol S1 on the first coordinate axis and the second symbol S2 on the second coordinate axis are formed by using the first mask, and the coordinate symbol SC representing the coordinates of the exposure area in the wafer 100 of the exposure area S is formed by using the second mask and the exposure manner of the overlay offset, and different coordinate symbols SC in different exposure areas have different coordinates in the coordinate system. Therefore, even after the wafer is diced and packaged, the position information of the corresponding exposure area S can be known from the exposure area coordinates of the wafer 100 without going through the package number, so that the related information of the wafer 100 in the manufacturing process can be easily grasped. In addition, the marking method of the wafer 100 can omit the step of marking numbers on the packages, thereby saving the cost of entrusting a package testing factory to mark numbers on the packages.
Hereinafter, the wafer W and the chip 100 of the above embodiment are described with reference to fig. 2A to 2C and fig. 4A to 4C. In addition, although the above method is used as an example of the method for marking the chips 100 on the wafer W, the invention is not limited thereto.
Referring to fig. 2A to 2C and fig. 4A to 4C, the wafer W includes a plurality of chips 100. The wafer 100 has a plurality of exposure areas S, and each exposure area S corresponds to at least one of the plurality of chips 100. In each wafer 100, there are a plurality of first symbols S1 on the first coordinate axis, a plurality of second symbols S2 on the second coordinate axis, and a coordinate symbol SC representing the coordinates of the exposure area. The different coordinate symbols SC in the different exposure areas S have different coordinates in a coordinate system formed by the first coordinate axis and the second coordinate axis. In addition, the details of the wafer W and the chip 100 can refer to the above embodiments, and the description thereof is not repeated.
Based on the above embodiments, in the wafer W and the chip 100 of the above embodiments, the first symbol S1 on the first coordinate axis, the second symbol S2 on the second coordinate axis, and the coordinate symbol SC representing the coordinates of the exposure area are provided, so that the related information of the chip 100 during the manufacturing process can be easily grasped.
In summary, in the marking method of the chip, the wafer and the chip of the above embodiments, the exposure area coordinates indicated by the coordinate symbol in the chip can easily grasp the related information of the chip in the manufacturing process, and the manufacturing cost of the product can be reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
[ description of symbols ]
100: wafer with a plurality of chips
200: exposure region diagram
A to H: numbering
R1: open area
R2: device region
S: exposure area
S1: first symbol
S2: second symbol
S100, S102, S104, S106: step (ii) of
SC, SC1, SC 2: coordinate symbol
And SS: wafer numbering
W: wafer

Claims (20)

1. A method of marking a wafer, comprising:
providing a wafer, wherein the wafer comprises a plurality of chips;
dividing a plurality of exposure areas on the wafer, wherein each exposure area corresponds to at least one of the plurality of chips;
forming a plurality of first symbols on a first coordinate axis and a plurality of second symbols on a second coordinate axis in each wafer by using a first mask; and
and forming a coordinate symbol representing the coordinate of the exposure area in each wafer of each exposure area by using a second mask and an overlapped offset exposure mode, wherein different coordinate symbols in different exposure areas have different coordinates in a coordinate system formed by the first coordinate axis and the second coordinate axis.
2. The method of marking wafers of claim 1 wherein the plurality of first symbols, the plurality of second symbols and the coordinate symbol are located in the same layer in each wafer.
3. The method of marking wafers of claim 1 wherein the plurality of first symbols and the plurality of second symbols are in the same layer in each wafer and the plurality of first symbols and the coordinate symbols are in different layers in each wafer.
4. A method of marking a wafer as recited in claim 1, wherein the coordinate sign bit is in the coordinate system viewed in elevation.
5. The method of marking a wafer as claimed in claim 1, wherein the first symbols and the second symbols are formed first, and then the coordinate symbols are formed.
6. The method of marking a wafer as claimed in claim 1, wherein the coordinate symbols are formed first, and then the plurality of first symbols and the plurality of second symbols are formed.
7. The method according to claim 1, wherein the forming of the first and second symbols comprises patterning a film using the first mask.
8. The method according to claim 1, wherein the coordinate symbol forming method comprises patterning a film using the second mask.
9. The method of marking a wafer as claimed in claim 1, wherein the first mask includes a pattern for forming the plurality of first symbols and a pattern for forming the plurality of second symbols.
10. The method of marking a wafer as claimed in claim 9, wherein the first mask further comprises at least one of a pattern for forming a wafer number and a pattern for forming a component.
11. The method of marking a wafer as claimed in claim 1, wherein the second mask includes a pattern for forming the coordinate symbol.
12. The method of marking a wafer as claimed in claim 1, wherein elements are formed through a layer for forming the coordinate symbols, and the lithography process for forming the coordinate symbols and the elements comprises:
forming a photoresist layer on the film layer;
respectively using the second mask for forming the coordinate symbol and the mask for forming the element to carry out exposure process on the photoresist layer; and
and developing the photoresist layer after the exposure process.
13. The method of marking a wafer of claim 1, wherein the plurality of first symbols and the plurality of second symbols comprise a plurality of numbers that are incremented.
14. The method of marking a wafer as claimed in claim 1, wherein the number of the coordinate symbols is one.
15. The method of marking a wafer as claimed in claim 1, wherein the number of the coordinate symbols is plural.
16. The method of marking a wafer as claimed in claim 1, wherein the shape of the coordinate symbol comprises L shapes, dots, polygons, or combinations thereof.
17. The method of marking wafers of claim 1 wherein the plurality of first symbols, the plurality of second symbols and the coordinate symbols are located in an open area of each wafer.
18. The method for marking a wafer as recited in claim 1, wherein the coordinate system comprises a rectangular coordinate system.
19. A wafer comprises multiple chips, wherein
The wafer has a plurality of exposure areas, and each exposure area corresponds to at least one of the plurality of chips,
in each wafer, there are a plurality of first symbols on a first coordinate axis, a plurality of second symbols on a second coordinate axis, and coordinate symbols representing the coordinates of the exposure area, and
different coordinate symbols in different exposure areas have different coordinates in a coordinate system formed by the first coordinate axis and the second coordinate axis.
20. A wafer has a plurality of first symbols on a first coordinate axis, a plurality of second symbols on a second coordinate axis, and a coordinate symbol representing a coordinate of an exposure area in each wafer.
CN201910058383.0A 2019-01-07 2019-01-22 Chip marking method, wafer and chip Pending CN111415881A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108100515 2019-01-07
TW108100515A TW202027189A (en) 2019-01-07 2019-01-07 Method of marking die, wafer and die

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CN102156392A (en) * 2010-02-11 2011-08-17 中芯国际集成电路制造(上海)有限公司 Device and method for detecting alignment parameter of photoetching machine
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JP2004077898A (en) * 2002-08-20 2004-03-11 Topcon Corp Exposing method and exposure device
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