KR960014961B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

compensating the die-to-die alignment of the neighboring first dies(33) by forming a first rectangular alignment mark(35) inside of the four corners of the first die(33) formed by the first exposure using a first pattern mask; and compensating the die-to-die or layer-to-layer misalignment by forming a second rectangular alignment mark(36) of different size with the first mark(35) at the position overlapped with the first alignment mark(35) inside the four corners of a second die(34) formed by the second exposure using a second pattern mask different from the first pattern mask.

Description

Manufacturing Method of Semiconductor Device

1 is a schematic diagram for explaining mask misalignment between dies using a conventional alignment mark.

2 is a schematic diagram for explaining an interlayer mask misalignment using a conventional alignment mark.

3a and b are plan views of dies in which the first and second alignment measurement marks according to the invention are formed;

4 is a plan view of the dies aligned by the first and second alignment marks of FIG.

* Explanation of symbols for main parts of the drawings

11, 21: semiconductor substrate 13, 23, 33, 34: die

15, 25: wiring 27: contact hole

29: exposure mask pattern 35, 36: measurement mark

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, an alignment mark used to measure an alignment state of an exposure mask during alignment of an exposure mask for forming a photoresist pattern is formed in a rectangular shape having a predetermined size inside a boundary of a die corner. The present invention relates to a method for manufacturing a semiconductor device which can improve the yield and reliability by correcting the alignment between four adjacent dies and also using the alignment of an interlayer mask.

In general, a plurality of exposure masks of a semiconductor device, for example, 4M DRAM, go through a complicated process of overlapping 12 exposure masks, and the alignment between the exposure masks used step by step is made based on a mark of a specific shape. The mark used at this time is called an alignment key or alignment mark.

The alignment mark is used for alignment between different exposure masks (hereinafter referred to as "layer to layer alignment") or between dies for one exposure mask.

Here, the die refers to the entire region formed by one exposure process, and a plurality of semiconductor chips may be included in one die.

A stepper, which is a step and repeat type exposure equipment used in a semiconductor device manufacturing process, is a device in which a stage moves in the X-Y direction and repeatedly moves in alignment. The stage is aligned with the wafer automatically or manually based on the alignment mark, the alignment error is generated by the mechanical movement of the stage, the device failure occurs when the alignment error exceeds the allowable range.

The conventional alignment mark is formed on a scribeline, which is a portion where a semiconductor chip is not formed on the wafer, and a visual inspection method using a venier alignment mark as a method of measuring the degree of misalignment using the alignment mark, There is an automatic check using a box in box or bar in bar alignment mark.

In the case of the die-to-die alignment in the above, as shown in FIG. 1, the width of the misalignment increases as the distance from the die 13 first exposed on the semiconductor substrate 11 along the arrow direction increases. That is, the portion indicated by the solid line in FIG. 1 is the boundary line of the die 13 at the ideal position to be formed, and the portion indicated by the dotted line is the boundary line of the actual die 13 formed by misalignment.

In the case of the interlayer alignment, the contact holes 27 are formed between the wirings formed on the semiconductor substrate 21 at regular intervals, for example, the metal wirings 25, as shown in FIG. ), The exposure mask pattern 29 for forming is misaligned. That is, the area of the contact hole 27 indicated by the solid line in FIG. 2 is misaligned with the exposure mask pattern 29 indicated by the dotted line.

As described above, the adjustment range of the overlapping accuracy due to misalignment depends on the design rule of the device, and is usually about 20 to 30% of the design rule. However, the conventional interlayer or die-to-die alignment marks formed on the scribe lines are inaccurate as the exposure process is performed several times, and the misalignment is corrected by measuring the different alignment marks between the die alignment and the interlayer alignment. There is a complex problem.

The present invention is to solve the above problems, an object of the present invention is to form an alignment mark between the different dies by forming a rectangular alignment mark of different sizes for each exposure mask inside the boundary line of the die square formed in one exposure process, The present invention provides a method of manufacturing a semiconductor device that can simultaneously improve interlayer alignment to improve yield and reliability.

A feature of the semiconductor device manufacturing method according to the present invention for achieving the above object is a method of manufacturing a semiconductor device in which a photosensitive film pattern is formed by performing interlayer or die-die exposure with a stepper, by one exposure. There is provided a semiconductor device manufacturing method capable of simultaneously correcting alignment and interlayer misalignment between adjacent dies by forming an alignment mark having a predetermined size on a corner of a die to be formed.

EMBODIMENT OF THE INVENTION Hereinafter, the manufacturing method of the semiconductor device which concerns on this invention is demonstrated in detail with reference to an accompanying drawing.

3 and 4 are views for explaining an alignment mark according to the present invention, and two patterns of a plurality of patterns are described by way of example, and are described in association with each other, and like reference numerals denote like reference numerals. .

First, first alignment marks 35 having a predetermined shape, for example, a square shape having a length of one side of 10 μm are formed inside the boundary line of the first edge 33 formed by the first exposure process. Inside the boundary line of the second die 34 square formed by the second exposure process, square second alignment marks 36 having a predetermined shape, for example, a length of one side of 5 μm, are formed. See also 3a and b)

The alignment process using the alignment marks 35 and 36 is as follows.

First, alignment between dies is performed by measuring each of the four adjacent first dies 33 by matching the first alignment marks 35 of the first dies 33 with the adjacent first alignment marks 35 using a stepper. Exposure is repeatedly performed so that the marks coincide with each other to form a square of 20 mu m.

Then, the second dies 34 overlapping the first dies 33 are repeatedly formed in the same die-to-die alignment method as the first dies 33 so that the four second alignment marks 36 are aligned. A square having one side of 10 μm is formed at a central portion of the square formed by the first alignment marks 35. In this case, the alignment between the first die 33 and the second die 34 may be corrected so that the boundary lines between the dies of the center portions of the quadrangle formed by the first and second alignment marks 35 and 36 are completely coincident with each other. (See Figure 4.)

Therefore, the alignment between the adjacent dies 33 and 34 or the alignment between the first die 33 and the second die 34 may be simultaneously achieved by rectangular alignment marks having different lengths on one side between the exposure masks.

As described above, the method for manufacturing a semiconductor device according to the present invention includes a first method formed by a primary exposure process in an exposure process for a photosensitive film pattern shape of a stepper in which one exposure mask is moved on a wafer and a plurality of side exposure processes are performed. A first alignment mark having a square shape having one side is formed inside the boundary line of the die square, and one side is overlapped with the first alignment mark inside the boundary line of the second die edge formed using another exposure mask. Since a second alignment mark having a square shape having different lengths is formed, the alignment between the dies can be corrected by matching the square first or second alignment marks, respectively, and the first and second alignment marks having different sizes. Is aligned so that the die-to-die borders of the center portions coincide with each other, thereby improving interlayer alignment to improve the yield and reliability of the semiconductor device. Is effective.

Claims (1)

In the method of manufacturing a semiconductor device in which an interlayer or die-die exposure is performed by a stepper to form a pattern, a rectangular shape is formed inside the boundary line of the corners of the first die formed by the first exposure using the first pattern mask. Forming a first alignment mark to correct alignment between adjacent first dies, and using a second pattern mask different from the first pattern mask to form an inner edge of the edge of the second die formed by the second exposure; And forming a square second alignment mark at a position different from the first alignment mark at a position overlapping with the first alignment mark, to correct die and interlayer misalignment.