JPH0258777B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for comparing and inspecting IC patterns on masks used in the manufacture of semiconductor integrated circuits (ICs).

(2) Background of the technology In the IC manufacturing process, a mask is used to create identical patterns on the wafer, but recent high-density IC manufacturing requires features such as high resolution and high-precision alignment. Motsu wafer steppers have been used. In Fig. 1, a wafer 1 is shown in a schematic plan view, in which the same pattern of parts 2 arranged in a grid is formed, and when all the wafer processes are completed, the wafer is cut and separated into parts 2. is,
Each one is called a semiconductor chip or die.

In a typical example of such a process, a photoresist film is applied and formed on the entire surface of the wafer, the pattern on the reticle mask is exposed by reduction projection, the entire surface is exposed by repeating the baking of one or several chips worth of IC patterns, and then developed. After processing, etching is performed to form a large number of IC patterns on the wafer in accordance with the patterns on the reticle mask. In normal IC manufacturing, at least 10 types of masks are prepared, and wafer processing is performed in accordance with each mask.

(3) Prior art and problems IC patterns on masks are repeatedly printed onto hundreds of wafers. If this mask becomes dirty or scratched, or if there are stains caused by drying water droplets left on the mask when it is rinsed, it will reappear on the many IC patterns on the wafer. Such IC pattern defects must be avoided by inspecting the IC pattern on the wafer.

Generally, the presence or absence of an IC pattern on a wafer, that is, whether there is an excess of the pattern or a part of the pattern is missing, is conventionally determined by forming a resist film on the wafer, baking, developing, or further etching. The pattern formed by such processing is visually inspected using a microscope.

Such inspection requires more time as the pattern becomes more complex, and even if it is inspected, there is no standard pattern (correct pattern) to compare and contrast with, so it is difficult to determine whether the IC pattern on the wafer is correct or not. It is difficult to judge.

(4) Purpose of the invention In view of the above-mentioned conventional problems, the present invention provides a
The purpose of the present invention is to provide a method that enables accurate and easy comparative inspection of IC patterns.

(5) Structure of the Invention According to the present invention, a reference pattern is formed in advance on a specific wafer, and an IC pattern is formed at a position adjacent to the reference pattern by a predetermined IC manufacturing process. This is accomplished by providing a method for forming and comparing and testing these two patterns.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

As mentioned above, in the IC manufacturing process, a number of masks are prepared, each of which has a specific IC pattern. Therefore, a reference pattern (correct pattern) is created for a specific mask.
Here, how to determine the correct pattern can be determined by testing the product to see whether or not a product with a certain pattern produces the designed results. It can be carried out by the usual manufacturing process.

The above-mentioned reference pattern schematically shown in FIG. 2 is formed, for example, in a portion (reference pattern portion) 12 arranged in a checkered pattern on the wafer 11. This reference pattern is applied to the wafer by exposure, development, and
It was created by actually performing processes such as etching. In the same figure, reference numeral 13 indicates a portion (pattern to be inspected) where no reference pattern is formed and a pattern to be inspected later is formed. Second
Wafers as shown in the figure are prepared for each mask.

In IC manufacturing, for example, if reticle mask a is used in step A, printing is performed on a large number of wafers by repeating reduction projection exposure using mask a using a so-called wafer stepper. Here, if it is desired to inspect whether or not a correct pattern is formed by mask a, the wafer 11 on which the reference pattern shown in FIG. lot (e.g.
50 wafers make up one lot).
A photoresist film is coated on the wafer 11 in the same way as on other wafers.

For a normal wafer, a pattern is projected and created on the entire surface as shown in FIG. exposed to light. Next, a predetermined development is performed to form an IC pattern in the pattern portion 13 to be inspected.

Next, the reference pattern and the test pattern are compared and tested. This inspection is performed using a mechanical comparison inspection machine or an optical inspection machine that optically inspects both patterns by superimposing them. Whether by mechanical or optical inspection, inspection machines for this purpose are commercially available, so a detailed description of the inspection machines will be omitted.

In the above comparison inspection, since the reference pattern and the pattern to be inspected are located next to each other, there is an advantage that the comparison inspection can be performed accurately and easily regardless of which device is used. Note that the arrangement of the reference patterns is not limited to the checkered pattern shown in Figure 2; They may be arranged side by side. The key is to arrange the pattern to be inspected so that it is formed immediately adjacent to the reference pattern.

(7) Effects of the Invention As explained in detail above, when the method of the present invention is used, a wafer for IC manufacturing is used, and by making preparations for forming a reference pattern on it, the pattern can be formed in the manufacturing process. Comparative inspection of IC patterns can be performed accurately and easily, which is highly effective in reducing the rate of defective products in IC manufacturing.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing an IC pattern formed on a wafer, and FIG. 2 is a schematic plan view of a wafer on which a reference pattern used in carrying out the method of the present invention is formed. 11... Wafer, 12... Reference pattern portion, 13
...Pattern part to be inspected.

Claims (1)

[Claims] 1. A method for inspecting an integrated circuit pattern made using a wafer stepper in a semiconductor device integrated circuit forming process, in which a reference wafer for inspection is formed by selectively arranging reference pattern portions on which accurate reference patterns are formed. 1. A pattern comparison inspection method, comprising: preparing a reference wafer, forming an integrated circuit pattern on a portion adjacent to the reference pattern portion of the reference wafer, and comparing and inspecting these two patterns.