JPH06181169A - Aligner and fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To increase production yield of semiconductor device by realizing high aligning accuracy even for a process having significant random error while taking advantage of short aligning time of conventional technology when a plurality of chips arranged on a semiconductor substrate are aligned sequentially to respective reference positions by step and repeat system. CONSTITUTION:When a semiconductor substrate is aligned by step and repeat system depending on the coordinate values of actual chip arrangement calculated based on error parameters (translation, expansion/contraction, rotation, perpendicularity error), random errors which can not be corrected by the error parameters are previously obtained at each chip position on a substrate and stored. The ransom errors thus stored are added to calculated coordinates of actual arrangement which is thereby corrected thus aligning the chips.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to alignment between a semiconductor substrate and a mask in a step-and-repeat exposure apparatus for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been rapidly miniaturized and highly densified, and a device for manufacturing the same, particularly a circuit pattern of a mask, is transferred by superposing it on a circuit pattern formed on a semiconductor substrate. The exposure apparatus is also required to have higher precision. Therefore, at present, an exposure apparatus exposes a mask circuit pattern by exposing one exposure unit (for example, one chip) on a semiconductor substrate and then exposing the mask circuit pattern again by stepping the semiconductor substrate by a certain distance. A step-and-repeat type apparatus, in particular, a reduction projection type exposure apparatus (stepper) that repeats the above steps has become the mainstream. FIG. 3 is a diagram for explaining the step-and-repeat method and the conventional alignment method. In this method, the semiconductor substrate 32 is placed on the XY two-dimensional moving stage 31 to form a projected image of the circuit pattern of the mask. Since they are positioned relative to each other, the projected image and each chip 33 on the semiconductor substrate 32 can be precisely overlapped.
In the case of the reduction projection type exposure apparatus, the alignment mark provided on the mask and each chip 3 on the semiconductor substrate 32.
Alignment mark 34 attached to 3 is directly observed through a projection lens, or a through-the-lens type alignment method for detecting and aligning the alignment mark, and a microscope for alignment provided apart from the projection lens by a certain distance. There are two methods, an off-axis type alignment method of sending the substrate 32 directly below the projection lens after the entire position of the semiconductor substrate 32 is aligned using. Generally, in the through-the-lens method, since alignment is performed for each chip 33 on the semiconductor substrate 32, the overlay accuracy is high, but there is a problem that the exposure processing time for one substrate becomes long. In the case of the off-axis method, once the alignment of the entire semiconductor substrate 32 is completed, the substrate 32 is simply stepped according to the arrangement of the chips 33, so the exposure processing time is shortened. However, since the alignment of each chip 33 is not performed, the expansion and contraction of the semiconductor substrate 32, the rotation error of the substrate 32 on the stage 31, and the stage 31.
A satisfactory overlay accuracy cannot be obtained due to the influence of the orthogonality of itself. Therefore, recently, not all of the plurality of chips 33 arranged on the semiconductor substrate 32, but only some of the chips 33 are aligned with a reference position such as a projection position of a mask pattern. A method has been proposed that enables more precise positioning by simply stepping, and is currently the mainstream of the positioning method.

The method will be described below with reference to FIG. Each of the plurality of chips 33 regularly arranged on the semiconductor substrate 32 mounted on the XY two-dimensional moving stage 31 along the designed arrangement coordinates is set to a predetermined reference position (mask pattern projection position). On the other hand, in the method of sequentially aligning with the step and repeat method, the chip 3
3 when the semiconductor substrate 32 is moved based on the designed array coordinate value (Dn) and some of the plurality of chips 33 (for example, 5 chips in the shaded area) are aligned with the reference position. The position is actually measured using the alignment mark 34 provided on each of the chips 33, and the designed array coordinate value (Dn) and the actual array coordinate value (Fn) to be aligned by the step-and-repeat method. Is a predetermined error parameter (the residual rotation θ of the semiconductor substrate 32, the linear expansion / contraction R, and the orthogonality W of the stage 31), and a translation matrix of the two-dimensional position of the semiconductor substrate 32. A matrix of quantities O) and a unique relationship (determinant Fn = A
Dn + O), the error parameters (A, O) and the design are designed so that the average deviation between the plurality of actually measured values and the actual array coordinate value (Fn) is minimized. The actual array coordinate value (Fn) is calculated from the above-mentioned unique relational expression by the least squares method based on the array coordinate value (Dn) and the array coordinate value (Dn) of the step and repeat method. Actual array coordinate value (Fn)
The semiconductor substrate 32 is aligned according to the above. As described above, according to this method, the alignment can be performed with high accuracy while keeping the exposure processing time short.

[0004]

However, the above-mentioned prior art has the following problems.

FIG. 4 focuses on one photolithography process that is repeated a plurality of times in semiconductor device manufacturing.
It is the result of measuring the overlay deviation of the circuit pattern of the mask with respect to the circuit pattern formed on the semiconductor substrate after performing the alignment according to the above-mentioned conventional technique, and a plurality of chips 41 are arranged on the semiconductor substrate. The vector 42 represents the direction and amount of overlay deviation of the chips 41. Further, upon alignment, the actual measurement of the chip position with respect to the reference position required to determine the error parameter was carried out for the five chips in the shaded area in FIG. FIG. 4A is a diagram showing the measured raw data, that is, the total error. 4 (b), (c),
(D) and (e) show translational error, expansion / contraction error, rotation error, and orthogonality error having the same meaning as the error parameter described in the section of the prior art from the total error shown in FIG. 4 (a). It is a figure showing the data extracted separately. Finally, FIG. 4 (f) shows that
It is a figure which shows the remaining error which removed the said translation, expansion / contraction, rotation, and orthogonality error, ie, the random error which cannot be removed by the conventional alignment method.

Next, FIG. 2 is a numerical representation of the error correction system of the conventional alignment method and the measurement and separation results of the overlay deviation shown in FIG. 4, which are summarized as shown in FIG. In the conventional alignment method, translation, expansion and contraction,
Since the correction system uses only rotation and orthogonality as error parameters, random errors that cannot be corrected by the error parameters remain as overlay deviations as shown in FIG. As shown in, the amount is 0.13 μm (3σ), which is an amount that cannot be ignored in the pursuit of highly accurate alignment.

[0007]

[Table 1]

Table 1 shows the result of measuring the overlay deviation of the mask circuit pattern with respect to the circuit pattern formed on the semiconductor substrate after the conventional alignment, and separating the error factors.

Such random errors naturally differ in each of the photolithography processes that are repeated a plurality of times, and occur when the semiconductor substrate itself is deformed depending on the process before each photolithography process, for example, the stress during the film forming process. In many cases, the direction and amount of the random error at each chip position are relatively high in reproducibility in the same process. Further, paying attention to Table 1, it should be noted that the translation, expansion / contraction, rotation, and orthogonality components should have been surely corrected, but cannot be pushed to zero and remain as a residual error. As described above, in the present test, the measurement of the chip position with respect to the reference position required for calculating the error parameter was carried out for the five chips in the shaded area shown in FIG. The measurement results of the 5 chips naturally include the random error shown in FIG. However, the conventional error parameter calculation method is based on the assumption that the random error is small enough to be ignored. Therefore, the calculated error parameter is multiplied by the error for the random error, which leads to the above-mentioned result shown in Table 1. In such a case, in order to improve the calculation accuracy of the error parameter, the number of chips for position measurement may be increased, but it was invented for the purpose of performing highly accurate alignment without increasing the exposure processing time. This is out of the original meaning of the conventional technique, and even if it is implemented, the random error cannot be removed.

As described above, the conventional technique holds true when the random error is so small that it can be ignored, but satisfactory high-precision alignment cannot be performed in the step where the random error is large. This causes a processing defect that the circuit pattern of the semiconductor device is displaced from a predetermined position and causes a reduction in yield. Therefore, the present invention solves such a problem, and an object of the present invention is to improve even a process having a large random error while keeping the advantage of being able to shorten the exposure processing time of the conventional technique. An object of the present invention is to provide an exposure apparatus capable of obtaining alignment accuracy and improve the yield of semiconductor device manufacturing.

[0011]

[Means for Solving the Problems]

1) The exposure apparatus of the present invention includes a plurality of chips which are regularly arranged on a semiconductor substrate along the designed arrangement coordinates.
When sequentially performing step-and-repeat alignment with respect to a predetermined reference position, each position when some of the plurality of chips are aligned with the reference position is actually measured, and the designed array coordinate value and the When the actual array coordinate values to be aligned by the step-and-repeat method have a unique relationship including a predetermined error parameter, the average of the plurality of actual measurement values and the actual array coordinate values The error parameter is determined so as to minimize the deviation, and the actual array coordinate value is calculated based on the determined error parameter and the designed array coordinate value, and the position of the step-and-repeat method is calculated. At the time of alignment, in the exposure apparatus that positions the semiconductor substrate according to the calculated actual array coordinate value, an error that cannot be corrected with the determined error parameter That is, a random error is obtained in advance for each chip position on the semiconductor substrate and stored, and the stored random error is added to the actual array coordinate value calculated based on the error parameter to correct it. , Characterized by positioning.

2) A method of manufacturing a semiconductor device according to the present invention is characterized in that the exposure apparatus according to claim 1 is used in a photolithography process for manufacturing a semiconductor device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below by taking a step-and-repeat type reduction projection type exposure apparatus (stepper) as an example.

In FIG. 3, each of a plurality of chips 33 regularly arranged on the semiconductor substrate 32 mounted on the XY two-dimensional moving stage 31 along the designed arrangement coordinates,
As a method of sequentially aligning with a predetermined reference position (mask pattern projection position) by the step-and-repeat method, four error parameters of translational error, expansion / contraction error, rotation error, and orthogonality error are calculated, and based on that, The process up to the step of obtaining the actual array coordinates and performing alignment is exactly the same as the conventional technique. Specifically, the chip 33
Each position when the semiconductor substrate 32 is moved based on the designed array coordinate value (Dn) and some of the plurality of chips 33 (for example, 5 chips in the shaded area) are aligned with the reference position. Is actually measured using the alignment mark 34 provided on each chip 33, and the designed array coordinate value (Dn) and the actual array coordinate value (Fn) to be aligned by the step-and-repeat method. Is a predetermined error parameter (the remaining rotation θ of the semiconductor substrate 32, the linear expansion / contraction R, and the orthogonality W of the stage 31), and the translation amount of the two-dimensional position of the semiconductor substrate 32. Of the matrix O) and a unique relationship (determinant Fn = A.
Dn + O), the error parameters (A, O) and the designed values are designed so that the average deviation between the plurality of actually measured values and the actual array coordinate values (Fn) is minimized. Based on the array coordinate value (Dn), the actual array coordinate value (F
It is also possible to calculate n) and align the semiconductor substrate 32 according to the calculated actual array coordinate value (Fn) during the step-and-repeat alignment. As described above, up to this point, it is exactly the same as the prior art,
The present embodiment is characterized in that a system for introducing a random error that cannot be corrected by the error parameter to the calculated actual array coordinate value and correcting the position is introduced. Specifically, as shown in FIG. 4 (f), the misalignment of the mask circuit pattern with respect to the circuit pattern formed on the semiconductor substrate after the alignment by the method up to the range of the above-mentioned conventional technique is performed. Random errors obtained by separating and removing translation, expansion, rotation, rotation, and orthogonality errors from the total error when measuring the raw error, i.e., the direction and amount of each chip position experimentally It was determined and stored in the exposure device. As described above, in the same process, the direction and amount of the random error at each chip position have relatively high reproducibility. Therefore, random errors were determined for several semiconductor substrates in the same process, and the averaged values were input to the exposure apparatus as true random errors. Further, since the translation, expansion / contraction, rotation, and separation of the orthogonality error have essentially the same meanings as the error parameters necessary for the above-mentioned alignment, they are calculated by the same calculation procedure. Then, the stored random error is added and corrected to the actual array coordinate value calculated based on the error parameter at the time of step-and-repeat alignment. Specifically, the alignment is performed with the position where the random error is removed from the actual array coordinate value as the final array coordinate value. FIG. 1 shows the error correction system of the alignment method of the present invention and the overlay deviation of the mask circuit pattern with respect to the circuit pattern formed on the semiconductor substrate after the alignment of the present invention is performed. This is a summary of the results separated into error factors. As shown in FIG. 1, in the present invention, in addition to the conventional error parameters (translation, expansion / contraction, rotation, orthogonality), even a random error that cannot be corrected by these error parameters is corrected and aligned. For,
High alignment accuracy can be obtained even in the process in which the random error is large.

[0015]

[Table 2]

Table 2 shows the result of measuring the overlay deviation of the mask circuit pattern with respect to the circuit pattern formed on the semiconductor substrate after the alignment of the present invention, and separating the error factors. .

Table 2 shows alignment results when the present invention is applied to the same steps as the results in the prior art shown in Table 1, but as can be seen by comparing both, the present invention According to the position alignment method of (1), each error factor is suppressed to a small level, and the overlay accuracy 3 sigma value combining these factors is about 0.09 μm, which is a dramatic improvement over the conventional method.
As described above, according to the present invention, it is possible to obtain high alignment accuracy even in a process having a large random error, while taking advantage of the advantage that the exposure time of the conventional technique can be shortened.

Although one embodiment of the present invention has been described above, in addition to this, 1) Random errors are corrected and aligned not in all the chips arranged on the semiconductor substrate but in some chips.

2) In addition to correcting by adding a random error to the array coordinate value to be actually positioned, which is calculated based on the error parameter, the random parameter is also taken into consideration when calculating the error parameter. Increase accuracy.

3) An exposure apparatus other than the reduction projection type, for example,
The present invention is applied to a 1 × projection type stepper, an X-ray exposure apparatus which is a proximity type stepper, and the like.

4) An apparatus (defect inspection, prober, etc.) for inspecting a semiconductor substrate, a mask having a plurality of chip patterns, etc. in a field other than the exposure apparatus, and an inspection field of view for each chip by a step-and-repeat method, Align with the reference position such as the probe needle.

In the above cases, the same effect as that of this embodiment can be expected.

[0023]

As described above, according to the present invention, 1) stepping each of a plurality of chips regularly arranged on a semiconductor substrate along a designed arrangement coordinate with respect to a predetermined reference position. When sequentially aligning by the and repeat method, each position when some of the plurality of chips are aligned with the reference position is actually measured, and the alignment coordinate value in the design is aligned by the step and repeat method. When it is assumed that the actual array coordinate values should have a unique relationship including a predetermined error parameter, the average deviation between the plurality of actual measurement values and the actual array coordinate values is minimized. To determine the error parameter, calculate the actual array coordinate value based on the determined error parameter and the designed array coordinate value, during step and repeat alignment, In an exposure apparatus that positions the semiconductor substrate according to the calculated actual array coordinate values,
An error that cannot be corrected by the determined error parameter,
That is, a random error is obtained in advance for each chip position on the semiconductor substrate and stored, and the actual array coordinate value calculated based on the error parameter is corrected by adding the stored random error, Position.

2) By using the exposure apparatus according to the first aspect in the photolithography process for manufacturing a semiconductor device, the advantage that the exposure processing time of the prior art can be shortened is taken into consideration, and even in the process where a random error is large. High alignment accuracy can be obtained, and the yield can be improved without lowering the mass production efficiency of semiconductor device manufacturing.

[Brief description of drawings]

FIG. 1 is a diagram showing an error correction system of an alignment method of the present invention.

FIG. 2 is a diagram showing an error correction system of a conventional alignment method.

FIG. 3 is a diagram illustrating a step-and-repeat type alignment method.

FIG. 4 is a diagram showing a result of measuring an overlay deviation of a circuit pattern of a mask with respect to a circuit pattern formed on a semiconductor substrate after performing alignment according to a conventional technique, and FIG. Raw data, that is,
It is a figure which shows a comprehensive error. (B) is a diagram showing the translation error component separated from the total error. (C) is
It is the figure which separated and showed the expansion-contraction error component from the total error. (D) is a diagram showing the rotation error component separated from the total error. (E) is a diagram showing the orthogonality error component separated from the total error. (F) is a diagram showing the remaining random error components obtained by removing translation, expansion, rotation, and orthogonality error components from the total error.

[Explanation of symbols]

 31 XY two-dimensional moving stage 32 semiconductor substrate 33 chip 34 alignment mark 41 chip 42 overlay misalignment

Claims (2)

[Claims] 1. A plurality of chips, which are regularly arranged on a semiconductor substrate along a designed arrangement coordinate, are sequentially aligned with a predetermined reference position by a step-and-repeat method. Actually measuring each position when some of the chips are aligned with the reference position, and the array coordinate value on the design and the actual array coordinate value to be aligned by the step and repeat method are predetermined error parameters. When including a unique relationship, the error parameter is determined so that the average deviation between the plurality of actual measured values and the actual array coordinate value is minimized, and the determined error The actual array coordinate value is calculated based on the parameter and the designed array coordinate value, and at the time of step and repeat alignment, the actual array coordinate value is calculated according to the calculated actual array coordinate value. In the exposure device for positioning the conductor substrate, an error that cannot be corrected by the determined error parameter, that is, a random error is previously obtained and stored for each chip position on the semiconductor substrate, and calculated based on the error parameter. To the actual array coordinate values,
An exposure apparatus, wherein the stored random error is added, corrected, and positioned. 2. A method of manufacturing a semiconductor device, wherein the exposure apparatus according to claim 1 is used in a photolithography process for manufacturing a semiconductor device.