JPS63943B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for inspecting a transferred image when a reduction projection exposure machine is used.

In recent years, as semiconductor integrated circuit devices have become faster and more highly integrated, methods for forming fine patterns have been studied. The most important process for forming fine patterns is photolithography, and the quality of fine pattern formation depends largely on the type and performance of the exposure machine. Recently developed reduction projection exposure machines have excellent performance in forming fine patterns, but there are various problems because the patterns are transferred directly from the reticle onto the wafer. For example, in the past, many chips were transferred from a reticle to create a mask, and that mask was used to transfer the chips onto a wafer. Therefore, even if there was dust on the mask, only that one chip would be defective, and the others would be defective. Chips are not affected. However, when a reduction projection exposure machine is used, if dust falls on the reticle or if the reticle itself is defective, all wafers and chips will be defective. Therefore, strict inspection is required when transferring from a reticle to a wafer. However, the pattern transferred onto the wafer usually already has a pattern from a previous process underneath it, making pattern inspection extremely difficult.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for easily and accurately inspecting transferred images using a reduction projection exposure device.

According to the present invention, in the step of coating a semiconductor substrate with a photosensitive organic film and transferring a desired pattern to the film, a desired pattern is formed on an unprocessed area without unevenness on the semiconductor substrate in a chip arrangement. can be obtained by separately transferring at least one location.

One of the effects obtained by the present invention is that reticles can be easily inspected. That is, since the transferred image of the reticle is transferred only to the pattern of the process on a flat area on the wafer, it is easy to find defective patterns due to dust or the like on the reticle. Furthermore, since the transfer pattern from that single process remains even after the integrated circuit device has been fabricated on the wafer, even if the lot is defective, it can be determined whether the defect is caused by a defective pattern even after fabrication. It's easy to do.

Next, embodiments of the present invention will be described using the drawings.
FIG. 1 is a plan view showing the arrangement of chips transferred onto a wafer by a conventional method, and FIG. 2 is a plan view showing the arrangement of chips in an embodiment of the present invention. First, as shown in FIG. 1, in the conventional method, chips with the same pattern are all arranged on a wafer, but as mentioned above, it is extremely difficult to determine whether or not there is a defect in the transferred pattern. Therefore, for example, as shown in FIG. 2A, a flat unprocessed area 202 is prepared in advance in the first transfer step, and one chip of the transferred image 201 of the first step is specially patterned thereon. However, this chip 201 is left blank in the subsequent transfer process, leaving the transfer pattern of the first process until the end. It goes without saying that most of the other chips 203 are also exposed at this time. Next, as shown in FIG. 2b, a second step transfer image 205 is prepared independently of the chip array 203 in the same manner as in the first step. The same process is performed after the third step. As a result, an independent pattern can be produced for each process apart from the normal chip array 203. By this method, the pattern after transfer of each layer can be created on a flat unprocessed area, and defects in the transferred pattern can be easily detected. Furthermore, since the transferred patterns of each layer remain after the manufacturing process is completed, dummy wafers can also be prepared. If there is a defective wafer, it can be easily resolved. As a result of the above, the inspection of the reticle can be greatly simplified, and the transferred image can also be inspected at the same time, so that the yield in the manufacturing process can be significantly improved. In this example, we used the area on the wafer to leave a transferred image of each layer, but it is also possible to prepare dummy wafers and use one for each layer separately from the product lot. .

[Brief explanation of the drawing]

FIG. 1 is a plan view of a wafer showing a conventional chip arrangement, and FIGS. 2a and 2b are plan views showing a chip arrangement according to an embodiment of the present invention. In the figure, 201 is the position of the transferred image of the chip in the first step;
Reference numeral 202 indicates a flat, unprocessed area, 203 indicates a normal chip arrangement, and 205 indicates the position of a transferred image of the chip in the second step.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device that includes multiple transfer steps using the reduced projection exposure method, a pattern identical to the process pattern is applied to an unprocessed area of the semiconductor substrate independently for each transfer step, in addition to the chip arrangement. A method for manufacturing a semiconductor integrated circuit device, characterized in that at least one location is transferred and used for detecting a pattern defect.