JPS63943B2 - - Google Patents
Info
- Publication number
- JPS63943B2 JPS63943B2 JP54156620A JP15662079A JPS63943B2 JP S63943 B2 JPS63943 B2 JP S63943B2 JP 54156620 A JP54156620 A JP 54156620A JP 15662079 A JP15662079 A JP 15662079A JP S63943 B2 JPS63943 B2 JP S63943B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- transferred
- wafer
- chip
- reticle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 14
- 230000002950 deficient Effects 0.000 description 8
- 239000000428 dust Substances 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路装置の製法に関し、特
に縮少投影露光機を用いた場合の転写像の検査方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for inspecting a transferred image when a reduction projection exposure machine is used.
近年、半導体集積回路装置は高速化、高集積化
が進むにつれ、微細パターンの形成方法が研究さ
れつつある。微細パターンを形成するための最も
主要な工程は写真蝕刻であり、しかもその中で微
細パターン形成の良否は露光機の種類、性能によ
るところが大である。最近開発された縮少投影露
光機は微細パターンの形成にすぐれた性能を持つ
ているが、レチクルから直接ウエハー上にパター
ンを転写するため、種々の問題が存在する。例え
ば従来はレチクルから多数のチツプを転写してマ
スクを作製し、そのマスクを使用してウエハー上
に転写しているため、たとえマスク上に塵埃があ
つたとしてもその1チツプのみ不良となり、他の
チツプには影響しない。しかしながら縮少投影露
光機を使用した場合は、レチクル上に塵埃があつ
たり、あるいはレチクルそのものに欠陥があつた
場合には全ウエハー、全チツプ不良となつてしま
う。従つてレチクルからウエハーに転写した際厳
重な検査が必要となる。しかしウエハー上に転写
されたパターンは通常その下にすでに前工程のパ
ターンがありパターン検査が極めて困難である。 In recent years, as semiconductor integrated circuit devices have become faster and more highly integrated, methods for forming fine patterns have been studied. The most important process for forming fine patterns is photolithography, and the quality of fine pattern formation depends largely on the type and performance of the exposure machine. Recently developed reduction projection exposure machines have excellent performance in forming fine patterns, but there are various problems because the patterns are transferred directly from the reticle onto the wafer. For example, in the past, many chips were transferred from a reticle to create a mask, and that mask was used to transfer the chips onto a wafer. Therefore, even if there was dust on the mask, only that one chip would be defective, and the others would be defective. Chips are not affected. However, when a reduction projection exposure machine is used, if dust falls on the reticle or if the reticle itself is defective, all wafers and chips will be defective. Therefore, strict inspection is required when transferring from a reticle to a wafer. However, the pattern transferred onto the wafer usually already has a pattern from a previous process underneath it, making pattern inspection extremely difficult.
従つて本発明の目的は縮少投影露光機による転
写像検査を簡単に的確に行う方法を提供するもの
である。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for easily and accurately inspecting transferred images using a reduction projection exposure device.
本発明によれば、半導体基板上に感光性有機被
膜を被覆し、該被膜に所望のパターンを転写する
工程において、前記半導体基板上の凹凸のない未
加工の領域に所望のパターンをチツプ配列とは別
に少なくとも1個所以上転写することによつて得
られる。 According to the present invention, in the step of coating a semiconductor substrate with a photosensitive organic film and transferring a desired pattern to the film, a desired pattern is formed on an unprocessed area without unevenness on the semiconductor substrate in a chip arrangement. can be obtained by separately transferring at least one location.
本発明によつて得られる効果としてまずレチク
ルの検査が容易にできることがあげられる。即
ち、レチクルの転写像がウエハー上の平坦な領域
にその工程のパターンのみ転写されるので、レチ
クル上にある塵埃などによる不良パターンを発見
しやすい。さらにその単一工程の転写パターンは
ウエハー上に集積回路装置を作製し終つても残つ
ているため、もしそのロツトが不良であつた場合
でも不良パターンによるものかどうかの不良解折
を作製後にも簡単に行なうことができる。 One of the effects obtained by the present invention is that reticles can be easily inspected. That is, since the transferred image of the reticle is transferred only to the pattern of the process on a flat area on the wafer, it is easy to find defective patterns due to dust or the like on the reticle. Furthermore, since the transfer pattern from that single process remains even after the integrated circuit device has been fabricated on the wafer, even if the lot is defective, it can be determined whether the defect is caused by a defective pattern even after fabrication. It's easy to do.
次に図面を用いて本発明の実施例を説明する。
第1図は従来の方法で行なつたウエハー上に転写
されたチツプの配列を示す平面図であり、第2図
は本発明の実施例のチツプ配列を示す平面図であ
る。まず、第1図に示すように従来の方法ではウ
エハー上にすべて同一パターンのチツプを配列さ
せていたが、前述したようにその転写パターンに
欠陥があるか否かが極めて判別し難かつた。そこ
で例えば第2図aに示すように第一の転写工程に
おいて平坦な未加工の領域202を予め用意して
おき、そこへ第一工程の転写像201を1チツプ
特別にパターニングしておく。ただしこのチツプ
201は後の転写工程では空白にしておき、第一
工程の転写パターンを最後まで残しておく。なお
このとき他の大部分のチツプ203も露光してお
くことは言うまでもない。次に第2図bに示すよ
うに第二工程の転写像205を第一工程と同様に
チツプ配列203とは独立に作製しておく。以下
第三工程以後同様の処理を行う。その結果、通常
のチツプ配列203とは別に各工程ごとに独立パ
ターンを作製できる。この方法によつて各層の転
写後のパターンを平坦な未加工の領域に作製で
き、転写パターンの欠陥を簡単に見い出すことが
できる。さらにまた、
各層の転写パターンが製造工程終了後も残つて
いるためダミーウエハーを用意する場合もでき
る。もし不良ウエハーがあればその不良解折も容
易に行うことができる。以上のことからレチクル
の検査を大幅に簡略化でき、しかも転写像の検査
を同時にでき、製造工程における歩留りを著ぢる
しく向上できる。なお本実施例ではウエハー上の
領域を使用して各層の転写像を残す方法をとつた
が、ダミーウエハーを用意して、製品ロツトとは
別に各層ごとに一枚づつ使用することも可能であ
る。 Next, embodiments of the present invention will be described using the drawings.
FIG. 1 is a plan view showing the arrangement of chips transferred onto a wafer by a conventional method, and FIG. 2 is a plan view showing the arrangement of chips in an embodiment of the present invention. First, as shown in FIG. 1, in the conventional method, chips with the same pattern are all arranged on a wafer, but as mentioned above, it is extremely difficult to determine whether or not there is a defect in the transferred pattern. Therefore, for example, as shown in FIG. 2A, a flat unprocessed area 202 is prepared in advance in the first transfer step, and one chip of the transferred image 201 of the first step is specially patterned thereon. However, this chip 201 is left blank in the subsequent transfer process, leaving the transfer pattern of the first process until the end. It goes without saying that most of the other chips 203 are also exposed at this time. Next, as shown in FIG. 2b, a second step transfer image 205 is prepared independently of the chip array 203 in the same manner as in the first step. The same process is performed after the third step. As a result, an independent pattern can be produced for each process apart from the normal chip array 203. By this method, the pattern after transfer of each layer can be created on a flat unprocessed area, and defects in the transferred pattern can be easily detected. Furthermore, since the transferred patterns of each layer remain after the manufacturing process is completed, dummy wafers can also be prepared. If there is a defective wafer, it can be easily resolved. As a result of the above, the inspection of the reticle can be greatly simplified, and the transferred image can also be inspected at the same time, so that the yield in the manufacturing process can be significantly improved. In this example, we used the area on the wafer to leave a transferred image of each layer, but it is also possible to prepare dummy wafers and use one for each layer separately from the product lot. .
第1図は従来のチツプ配列を示したウエハーの
平面図であり、第2図a及び第2図bは本発明の
実施例のチツプの配列を示した平面図である。図
中、201は第一工程のチツプの転写像の位置、
202は平坦で未加工の領域、203は通常のチ
ツプ配列、205は第二工程のチツプの転写像の
位置を各々示す。
FIG. 1 is a plan view of a wafer showing a conventional chip arrangement, and FIGS. 2a and 2b are plan views showing a chip arrangement according to an embodiment of the present invention. In the figure, 201 is the position of the transferred image of the chip in the first step;
Reference numeral 202 indicates a flat, unprocessed area, 203 indicates a normal chip arrangement, and 205 indicates the position of a transferred image of the chip in the second step.
Claims (1)
む半導体集積回路装置の製法において、各転写工
程ごとに独立させて半導体基板の未加工の領域に
チツプ配列とは別に工程用パターンと同一パター
ンを少なくとも1個所以上転写しておき、パター
ン欠陥部の検出に用いることを特徴とする半導体
集積回路装置の製法。1. In a method for manufacturing a semiconductor integrated circuit device that includes multiple transfer steps using the reduced projection exposure method, a pattern identical to the process pattern is applied to an unprocessed area of the semiconductor substrate independently for each transfer step, in addition to the chip arrangement. A method for manufacturing a semiconductor integrated circuit device, characterized in that at least one location is transferred and used for detecting a pattern defect.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15662079A JPS5679431A (en) | 1979-12-03 | 1979-12-03 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15662079A JPS5679431A (en) | 1979-12-03 | 1979-12-03 | Manufacture of semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5679431A JPS5679431A (en) | 1981-06-30 |
JPS63943B2 true JPS63943B2 (en) | 1988-01-09 |
Family
ID=15631688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15662079A Granted JPS5679431A (en) | 1979-12-03 | 1979-12-03 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679431A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5814137A (en) * | 1981-07-16 | 1983-01-26 | Fujitsu Ltd | Exposure system by reduced projection |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5420317A (en) * | 1977-07-15 | 1979-02-15 | Taiyo Electric Mfg | Exciter for brushless ac generator |
JPS5662323A (en) * | 1979-10-26 | 1981-05-28 | Fujitsu Ltd | Reticle examination method |
-
1979
- 1979-12-03 JP JP15662079A patent/JPS5679431A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5420317A (en) * | 1977-07-15 | 1979-02-15 | Taiyo Electric Mfg | Exciter for brushless ac generator |
JPS5662323A (en) * | 1979-10-26 | 1981-05-28 | Fujitsu Ltd | Reticle examination method |
Also Published As
Publication number | Publication date |
---|---|
JPS5679431A (en) | 1981-06-30 |
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