JPS6131610B2 - - Google Patents
Info
- Publication number
- JPS6131610B2 JPS6131610B2 JP13848079A JP13848079A JPS6131610B2 JP S6131610 B2 JPS6131610 B2 JP S6131610B2 JP 13848079 A JP13848079 A JP 13848079A JP 13848079 A JP13848079 A JP 13848079A JP S6131610 B2 JPS6131610 B2 JP S6131610B2
- Authority
- JP
- Japan
- Prior art keywords
- reticle
- pattern
- glass substrate
- chip
- chip pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 11
- 238000007689 inspection Methods 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims 1
- 239000011521 glass Substances 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000002950 deficient Effects 0.000 description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Description
【発明の詳細な説明】
本発明はレチクル検査方法、より詳しくは、半
導体装置の製造においてウエハーへのパターン焼
付けに関連したレチクル検査方法に関する。ここ
でレチクルとは、ウエハー(半導体基板)への素
子(チツプ)パターンの焼付けの際に用いられる
チツプの10倍の大きさのパターンを持つものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reticle inspection method, and more particularly to a reticle inspection method related to pattern printing on a wafer in the manufacture of semiconductor devices. The reticle here has a pattern that is 10 times the size of the chip used to print element (chip) patterns onto wafers (semiconductor substrates).
該レチクルをマスクとして、シリコン等の半導
体基板に、チツプパターンを直接且つ複数個並べ
て露光するいわゆるステツプ・アンド・リピート
方式によるパターン焼付けにおいては、マスクで
あるレチクルに不良があるとすべてのチツプは不
良になり、このことは労力とウエハーの損失とな
る。ところで、従来技術によると露光されたレチ
クルのパターンの検査は検査者の眼でなされ、そ
れに数時間もの時間を要するものであつた。 In pattern printing using the so-called step-and-repeat method, in which a plurality of chip patterns are exposed directly onto a semiconductor substrate such as silicon by using the reticle as a mask, if the reticle, which is the mask, is defective, all chips are defective. This results in a loss of labor and wafers. However, according to the prior art, the pattern of an exposed reticle is inspected by the inspector's eyes, which takes several hours.
本発明は従来技術において経験された上記の問
題を解決するものである。まず、チツプパターン
の10倍の大きさのパターンを有するレチクルを形
成する。該レチクルは、周知のようにガラス基板
上にクロム等マスクパターンが選択的に形成され
て構成される。本発明にあつては該レチクルが不
良でないことを確認した上でガラス基板上にレン
ズ焼付けによつてチツプパターンを作成し、焼き
付けられたパターンを目視検査で不良でないこと
を確認する。かかるチツプパターンは以後の検査
において基準となるものであるから基準チツプパ
ターンと呼称する。本発明においては、かかる基
準チツプパターンを用いてレチクルを検査するの
であるが、その方法を以下添付図面を参照して説
明する。 The present invention solves the above problems experienced in the prior art. First, a reticle with a pattern 10 times the size of the chip pattern is formed. As is well known, the reticle is constructed by selectively forming a mask pattern such as chrome on a glass substrate. In the present invention, after confirming that the reticle is not defective, a chip pattern is created on a glass substrate by lens baking, and the printed pattern is visually inspected to confirm that it is not defective. Such a chip pattern will be referred to as a reference chip pattern because it will serve as a reference for subsequent tests. In the present invention, a reticle is inspected using such a reference chip pattern, and the method will be explained below with reference to the accompanying drawings.
先ず第1図に示されるウエハーとほぼ同じ膜厚
を有するガラス基板1を準備し、その一方の表面
にクロムまたは類似の物質を蒸着したものを用意
する。かかる工程は従来知られた技術に従つてな
されうるのでその詳細な説明は省略する。ここで
ガラス基板1の厚さがウエハーとほぼ同一とされ
る理由は、レチクルから投影される像の焦点をほ
ぼ一定とし操作性を向上させるためである。 First, a glass substrate 1 having approximately the same film thickness as the wafer shown in FIG. 1 is prepared, and one surface of the glass substrate 1 has chromium or a similar substance deposited thereon. Since this process can be performed according to conventionally known techniques, detailed explanation thereof will be omitted. The reason why the thickness of the glass substrate 1 is made to be approximately the same as that of the wafer is to improve operability by keeping the focus of the image projected from the reticle approximately constant.
次に、かくの如くに用意したガラス基板1の上
の前記クロム膜上にポジ型フオト・レジストを塗
布する。かかるフオト・レジストには例えば市販
の米国シプレイ社によるAZ1350を適用すること
ができる。かかる状態において、ガラス基板1の
一方の縁の近くに当該縁に沿つて前記レチクルを
用いて該レチクルの有するチツプパターンを1列
焼付ける。このパターンは検査者の眼で不良でな
いことを確認する。次に該フオト・レジストをマ
スクとしてクロムをエツチングし、ガラス基板の
〓〓〓〓
上にはその一方縁に沿つて1列の基準チツプパタ
ーン2………が作られる。クロムを蒸着した上記
の如きガラス基板は半導体装置の製造工程におけ
る窓開きのパターン毎に用意される。そして前記
レチクルをそのまま用いての実際の製造工程の窓
開きの直前に、前記ガラス基板上の基準チツプパ
ターンの列の隣りに第2図に示されるように検査
すべきレチクルすなわちガラス基板に前記基準チ
ツプパターンを形成したレチクルであつて、且つ
実際の製造工程に適用される段階のレチクルの有
するチツプパターン3を1列に焼付け、このチツ
プパターンと前記基準チツプパターンとを自動検
査装置で比較検査し、かかる製造工程において使
用される段階において当該レチクルが完全である
かどうかを検査する。この検査をなすに際し、チ
ツプパターンがガラス基板の上に焼き付けられて
いて、光透過性があるということが重要な意味を
もつ。上記の自動検査は、基準チツプパターンと
検査されるべきチップパターンとに光を当て、そ
れを電気的信号に変え、基準チツプパターンから
の信号と被検査チツプパターンからの信号とを互
に打消し合うように合成する。被検査チツプパタ
ーンレチクルが不良でないのであれば、双方の信
号を合成したものは別に信号を出すことはない
が、欠陥があるかまたはごみが付着していればそ
れは1つの信号を発生し、その信号は自動的にと
らえることができる。 Next, a positive type photoresist is applied onto the chromium film on the glass substrate 1 prepared in this manner. As such a photoresist, for example, commercially available AZ1350 manufactured by Shipley, Inc. in the United States can be applied. In this state, one row of chip patterns of the reticle are printed near one edge of the glass substrate 1 along the edge using the reticle. The inspector visually confirms that this pattern is not defective. Next, the chromium is etched using the photo resist as a mask, and the glass substrate is removed.
A row of reference chip patterns 2 . . . is formed on the top along one edge thereof. A glass substrate as described above on which chromium is vapor-deposited is prepared for each window opening pattern in the semiconductor device manufacturing process. Immediately before opening the window in the actual manufacturing process using the reticle as it is, the reticle to be inspected, that is, the glass substrate, is placed next to the row of reference chip patterns on the glass substrate as shown in FIG. The chip pattern 3 of the reticle, which has a chip pattern formed thereon and which is at the stage of being applied to the actual manufacturing process, is printed in one row, and this chip pattern and the reference chip pattern are comparatively inspected using an automatic inspection device. , the integrity of the reticle is inspected during use in the manufacturing process. When performing this inspection, it is important that the chip pattern is printed on the glass substrate and that it is transparent to light. The automatic inspection described above shines light on the reference chip pattern and the chip pattern to be inspected, converts it into an electrical signal, and cancels out the signal from the reference chip pattern and the signal from the chip pattern to be inspected. Combine to match. If the chip pattern reticle to be inspected is not defective, the combination of both signals will not output a separate signal, but if it is defective or has dust attached, it will generate one signal, and its Signals can be captured automatically.
このような本発明の方法によれば、パターンの
環像、クロムエツチング、フオト・レジストの剥
離を経て自動検査に至るが、ここにおける所要時
間は10分から20分であつて、従来行われている目
視検査に比べて所要時間が約10分の1に短縮さ
れ、更に検査の信頼性を著しく向上させることが
できる。そして、当該比較検査の結果良品と判断
されたレチクルはそのまま実際の製造工程に適用
される。 According to the method of the present invention, automatic inspection is performed through the pattern ring image, chrome etching, and photoresist peeling, but the time required here is 10 to 20 minutes, which is different from the conventional method. The time required is reduced to about one-tenth that of visual inspection, and the reliability of the inspection can be significantly improved. Then, the reticle determined to be non-defective as a result of the comparative inspection is directly applied to the actual manufacturing process.
そして一ロツトの製造工程における当該レチク
ルの使用が終了したならば、該レチクルの、次の
製造ロツトへの使用可能性を判定するために該レ
チクルを用いて前記ガラス基板へチツプパターン
を再び焼付ける。この新しいチツプパターンは前
の製造ロツトに使用されたチツプパターン3に平
行して形成し3′、基準チツプパターン2を参照
して検査してもよいし、前の製造ロツトに使用さ
れたチツプパターン3が不良でなかつたのであれ
ばそれと対比して検査してもよい。このようにし
て、ガラス基板上に更に被検査チツプパターンを
焼付けることができなくなるまで上述した検査工
程を繰返すことができる。 When the use of the reticle in the manufacturing process for one lot is completed, the chip pattern is printed onto the glass substrate again using the reticle in order to determine whether the reticle can be used in the next manufacturing lot. . This new chip pattern may be formed parallel to the chip pattern 3 used in the previous production lot 3' and inspected with reference to the reference chip pattern 2, or the chip pattern used in the previous production lot may be If No. 3 is not defective, it may be inspected in comparison with No. 3. In this way, the above-described testing process can be repeated until no further chip patterns to be tested can be printed onto the glass substrate.
第1図は本発明の方法を実施するに際し用いら
れるガラス基板に基準チツプパターンを焼付けた
状態を示す正面図、第2図は基準チツプパターン
の隣りに検査すべきチツプパターンが焼付けられ
た状態を示す第1図のガラス基板の正面図、であ
る。
1……ガラス基板、2……基準チツプパター
ン、3,3′……被検査チツプパターン。
〓〓〓〓
Fig. 1 is a front view showing a state in which a reference chip pattern is printed on a glass substrate used in carrying out the method of the present invention, and Fig. 2 shows a state in which a chip pattern to be inspected is printed next to the reference chip pattern. 2 is a front view of the glass substrate shown in FIG. 1. FIG. 1... Glass substrate, 2... Reference chip pattern, 3, 3'... Chip pattern to be inspected. 〓〓〓〓
Claims (1)
となるパターンを形成し、前記レチクルを用いて
の露光処理工程の前に該レチクルのパターンを前
記基板上の基準パターンに並べて形成し、該基準
パターンと新らたに形成されたパターンとを比較
して当該レチクルの検査を行うことを特徴とする
レチクル検査方法。1. A reference pattern is formed on a thin film on a substrate using a desired reticle, and before an exposure process using the reticle, the pattern of the reticle is formed in line with the reference pattern on the substrate, and the reference pattern is A reticle inspection method characterized by inspecting the reticle by comparing a pattern with a newly formed pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13848079A JPS5662323A (en) | 1979-10-26 | 1979-10-26 | Reticle examination method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13848079A JPS5662323A (en) | 1979-10-26 | 1979-10-26 | Reticle examination method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5662323A JPS5662323A (en) | 1981-05-28 |
JPS6131610B2 true JPS6131610B2 (en) | 1986-07-21 |
Family
ID=15223050
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13848079A Granted JPS5662323A (en) | 1979-10-26 | 1979-10-26 | Reticle examination method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5662323A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6327212U (en) * | 1986-07-29 | 1988-02-23 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5679431A (en) * | 1979-12-03 | 1981-06-30 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor integrated circuit device |
JPS58210618A (en) * | 1982-06-02 | 1983-12-07 | Hitachi Ltd | Method and apparatus for reduced projection exposure |
JPS6216528A (en) * | 1985-07-16 | 1987-01-24 | Hoya Corp | Substrate with al film |
US4637714A (en) * | 1985-10-31 | 1987-01-20 | International Business Machines Corporation | Inspection system for pellicalized reticles |
-
1979
- 1979-10-26 JP JP13848079A patent/JPS5662323A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6327212U (en) * | 1986-07-29 | 1988-02-23 |
Also Published As
Publication number | Publication date |
---|---|
JPS5662323A (en) | 1981-05-28 |
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