JPS5662323A - Reticle examination method - Google Patents

Reticle examination method

Info

Publication number
JPS5662323A
JPS5662323A JP13848079A JP13848079A JPS5662323A JP S5662323 A JPS5662323 A JP S5662323A JP 13848079 A JP13848079 A JP 13848079A JP 13848079 A JP13848079 A JP 13848079A JP S5662323 A JPS5662323 A JP S5662323A
Authority
JP
Japan
Prior art keywords
pattern
reticle
chip pattern
row
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13848079A
Other languages
Japanese (ja)
Other versions
JPS6131610B2 (en
Inventor
Masao Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13848079A priority Critical patent/JPS5662323A/en
Publication of JPS5662323A publication Critical patent/JPS5662323A/en
Publication of JPS6131610B2 publication Critical patent/JPS6131610B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To improve reliability by shortening the time required for inspection, by forming on a substrate pattern of reticle side by side with reference pattern prior to exposure treatment process and making an examination by comparing these two patterns with each other. CONSTITUTION:A chip pattern is baked in a row in the neighborbood of one end of a glass substrate 1 using a reticle, and this is used as a reference pattern. And then, by using the same reticle, a chip pattern 3 is baked in a row next to the row of the reference chip pattern immediately before opening of a window in the manufacturing process, and this chip pattern and the reference chip pattern are comparatively examined by an automatic examining device.
JP13848079A 1979-10-26 1979-10-26 Reticle examination method Granted JPS5662323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13848079A JPS5662323A (en) 1979-10-26 1979-10-26 Reticle examination method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13848079A JPS5662323A (en) 1979-10-26 1979-10-26 Reticle examination method

Publications (2)

Publication Number Publication Date
JPS5662323A true JPS5662323A (en) 1981-05-28
JPS6131610B2 JPS6131610B2 (en) 1986-07-21

Family

ID=15223050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13848079A Granted JPS5662323A (en) 1979-10-26 1979-10-26 Reticle examination method

Country Status (1)

Country Link
JP (1) JPS5662323A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679431A (en) * 1979-12-03 1981-06-30 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor integrated circuit device
JPS58210618A (en) * 1982-06-02 1983-12-07 Hitachi Ltd Method and apparatus for reduced projection exposure
JPS6216528A (en) * 1985-07-16 1987-01-24 Hoya Corp Substrate with al film
JPS6337617A (en) * 1985-10-31 1988-02-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Method of detecting defect on semiconductor substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6327212U (en) * 1986-07-29 1988-02-23

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679431A (en) * 1979-12-03 1981-06-30 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor integrated circuit device
JPS63943B2 (en) * 1979-12-03 1988-01-09 Cho Eru Esu Ai Gijutsu Kenkyu Kumiai
JPS58210618A (en) * 1982-06-02 1983-12-07 Hitachi Ltd Method and apparatus for reduced projection exposure
JPS6216528A (en) * 1985-07-16 1987-01-24 Hoya Corp Substrate with al film
JPS6337617A (en) * 1985-10-31 1988-02-18 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Method of detecting defect on semiconductor substrate
JPH046937B2 (en) * 1985-10-31 1992-02-07 Intaanashonaru Bijinesu Mashiinzu Corp

Also Published As

Publication number Publication date
JPS6131610B2 (en) 1986-07-21

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