JPH09275143A - Semiconductor integrated circuit mounting wafer and manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield without reducing the number of chips of a wafer and reduce manufacturing cost, by making the redundancy circuit area of a chip region positioned in the wafer peripheral part larger than the redundancy circuit area of a chip region positioned in the wafer central part. SOLUTION: After a pattern of a semiconductor chip having a redundancy circuit of normal size in the central part of a wafer 1 is formed, patterns of semiconductor chips 2, 3 having redundancy circuits 7 whose size are larger than a previous semiconductor integrated circuit are formed on a region containing a blank part of the wafer peripheral part. After semiconductor chips 2, 3 having large scale redundancy circuits 7 are formed, the semiconductor chips 2, 3 having small scale redundancy circuits 7 may be formed in the central part of the wafer 1. If a defective part detected by a test can be replaced with the redundancy circuit, after the semiconductor chips 2, 3 are formed on the wafer 1, replacement is performed. Thus relief probability of the imperfect semiconductor chips 2, 3 is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit mounting wafer and a method for manufacturing a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit mounting wafer having a redundant circuit and a method for manufacturing a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, in order to manufacture a large-scale integrated circuit (LSI), usually a plurality of rectangular chips are formed on a circular Si wafer by using a lithography technique. At that time, an extra portion where a semiconductor chip cannot be formed occurs in the peripheral portion of the wafer. On the other hand, in the case of LSIs, especially semiconductor memories, defective chips are actually produced at the same time even when they are mass-produced in a factory. Therefore, it is better to reduce defective chips and increase yield.
It is an important issue for SI manufacturing technology.

At present, especially in a semiconductor memory, in order to improve the yield, a redundancy circuit (redundancy circuit) which replaces a defective circuit is made in advance in the integrated circuit, and when the defect occurs, the redundancy circuit is formed. It is common to change defective chips to chips of both products using to improve the yield.

FIG. 6A is a plan view of a semiconductor wafer on which a plurality of semiconductor chips are formed, and FIG. 6B is a plan view of the semiconductor chip. 1 is a semiconductor wafer, 20
Is a semiconductor chip, 6 is a functional circuit section, and 7 is a redundancy circuit section. To increase the yield, each chip 2
0 has a redundancy circuit 7 of a certain scale.
Each chip 20 is inspected by a tester, and if the defective portion can be relieved by the redundancy circuit 7, it is replaced and relieved to be a good product, and the yield is increased. However, in reality, the number of defective portions was around the scale of the prepared redundancy circuit 7, and there were semiconductor chips that were defective.

If the size of the redundancy circuit section 7 in the chip is increased, the probability that a defective chip, which has been small due to the small size of the redundancy circuit section 7 until now, can be relieved and the yield can be increased. it can.
However, when the scale of the redundancy circuit section 7 is increased, the area of each chip 20 is increased and the number of chips 20 that can be formed on the wafer 1 is decreased, so that the manufacturing cost per chip becomes high. is there. Therefore, the scale of the redundancy circuit is currently determined so as to minimize the manufacturing cost.

[0006]

As described above, in the manufacture of the conventional semiconductor integrated circuit device, when the redundancy circuit is increased in scale in order to increase the yield, the chip area is increased and the number of chips per wafer is increased. Since there is a decrease, there is a problem that the manufacturing cost increases.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device which can increase the yield without reducing the number of chips per wafer and can reduce the manufacturing cost. is there.

[0008]

[Means for Solving the Problems]

(Structure) (1) In a semiconductor integrated circuit mounting wafer in which a plurality of semiconductor integrated circuits including redundant circuits are arranged in each chip area on a semiconductor wafer, of the chip area, redundancy of a chip area located in a peripheral portion of the wafer The circuit area was made larger than the redundant circuit area of the chip area located in the central portion of the wafer.

(2) The semiconductor wafer is divided into a plurality of chip areas, semiconductor integrated circuits including redundant circuits are formed in the respective chip areas, and the semiconductor wafer is cut along the chip areas to form a plurality of semiconductors. In the method of manufacturing a semiconductor integrated circuit device for producing an integrated circuit chip, the size of the redundant circuit in the chip area located in the peripheral portion of the wafer among the chip areas on the wafer Larger than the scale of.

(3) The semiconductor wafer is divided into a plurality of chip regions, semiconductor integrated circuits including redundant circuits are formed in the respective chip regions, and the semiconductor wafer is cut along the chip regions to form a plurality of semiconductors. In the method of manufacturing a semiconductor integrated circuit device for forming an integrated circuit chip, an additional redundant circuit is provided together with the original redundant circuit in the chip area located on the wafer peripheral portion of the chip area on the wafer.

(4) Of the chip area on the wafer,
The area of the chip region located in the peripheral portion of the wafer was made larger than the area of the chip region located in the central portion of the wafer. (5) The chip area located in the peripheral portion of the wafer includes a surplus area which is not used for chip formation when a plurality of rectangular chips having the same shape are arranged on a circular wafer.

(6) A silicon single crystal substrate, an SOI substrate, or a compound semiconductor substrate is used as the semiconductor wafer. (7) A mask used when forming a pattern in the chip area has a pattern of a semiconductor integrated circuit and a pattern of an additional redundant circuit provided adjacent to each side of the pattern.

(8) A pattern is formed in the chip area of the wafer by step & repeat while hiding the pattern of the additional redundant circuit described in (6) as appropriate. (9) The same pattern is formed in the chip area, and the pattern area of the semiconductor integrated circuit and the pattern area of the redundant circuit are appropriately hidden in the chip area of the wafer peripheral area by using the mask described in (6) above. Form.

(10) The chip area is not arranged in a fixed direction, but an additional redundant circuit is formed in the short side direction of the chip area. (Function) When the inventors investigated the cause of the defective chip, it was found that it was due to dust mixed during the manufacturing process, variation in the film thickness of the deposited film, variation in the etching rate, and the like. Further, it has been found that the cause of this defect is more remarkable especially in the peripheral portion of the wafer.

Therefore, when the redundancy circuits of the same scale are provided, the number of redundancy circuits in the peripheral portion of the wafer becomes insufficient, and the probability of defective products becomes higher than that of the central portion. For example, a chip at the center of the wafer can obtain a yield of almost 100%, while chips at the peripheral portion have a yield of about 70%.

Therefore, in the present invention, the scale of the redundancy circuit of the chip in the peripheral portion of the wafer is made larger than that of the chip in the central portion of the wafer.
By relieving a chip that has been defective due to a lack of a redundancy circuit in the related art, the yield of the peripheral portion of the wafer can be increased and the yield of the entire wafer can be increased.

Further, when forming a plurality of chips on a wafer in an array, there are regions in the wafer where the chips cannot be formed. Therefore, by forming an additional redundant circuit for peripheral chips in a region where chips cannot be formed, it is possible to prevent a decrease in the number of chips that can be obtained from one wafer.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1A is a plan view of a semiconductor wafer on which a plurality of semiconductor chips according to the first embodiment of the present invention are formed. Semiconductor chips 2 and 3 are arranged on the surface of the wafer 1. The semiconductor chip 2 in the central portion of the wafer 1 includes a redundancy circuit (redundancy circuit), which is not shown. The semiconductor chip 3 arranged in the peripheral portion of the wafer 1 is composed of the same circuit portion 4 as the semiconductor chip 2 in the central portion and an additional redundancy circuit portion 5. here,
The chips 2 and 3 substantially represent chip regions, and are finally cut out from the wafer to be chips.

The present invention includes a method of manufacturing a semiconductor integrated circuit device such as the chip itself cut out in this manner, or an IC or LSI mounted with this chip. Furthermore,
The present invention also includes a wafer on which a semiconductor integrated circuit before being cut out as a chip is mounted.

The wafer 1 has a region in which semiconductor chips cannot be formed because a chip pattern is formed and protrudes out of the wafer (this region is hereinafter referred to as a blank region). The additional redundancy circuit section 5 of the semiconductor chip 3 is arranged in the blank area on the wafer 1. The semiconductor wafer 1 is made of a silicon single crystal, an SOI substrate, a compound semiconductor substrate, or the like.

The structure of the semiconductor chips 2 and 3 will be described in more detail below. The semiconductor chip 2 in the central portion is shown in FIG.
As shown in, the functional circuit unit 6 for realizing a certain function
And a redundancy circuit section 7. Further, the semiconductor chip 3 in the peripheral portion is, as shown in FIG.
In addition to the same functional circuit section 6 and redundancy circuit section 7 of the central semiconductor chip, an additional redundancy circuit section 5
have.

For example, the functional circuit section 6 of the semiconductor chip is DR
When it is AM, spares corresponding to rows and columns are formed in the redundancy circuits 5 and 7. If there is a defect in a row, a column, or a memory cell in the memory array, it is replaced with the column or row in the redundancy circuits 5 and 7 and used as a good product.

Next, the manufacturing method will be described. Since the thin film formation, etching, etc. are no different from the steps for manufacturing a normal semiconductor chip, only the lithography step will be described. In the lithography process, the mask shown in FIG. 2 is used. A semiconductor integrated circuit pattern portion 9 including a normal redundancy circuit is formed in the central portion of the mask 8. Further, adjacent to the pattern 9, the additional redundancy circuit pattern portions 10a, 10b, 10c, 10 are provided.
d is formed.

Using the mask 8 described above, the pattern of each chip is sequentially formed by step & repeat. Here, when the pattern of the chip 2 in the central portion is formed, the mask 8 is used.
The pattern 10 is formed by hiding all of the patterns 10
When forming the pattern of the chip 3 in the peripheral portion, the patterns 8 and 10a or 10b are simultaneously formed by concealing the pattern other than the mask pattern 10a or 10b. As a result, a pattern of semiconductor chips is formed on the wafer 1 as shown in FIG.

A manufacturing method as described below may be used. A circuit pattern having redundancy circuits of the same scale is formed in the peripheral portion and the central portion on the wafer. afterwards,
An additional redundancy circuit part pattern is formed in the blank area of the wafer. At the time of forming the additional redundancy circuit pattern, the pattern can be formed by appropriately hiding and exposing the pattern using the mask of FIG. At this time, the pattern need not be formed in the central portion of the mask 8.

A layout different from that of FIG. 1 is shown. In FIG. 1, there are some chips in which the additional redundancy circuit 5 is not formed because the peripheral semiconductor chip 3 does not have a region for forming the additional redundancy circuit 5 on the long side of the chip. Therefore, as shown in FIG. 3, an additional redundancy circuit portion 5 may be formed on the short side of the semiconductor chip 11 in the peripheral portion of the wafer. Here, in order to form the pattern of the additional redundancy circuit 5 on the semiconductor chip 11 of FIG. 3, the upper side 10c or the lower side pattern 10d of the mask of FIG. 3 may be used appropriately.

A method different from the above-mentioned manufacturing method will be described. After forming a pattern of a semiconductor chip having a normal-scale redundancy circuit in the center of the wafer,
A pattern of a semiconductor chip having a redundancy circuit, which is larger in scale than the preceding semiconductor integrated circuit, may be formed in a region including a blank region in the peripheral portion of the wafer. In this manufacturing method, a semiconductor chip having a small redundancy circuit may be formed after forming a semiconductor chip having a large redundancy circuit.

In the case of this manufacturing method, instead of forming the additional redundancy circuit section in the blank area, the entire chip including the additional redundancy circuit section is formed as shown in FIG.
It can be formed in a region including a margin region.

After forming a semiconductor chip on a wafer, a test is conducted to find a defective portion, and if the defective portion can be replaced with a redundancy circuit, the defective portion is replaced with a redundancy circuit. Conventionally, a semiconductor chip, which has been defective due to lack of redundancy circuit in peripheral chips, has a higher probability of being salvaged in the present embodiment, so that the overall yield can be increased, and thus the manufacturing cost can be reduced. Can be lowered.

Furthermore, the manufacturing information 6a, 6b of each chip may be marked in the area of each semiconductor chip 2, 3. This manufacturing information includes information such as from which position on which wafer the chip is cut out. Therefore, if the scale of the redundant circuit of each chip and the positional relationship obtained from the manufacturing information have a correlation of the present invention, they are included in the present invention.

(Second Embodiment) FIG. 5A is a plan view of a semiconductor wafer on which a plurality of semiconductor chips according to the second embodiment of the present invention is formed. FIG. 5B shows a semiconductor. It is a top view of a chip. Here, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof is omitted. The feature of this embodiment is that the semiconductor chips 2 and 3 are not arranged in a fixed direction. Further, an additional redundancy circuit section 5 is formed in the peripheral side in the short side direction of the semiconductor chip 3.

In this case, the lateral widths of the central chip 2 and the peripheral chip 3 are constant. Then, for example, the semiconductor chip 3 can be formed without changing the position of the bonding pad. Therefore, the steps such as the inspection by the tester, the subsequent cutting of the chip, the housing in the package, and the wire bonding can be performed relatively easily as compared with the previous embodiment. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

[0033]

EFFECTS OF THE INVENTION By forming a redundant circuit on a chip in the peripheral portion of a semiconductor wafer, which is larger in size than the chip in the central portion of the wafer, by utilizing a region where the chip cannot be formed,
The yield can be increased without reducing the number of chips per wafer.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor wafer and a single chip according to a first embodiment.

FIG. 2 is a plan view showing a mask when forming a semiconductor chip in the first embodiment.

FIG. 3 is a plan view (1) showing another example of the layout according to the first embodiment.

FIG. 4 is a plan view (2) showing another example of the layout according to the first embodiment.

FIG. 5 is a plan view showing a semiconductor wafer and a single chip according to the second embodiment.

FIG. 6 is a plan view showing a wafer having a plurality of conventional semiconductor chips formed thereon and a single chip.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor wafer 2 ... Semiconductor chip 3 ... Semiconductor chip 4 ... Circuit part 5 ... Additional redundancy circuit part 6 ... Functional circuit part 7 ... Redundancy circuit part 8 ... Mask 9 ... Semiconductor integrated circuit mask 10 ... Additional redundancy circuit mask 11 ... Semiconductor Tip

Claims (6)

[Claims] 1. A semiconductor integrated circuit mounting wafer in which a plurality of semiconductor integrated circuits including a redundant circuit are arranged in each chip area on a semiconductor wafer, and in the chip area, a redundant circuit in a chip area located in a peripheral portion of the wafer. A semiconductor integrated circuit mounted wafer having an area larger than a redundant circuit area of a chip region located in the center of the wafer. 2. A semiconductor wafer is divided into a plurality of chip regions, a semiconductor integrated circuit including a redundant circuit is formed in each chip region, and then the semiconductor wafer is cut along the chip region to form a plurality of semiconductor integrated circuits. In a method of manufacturing a semiconductor integrated circuit device for creating a circuit chip, in the chip area on the wafer, the scale of the redundant circuit in the chip area located in the peripheral portion of the wafer is A method for manufacturing a semiconductor integrated circuit device, wherein the method is larger than the scale. 3. A semiconductor wafer is divided into a plurality of chip regions, a semiconductor integrated circuit including a redundant circuit is formed in each chip region, and then the semiconductor wafer is cut along the chip region to form a plurality of semiconductor integrated circuits. In a method of manufacturing a semiconductor integrated circuit device for producing a circuit chip, an additional redundant circuit is provided together with an original redundant circuit in a chip region located on a peripheral portion of a wafer among chip regions on the wafer. Method of manufacturing circuit device. 4. The chip area on the wafer, of the chip area located in the peripheral area of the wafer, is larger than the area of the chip area located in the central area of the wafer. A method for manufacturing the semiconductor integrated circuit device described. 5. A chip region located at the peripheral portion of the wafer includes a region which is a surplus region which is not used for chip formation when a plurality of rectangular chips having the same shape are arranged on a circular wafer. The method for manufacturing a semiconductor integrated circuit device according to claim 1, 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a silicon single crystal substrate, an SOI substrate, or a compound semiconductor substrate is used as the semiconductor wafer.