JP3057767B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging semiconductor integrated circuit chips (hereinafter referred to as IC chips), and more particularly to a method of arranging IC chips of different sizes on a semiconductor substrate.

[0002]

2. Description of the Related Art In some cases, a plurality of types of IC chips having different sizes for trial testing are formed on the same semiconductor substrate.

As shown in FIG. 3, the first conventional method for arranging IC chips is to provide first and second chip patterns 5 and 6 having different sizes adjacent to each other. A reticle 4 having a light-shielding band 7 provided around the chip patterns 2 and 3 is prepared. As shown in FIG. 4, the chip patterns 5 and 6 of the reticle 4 are simultaneously exposed on the semiconductor substrate 1 by a reduced projection exposure method. They are arranged to form IC chips 2 and 3. However, this arrangement method has a problem that the number of IC chips 2 and 3 cannot be changed even when it is desired to reduce the number of IC chips 3 to half or less of the number of IC chips 2, resulting in a large waste.

In order to improve the above problem, a second conventional method of arranging IC chips employs a light emitting method for exposing light between a first chip pattern 5 and a second chip pattern 6 as shown in FIG. As shown in FIG. 6, a reticle 4b provided with a light-shielding band 3 for preventing
IC chip 2 or 3 is formed on semiconductor substrate 1 by exposing one of chip pattern 5 and chip pattern 6 on b to light while exposing it to light. The IC chip 3 can be formed by simultaneously forming the chip patterns 5 and 6 of the reticle 4b and exposing the adjacent IC chip 2 and IC chip 3 at the same time. In this method, a chip unformed region 8 other than the region corresponding to the light-shielding band 3 on the reticle is formed on the semiconductor substrate 1.

[0005]

According to the first conventional method of arranging IC chips, as shown in FIG.
Only the same number of C chips 2 and 3 can be formed on a semiconductor substrate. Further, in the second method, as shown in FIG. 6, IC chips 2 and 3 having different sizes can be formed in different numbers on the semiconductor substrate, but the chip unformed areas are formed on the semiconductor substrate. Sometimes. In such a case, a difference occurs in the pattern density per unit area between a region near the chip unformed region and a region distant from the region where the chip is not formed, causing a variation in the etching rate in the etching of the semiconductor substrate in the etching. A region closer to the region having a lower pattern density has a higher etching rate, so that the line width of the pattern becomes narrower, and there has been a problem that variations in pattern dimensions, abnormal shapes, and the like occur in the semiconductor substrate surface.

[0006]

The features of the present invention relate to each other.
First and second patterns having different sizes are formed.
Preparing a reticle, the first pattern of the reticle;
The second pattern with respect to the semiconductor substrate in a state where light is shielded.
The semiconductor substrate by performing reduced projection exposure of the
Then, while leaving the unexposed area, the second pattern
Provided in an array to block the second pattern of the reticle.
In the lighted state, the unexposed area on the semiconductor substrate is
Performing the reduced projection exposure of the first pattern
The present invention is to provide the first pattern in the unexposed area .

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram for explaining an embodiment of the present invention, and FIG. 2 is a plan view of a reticle used to constitute the embodiment of FIG.

As shown in FIGS. 1 and 2, a reticle 4 having a light-shielding band 7 provided between and around a first chip pattern 5 and a second chip pattern 6 is used. In a state where the chip pattern 6 is shielded from light, reduction projection exposure of the chip pattern 5 is performed, and an IC is formed on the semiconductor substrate 1.
The chips 2 are selectively arranged. At this time, an unexposed area is provided at a predetermined position. Next, an unexposed area is exposed in a state where the chip pattern 5 of the reticle is shielded from light,
The chip 3 is formed.

Here, the length B of the chip pattern 6 in the vertical direction is set to a value which is a fraction of the length A of the chip pattern 5 in the vertical direction. Can be formed without leaving.

The dimensions of the IC chip area are not limited to two types, and three or more types of IC chip areas in which the dimension of one side of the IC chip area is an integral multiple or a fraction of an integer may be formed in combination. It is possible.

[0012]

As described above, according to the present invention, a plurality of IC chips having different sizes are combined and formed on a semiconductor substrate, and a chip arrangement can be efficiently performed without generating a chip unformed area. This has the effect of preventing the occurrence of variations in pattern dimensions between chips, abnormalities in shape, etc., which occur in later steps such as etching.

[Brief description of the drawings]

FIG. 1 is a layout diagram for explaining an embodiment of the present invention.

FIG. 2 is a plan view of a reticle used to construct the embodiment of FIG.

FIG. 3 is a plan view of a reticle used to configure a first conventional method for arranging IC chips.

FIG. 4 is a layout diagram showing a first arrangement method of a conventional IC chip.

FIG. 5 is a plan view of a reticle used for configuring a second conventional method for arranging IC chips.

FIG. 6 is a layout diagram showing a second method of arranging conventional IC chips.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 3 IC chip 4 Reticle 5, 6 Chip pattern 7 Shielding band 8 Chip unformed area

Continuation of front page (56) References JP-A-2-306611 (JP, A) JP-A-55-132039 (JP, A)

Claims (3)

(57) [Claims] 1. A first and a second package having different sizes from each other.
Prepare a reticle with a turn formed, and
When the first pattern is shielded from light with respect to the semiconductor substrate,
By performing reduced projection exposure of the second pattern
On the semiconductor substrate, while leaving an unexposed area,
A second pattern is provided in an array, and the second pattern of the reticle is provided.
2 on the semiconductor substrate in a state where the pattern 2 is shielded from light.
Reduced projection exposure of the first pattern to unexposed areas
The first pattern in the unexposed area
The method of manufacturing a semiconductor integrated circuit device characterized by providing a. 2. A vertical or horizontal direction of the second pattern.
The process according to claim 1, the semiconductor integrated circuit device according to the length of the is equal to or an integer multiple of the first pattern. 3. The first package formed on the reticle.
A light-shielding band between and around the turn and the second pattern
The method of manufacturing a semiconductor integrated circuit device according to claim 1 or 2, wherein the provided.