JP2005283609A - Reticle for reduction projection aligner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reticle capable of increasing the mounting number of chips, by preventing the generation of chipping of metals. <P>SOLUTION: The reticle 1 for a reduction projection aligner is provided with a substrate 3. The substrate 3 is provided with a plurality of substantially same size pattern regions 5 and a scribe line region 7, arranged in between the two adjacent pattern regions 5. At least one of the pattern regions 5 is an alignment mark arranged region 5a, and the residue is a body chip pattern region 5b. A body chip pattern 9 is formed on each body chip pattern region 5b, and the chip pattern is not formed on the alignment mark arrangement region 5a, and an alignment mark 11 is arranged. Since the alignment mark need not be arranged on the scribe line region 7, the width of the scribe line region 7 can be made narrow, and the mounting number of the chips can be increased. In addition, since the alignment mark need not be formed on a metal film of the scribe line region 7, generation of the chipping of the metal can be suppressed in a dicing process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reticle for a reduction projection exposure apparatus, and more particularly to a reticle for a reduction projection exposure apparatus having a feature in the arrangement of alignment marks.

  The manufacture of a semiconductor device usually includes a plurality of photolithography processes. In recent years, the photolithography process is mainly performed using a stepper (reduction projection exposure apparatus). The stepper is attached with a reticle for a reduction projection exposure apparatus in which a predetermined pattern is formed, and a predetermined pattern is formed on the wafer by exposing the wafer through the reticle. An alignment mark is usually formed on the reticle, and is used for alignment between the reticle and the wafer.

As an alignment mark arrangement method, a method of arranging an alignment mark in a scribe line area between two adjacent main body chip pattern areas, and a method of arranging an alignment mark in a process control module (PCM) area are known. (For example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 3-18012

  However, when the alignment mark is arranged in the scribe line area, the scribe line area needs to have a sufficient width. Therefore, in this case, it is difficult to increase the number of chips (the number of mounted chips) formed on one wafer by narrowing the width of the scribe line region. Also, in the metal wiring process, alignment marks are formed on the metal film in the scribe line region, but this metal film is usually not removed in the subsequent process, and metal chips are generated during dicing, thereby improving the yield. It causes a decrease.

  When the alignment mark is arranged in the PCM area, there is no problem as described above. However, the PCM area may have a larger area than the main body chip, and in that case, forming the number of PCM areas necessary for wafer alignment on the wafer reduces the number of chips. Connection is undesirable.

  The present invention has been made in view of such circumstances, and provides a reticle that can prevent the generation of metal chips and increase the number of chips.

  A reticle for reduced projection exposure apparatus of the present invention comprises a plurality of pattern regions having substantially the same size on a substrate and a scribe line region disposed between two adjacent pattern regions. At least one of them is an alignment mark arrangement area, and the rest is a main body chip pattern area. A main body chip pattern is formed in each main body chip pattern area, and an alignment mark is arranged in the alignment mark arrangement area.

  According to the reticle for reduced projection exposure apparatus of the present invention, it is not necessary to arrange alignment marks in the scribe line area, so that the width of the scribe line area can be narrowed and the number of mounted chips can be increased. In addition, since it is not necessary to form alignment marks on the metal film in the scribe line region, generation of metal chips can be suppressed in the dicing process.

  In addition, since the reticle for reduced projection exposure apparatus of the present invention includes the alignment mark arrangement region, the alignment mark can be easily arranged even when the number of alignment marks increases. Further, when the alignment mark arrangement area is smaller than the PCM area, the number of chips mounted can be increased as compared with the case where the alignment mark is formed in the PCM area.

  A reticle for reduced projection exposure apparatus of the present invention comprises a plurality of pattern regions having substantially the same size on a substrate and a scribe line region disposed between two adjacent pattern regions. At least one of them is an alignment mark arrangement area, and the rest is a main body chip pattern area. A main body chip pattern is formed in each main body chip pattern area, and an alignment mark is arranged in the alignment mark arrangement area.

  The substrate can be formed of a material having a high transmittance with respect to light used for exposure of the wafer. Specifically, for example, the substrate can be formed of synthetic quartz. The pattern formed on the substrate can be formed, for example, by a process of forming a film of metal chromium or the like on the substrate and patterning the film by electron beam lithography or the like.

  A plurality of pattern regions having substantially the same size are formed on the substrate. At least one of these pattern areas is an alignment mark arrangement area. Preferably, one of these pattern areas is an alignment mark arrangement area. This is to make the area used for the alignment mark arrangement as small as possible and to secure as many chips as possible. For example, when the area of the pattern region is small, a plurality of pattern regions may be used as the alignment mark arrangement region.

An alignment mark is arranged in the alignment mark arrangement region. The alignment mark is preferably arranged only in the alignment mark arrangement region. Moreover, it is preferable that the main body chip pattern is not formed in the alignment mark arrangement region.
The alignment mark arrangement area preferably includes an alignment mark arrangement prohibition area, and the alignment mark arrangement prohibition area is preferably formed at a position close to the main body chip pattern area. The reason is as follows. When the reticle of the present invention is used to expose a wafer with a stepper, there are a step of printing alignment marks on the wafer and a step of not printing. In the step of not printing the alignment mark on the wafer, the alignment mark arrangement region is usually covered with a reticle blind. The alignment mark placement prohibition area is provided near the main body chip pattern area in the alignment mark arrangement area, even when the position of the reticle blind is shifted, the alignment mark does not appear on the main body chip (double exposure). It is for doing so. In addition, the size of the alignment mark prohibited area is approximately 1.5 to 6 mm in consideration of the accuracy of the model.

  The remainder of the plurality of pattern areas is the main body chip pattern area. A main body chip pattern is formed in the main body chip pattern area, but when there are a plurality of main body chip pattern areas, a different main body chip pattern may be formed in each main body chip pattern area. .

  Other patterns such as an overlay measurement pattern may be formed in each main body chip pattern region. The overlay measurement pattern is used to confirm whether or not the alignment between the wafer and the reticle is appropriate. The overlay measurement pattern may be singular or plural. The overlay measurement patterns are preferably provided at the four corners of the main body chip pattern region.

  When a plurality of alignment marks are formed on the substrate, some of them may be formed in each main body chip pattern region. This is because if there is an area in the main body chip pattern area where the main body chip pattern is not formed, that area can be used effectively.

  Since the alignment mark arrangement area and the main body chip pattern area are “substantially the same size”, even if the alignment mark arrangement area is provided, the arrangement of the main body chip pattern area is not disturbed (see FIG. 2). ). Therefore, “substantially the same size” includes cases where the sizes are different within a range in which the effect of the present invention can be obtained.

  It is preferable that no alignment mark is arranged in a scribe line region arranged between two adjacent pattern regions. This is because in this case, the width of the scribe line region can be reduced. Specifically, for example, the width of the scribe line region can be 1 to 110 μm, and preferably 1 to 30 μm. By making it smaller than 110 μm, the number of chips can be increased. The width of the scribe line region is preferably as small as possible. For example, when dicing is performed using a dicing blade or a laser, the scribe line region has a predetermined width, specifically about 1 μm or more in order to perform dicing. It is preferable.

  The substrate preferably further includes a basic element pattern region for characteristic evaluation, and the basic element pattern for characteristic evaluation is formed in the basic element pattern region for characteristic evaluation. By forming the basic element for characteristic evaluation on the wafer, it can be confirmed whether or not the manufactured semiconductor device has satisfactory performance.

  An alignment mark may or may not be formed in the basic element pattern region for characteristic evaluation. However, even when the alignment mark is formed, when the wafer is exposed using the reticle of the present invention, when the alignment mark in the alignment mark arrangement region is printed on the wafer, the basic element pattern for characteristic evaluation is used. Since the region is usually covered with a reticle blind or the like, the alignment mark in the basic element pattern region for characteristic evaluation is usually not used for wafer alignment.

  Next, a wafer exposure method using the reduced projection exposure apparatus reticle of the present invention will be described.

  First, using the above-described reticle for reduced projection exposure apparatus, alignment marks are printed on at least three places on the wafer, preferably eight or more places. At this time, the main body chip pattern and the alignment mark are preferably printed at the same time. Further, it is preferable that the alignment marks are evenly arranged on the wafer. This alignment mark is used for wafer alignment.

  Next, the main body chip pattern is baked on the wafer in a state where the basic element pattern area for characteristic evaluation and the alignment mark arrangement area are covered with the reticle blind. At this time, a portion for baking the basic element pattern for characteristic evaluation in a later process is left open.

Next, the basic element pattern for characteristic evaluation is baked on the portion that has been vacated in the previous step. About five basic element patterns for characteristic evaluation are preferably formed and arranged uniformly on the wafer.
Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a plan view of a reticle 1 for a reduction projection exposure apparatus according to Embodiment 1 of the present invention. In FIG. 1, hatched lines indicate that a predetermined pattern is formed. The reduction projection exposure apparatus reticle 1 includes a substrate 3. The substrate 3 includes a plurality of pattern regions 5 having substantially the same size, and a scribe line region 7 disposed between two adjacent pattern regions 5. At least one of the pattern areas 5 is an alignment mark arrangement area 5a, and the rest is a main body chip pattern area 5b. A main body chip pattern 9 is formed in each main body chip pattern region 5b. A main body chip pattern is not formed in the alignment mark arrangement region 5a, and the alignment mark 11 is arranged. No alignment mark is arranged in the scribe line area 7. The overlay accuracy measurement pattern 13 is formed in the main body chip pattern region 5b. The overlay accuracy measurement pattern 13 is arranged at each corner in each main body chip pattern region 5b so that the overlay accuracy in each shot can be grasped.

The substrate 3 includes a basic element pattern region 15 for characteristic evaluation, and a basic element pattern 17 for characteristic evaluation is formed in the basic element pattern region 15 for characteristic evaluation.
In the alignment mark arrangement area 5a, an alignment mark arrangement prohibition area 19 is formed, and the alignment mark arrangement prohibition area 19 is formed at a position close to the main body chip pattern area. The right end of the alignment mark placement prohibited area 19 is approximately 1.5 to 6 mm away from the left end of the alignment mark placement area 5a. Arranged at a position 1.5 to 6 mm apart is a value that takes into account the reticle blind accuracy of the reduction projection exposure apparatus (depending on the model), and prevents the alignment mark from appearing on the chip (double exposure). Because of that.

  Next, a wafer exposure method using the reticle of the first embodiment will be described with reference to FIG. FIG. 2 is a plan view of a wafer 31 exposed by a stepper using the reticle of the first embodiment. On the wafer 31, the main body chip pattern 9, the alignment mark 11, and the characteristic evaluation basic element pattern 17 are baked in the main body chip pattern area 5b, the alignment mark arrangement area 5a, and the characteristic evaluation basic element pattern area 15, respectively. Yes.

  First, the base layout grid 33 of the wafer layout is input to the stepper with a pitch size that combines the main body chip pattern region 5b and the alignment mark arrangement region 5a, and the main body chip pattern 9 and the alignment mark 11 are simultaneously placed on the wafer 31. Bake in 9 places (minimum 3 places). It is preferable to arrange the baking portions evenly on the wafer 31.

  Next, the main body chip pattern 9 is baked in the empty space of the wafer 31. At this time, spaces having the size of the basic element pattern region 15 for characteristic evaluation are provided at five locations on the wafer 31.

  Next, the basic element pattern 17 for characteristic evaluation is printed on the space on the wafer 31 to complete the exposure of the wafer 31.

  When a plurality of alignment marks 11 are formed in the same row, the interval between two adjacent alignment marks 11 is set to an integral multiple of the pitch size of the area of the main body chip alone, thereby overlapping shots (double exposure). ).

  Next, with respect to an A chip having a size of 1.5 mm × 10.0 mm and a B chip having a size of 2.0 mm × 15.0 mm, the relationship between the scribe line width and the number of mounted chips was simulated on an 8-inch wafer. It was. The results are shown below.

A chip

B chip

  The rate of increase in the number of mounted chips was determined based on the number of mounted chips when the scribe line width was 110 μm. As is clear from Tables 1 and 2, it can be seen that the number of mounted chips increases as the scribe line width decreases. This result shows that the number of chips can be increased according to the reticle for reduced projection exposure apparatus of the present invention.

It is a top view which shows the reticle for reduction projection exposure apparatuses which concerns on Example 1 of this invention. It is a top view which shows the wafer which exposed using the reticle which concerns on Example 1 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reducing projection exposure apparatus reticle 3 Substrate 5 Pattern area 7 Scribe line area 5a Alignment mark placement area 5b Main body chip pattern area 9 Main body chip pattern 11 Alignment mark 13 Overlay accuracy measurement pattern 15 Basic element pattern area for characteristic evaluation 17 Characteristics Basic element pattern for evaluation 31 Wafer 33 Array lattice

Claims (7)

  A plurality of pattern areas having substantially the same size and a scribe line area arranged between two adjacent pattern areas are provided on a substrate, and at least one of the pattern areas is an alignment mark arrangement area The remainder is a main body chip pattern area, a main body chip pattern is formed in each main body chip pattern area, and an alignment mark is arranged in the alignment mark arrangement area.   The reticle according to claim 1, wherein the alignment mark arrangement area includes an alignment mark arrangement prohibition area, and the alignment mark arrangement prohibition area is formed at a position close to the main body chip pattern area.   The reticle according to claim 1, wherein an overlay measurement pattern is further formed in each main body chip pattern region.   The reticle according to claim 1, wherein the alignment mark is arranged only in an alignment mark arrangement region.   The reticle according to claim 1, wherein the scribe line region has a width of 1 to 110 μm.   The reticle according to claim 1, wherein the substrate further includes a basic element pattern region for characteristic evaluation, and the basic element pattern for characteristic evaluation is formed in the basic element pattern region for characteristic evaluation.   A method for aligning a semiconductor wafer, comprising: forming alignment marks at least at three locations on the wafer using the reticle according to claim 1; and performing alignment of the wafer using the formed alignment marks.

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