JP5533204B2 - Reticle and semiconductor device manufacturing method - Google Patents

Description

  The present invention relates to a reticle for forming a semiconductor chip and a test element group (TEG), a method for manufacturing a semiconductor device using such a reticle, and a semiconductor wafer manufactured using such a reticle. .

  In order to evaluate the quality and the like of the semiconductor device, a test element group (hereinafter referred to as TEG) is formed. The TEG can be formed on a semiconductor wafer at the same time as a semiconductor chip to be a product.

  The manufacturing process of a semiconductor chip or TEG includes an exposure process in which a mask pattern formed on a reticle is transferred to a resist on a semiconductor wafer. The mask pattern of the semiconductor chip and the mask pattern of the TEG can be formed on the same reticle.

  There are various types of TEGs depending on the item to be evaluated. If the types of TEGs to be formed can be increased, more items can be evaluated. For this reason, there are cases where it is desired to form a plurality of types of mask patterns related to TEG formation on the same reticle together with a mask pattern related to semiconductor chip formation. A technique for efficiently arranging a mask pattern for forming a semiconductor chip and a mask pattern for forming a plurality of types of TEGs on the same reticle is desired.

Japanese Patent Laid-Open No. 3-197949

  An object of the present invention is to provide a reticle in which a mask pattern for forming a semiconductor chip and a mask pattern for forming a plurality of types of TEGs are arranged in a novel design.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device using such a reticle and a semiconductor wafer manufactured using such a reticle.

According to one aspect of the present invention, a TEG disposition light-shielding band includes a chip region in which a mask pattern for forming a semiconductor chip is formed, and a scribe region disposed around the chip region. Are arranged, and the first TEG region is sized to be included in the TEG arrangement light-shielding band. The chip patterning region and the first TEG region in which the mask pattern for forming the first TEG is formed. A first TEG patterning region and a second TEG region in which a mask pattern for forming a second TEG is formed, and the second TEG region is sized to be included in the TEG arrangement light shielding band; It possesses a first 2TEG patterning area, the first 1TEG patterning area, including the blank region disposed around the first 1TEG region The outer edge of the margin area is sized to include the TEG arrangement shading band, and a first overlay inspection pattern is formed in the TEG arrangement shading band, and the margin area has the first overlay inspection pattern. A reticle is provided on which a second overlay inspection pattern that is paired with one overlay inspection pattern is formed .

  In the exposure for transferring the chip patterning area, the unexposed portion can be formed by transferring the TEG arrangement shading band to the scribe area. In the subsequent exposure, the first TEG region related to the first TEG formation or the second TEG region related to the second TEG formation can be appropriately selected and transferred into the unexposed portion. In this way, a plurality of types of TEGs can be formed.

  The first TEG patterning region and the second TEG patterning region are prepared separately from the chip patterning region. As a result, a plurality of types of TEGs can be formed, and an increase in the area of the chip patterning region is suppressed, and a decrease in the number of effective chips is suppressed.

FIG. 1 is a schematic plan view showing a reticle design according to the first embodiment of the present invention and a printing layout when exposure is performed with the reticle of the first embodiment. 2A to 2C are schematic plan views showing the semiconductor wafer in a state where primary exposure, secondary exposure, and tertiary exposure are finished in the first embodiment, respectively. FIG. 3 is a schematic plan view showing the vicinity of the TEG arrangement light-shielding band and the vicinity of the first TEG patterning region in the chip patterning region of the reticle according to the embodiment (the relationship between the sizes of the regions is shown). FIG. 4 is a schematic plan view showing the vicinity of the TEG arrangement shading band and the vicinity of the first TEG patterning region in the chip patterning region of the reticle of the embodiment (showing the overlay inspection pattern). FIG. 5 is a schematic plan view showing the reticle design of the second embodiment. FIG. 6A is a schematic plan view showing the design of the reticle of the third embodiment, and FIGS. 6B and 6C are schematic plan views showing the printing layout when exposure is performed with the reticle of the third embodiment. 7A to 7C are schematic plan views showing the semiconductor wafer in a state where the primary exposure, the secondary exposure, and the tertiary exposure are finished in the third embodiment, respectively. FIG. 8 is a schematic plan view showing the relationship between the reticle placed on the exposure apparatus and the masking unit of the exposure apparatus. FIG. 9 is a schematic plan view showing a reticle design of the first comparative example and a printing layout when exposure is performed with the reticle of the first comparative example. FIG. 10 is a schematic plan view showing the semiconductor wafer in a state where the exposure to the entire surface is completed in the first comparative example. FIG. 11 is a schematic plan view showing a reticle design of the second comparative example and a printing layout when exposure is performed with the reticle of the second comparative example. FIG. 12 is a schematic plan view showing a reticle design of the third comparative example and a printing layout in the case of exposing with the reticle of the third comparative example.

  First, with reference to FIG. 8, a general structure of a reticle and an exposure area setting method in an exposure apparatus will be described. FIG. 8 is a schematic plan view showing the relationship between the reticle ret placed on the exposure apparatus and the masking unit mu of the exposure apparatus.

  The reticle ret is formed to include a translucent substrate 101 and a light shielding member arranged on the translucent substrate 101 by forming a desired light shielding pattern. For example, quartz is used as the light-transmitting substrate material, and chromium is used as the light shielding material.

  The effective patterning region 102 including the center of the translucent substrate 101 (reticle plate center) is a region where pattern transfer can be performed with high accuracy by the lens of the exposure apparatus. Inside the effective patterning region 102, a patterning region 103 on which a mask pattern to be transferred onto the semiconductor wafer is formed is disposed.

  In the example shown in FIG. 8, a chip region 103a on which a mask pattern for one semiconductor chip is formed and a scribe region 103b arranged around the chip region 103a are transferred onto a semiconductor wafer by one exposure. Patterning region 103. The light shielding band 104 surrounds the outside of the patterning region 103, and the edge of the opening of the light shielding band 104 defines the edge of the patterning region 103.

  The masking unit mu includes four masking blades 201 and a control unit 202 that moves each masking blade 201 to a desired position. The inside of the opening 105 defined by the inner edges of the four masking blades 201 is an exposure region where the reticle ret is irradiated with light. The edge of the masking blade 201 is disposed slightly outside the edge of the patterning region 103 within the width of the light shielding band 104. As a result, the entire region in the patterning region 103 is pattern-transferred, and the outer region of the light shielding band 104 is shielded from light. Each masking blade 201 can be moved so that a desired exposure area is set according to the design of the reticle ret.

  Next, prior to the description of the reticle according to the embodiment of the present invention, the reticles of the first to third comparative examples will be described.

  First, the first comparative example will be described with reference to FIGS. 9 and 10. FIG. 9 is a schematic plan view showing a reticle design of the first comparative example and a printing layout when exposure is performed with the reticle of the first comparative example.

  The design of the reticle ret of the first comparative example will be described. As described with reference to FIG. 8, the patterning region 3 is arranged in the effective patterning region 2. The reticle patterning region 3 of the first comparative example includes two chip regions M1 and a scribe region 3a disposed around both chip regions M1. A scribe center 3aC is defined at the center in the width direction of the scribe region 3a. One chip area M1 is arranged in the X direction (horizontal direction on the paper surface), and two chip areas M1 are arranged in the Y direction (vertical direction on the paper surface) to form a 1 × 2 type block reticle. .

  A light shielding band 4 surrounds the outside of the patterning region 3. As described with reference to FIG. 8, at the time of exposure, the edge of the masking blade is disposed slightly outside the edge of the patterning region 3 within the width of the light shielding band 4, and the reticle ret is irradiated with light. Region 5 is defined.

  A TEG region M2 in which a mask pattern for forming a TEG is formed is arranged in a scribe region 3a between chip regions M1 arranged in the Y direction. In general, the TEG is formed for evaluating a new design, a new material, and a new process in a development stage of a semiconductor device, and performing a quality evaluation in a mass production stage. Various types of TEGs are formed depending on the item to be evaluated. The type of TEG is represented with an alphabet. In the reticle of the first comparative example, a mask pattern for forming one kind of TEG-A is formed in the TEG region M2.

  The printing layout of the first comparative example will be described. On the semiconductor wafer 10, the patterning regions 3 of the reticle ret to be reduced and projected are arranged without gaps. However, the adjacent patterning regions 3 on the semiconductor wafer 10 are arranged such that the scribe regions 3a overlap each other with the scribe centers 3aC aligned. Note that the region on the reticle ret and the region on the semiconductor wafer 10 onto which this region is projected may be indicated by the same name or reference numeral.

  The first comparative example has a layout in which regions each having two chip regions M1 as one unit are arranged. The edge of the unit area is indicated by a bold line. For each unit region, the TEG region M2 (that is, TEG-A) is arranged in the scribe region 3a between the two chip regions M1.

  The chip area M1 that enters the inside of the chip effective area boundary 11 that is a few mm (for example, 5 mm) inside the edge of the semiconductor wafer 10 is an effective chip as a product, and the semiconductor wafer 10 outside the chip effective area boundary 11 is outside the chip effective area boundary 11. The chip area M1 that overlaps the edge becomes an invalid chip that cannot be produced. Invalid chips are shown with diagonal lines. Note that the chip effective area boundary refers to the product guarantee area, and is different for each semiconductor device manufacturer.

  Next, an exposure process using the reticle ret of the first comparative example will be described. First, a photosensitive resist is applied on the semiconductor wafer 10. Spin coating can be used for resist coating.

  Next, the semiconductor wafer 10 is placed at the first exposure position on the wafer stage. Although the wafer stage has a function of rotating the semiconductor wafer 10 in the plane, the semiconductor wafer 10 is not rotated in the first comparative example. That is, the setting of the rotation angle is 0 °. In a third embodiment to be described later, the rotation angle is set to other than 0 °.

  Next, a masking blade is disposed at a position that defines the exposure region 5 including the patterning region 3.

  Then, the first exposure position on the semiconductor wafer 10 is exposed. Further, while moving the semiconductor wafer 10 on the wafer stage, the projection image of the patterning region 3 is scanned on the semiconductor wafer 10 to repeat the exposure, and the entire surface of the semiconductor wafer 10 is exposed.

  FIG. 10 is a schematic plan view showing the semiconductor wafer 10 in a state where the exposure to the entire surface is completed. On the semiconductor wafer 10, a plurality of chip regions M1 are arranged in a matrix with a scribe region 3a interposed therebetween. The TEG area M2 related to the formation of TEG-A is transferred onto the scribe area 3a between the two chip areas M1 to which the pattern has been transferred simultaneously by one exposure. When the exposure of the entire surface of the semiconductor wafer 10 is completed, development processing is performed.

  In the exposure using the reticle of the first comparative example described above, only one type of TEG (TEG-A) can be formed.

  Next, a second comparative example will be described with reference to FIG. FIG. 11 is a schematic plan view showing a reticle design of the second comparative example and a printing layout when exposure is performed with the reticle of the second comparative example.

  The design of the reticle ret of the second comparative example will be described. The reticle patterning region 3 of the second comparative example includes one chip region M1 and a scribe region 3a arranged around the chip region M1. A scribe center 3aC is defined in the scribe region 3a. A 1 × 1 type single reticle is formed in which one chip area M1 is arranged in the X direction (horizontal direction on the paper) and one chip area M1 is arranged in the Y direction (vertical direction on the paper surface). ing.

  Since the first comparative example was a 1 × 2 type block reticle, the TEG region could be arranged in the scribe region between the two chip regions arranged in the patterning region. Since the second comparative example is a single reticle, the TEG region cannot be disposed in the scribe region between the adjacent chip regions in the patterning region 3, and the TEG region is included in the scribe region around the patterning region 3. An area will be arranged.

  However, a mask pattern for forming an alignment mark or the like is disposed in the scribe region 3 a around the patterning region 3. Therefore, in the second comparative example, the width of the scribe region portion that is long in the Y direction on the right side of the chip region M1 is widened, and the TEG region related to the formation of the TEG-A is formed inside the scribe center 3aC (chip region M1 side). M2 is arranged.

  The printing layout of the second comparative example will be described. Since the second comparative example is a single reticle, it has a layout in which regions each having one chip region M1 as one unit are arranged. For each unit region, the TEG region M2 (that is, TEG-A) is arranged in the scribe region 3a on the right side of the chip region M1.

  Similar to the first comparative example, the chip area M1 that enters the inside of the chip effective area boundary 11 that is several mm (for example, 5 mm) inside the edge of the semiconductor wafer 10 is the effective chip that becomes the product, The chip region M1 that overlaps the edge of the semiconductor wafer 10 on the outer side from 11 becomes an invalid chip that cannot be manufactured. In the reticle design of the second comparative example, the width of the scribe region 3a is increased in order to arrange the TEG region. As the scribe region width is expanded, the area of the patterning region 3 is increased, so that the number of effective chips per semiconductor wafer 10 may be reduced.

  Even when the reticle of the second comparative example is used, similarly to the first comparative example, the projected image of the patterning region 3 is scanned on the semiconductor wafer 10 and the entire surface of the semiconductor wafer 10 is exposed. Similarly to the first comparative example, the reticle of the second comparative example can form only one type of TEG (TEG-A).

  Next, a third comparative example will be described with reference to FIG. FIG. 12 is a schematic plan view showing a reticle design of the third comparative example and a printing layout in the case of exposing with the reticle of the third comparative example.

  In the third comparative example, a 1 × 1 type single reticle is formed as in the second comparative example. The difference from the second comparative example is that a TEG region M3 in which a mask pattern for forming a second type of TEG (TEG-B) is formed is added.

  The second TEG region M3 is disposed adjacent to the first TEG region M2. In the third comparative example, since the second TEG region M3 is added, the width of the scribe region 3a on the right side of the chip region M1 is further expanded as compared with the second comparative example.

  In the third comparative example, two types of TEGs, that is, both TEG-A and TEG-B can be formed. As the number of types of TEG increases, the number of items that can be evaluated from the TEG increases. For example, the development period of a semiconductor device can be shortened.

  However, if the number of TEG types is increased, the number of TEG regions formed on the reticle is increased, and the area of the scribe region must be increased. If the area of the scribe region is increased, the area of the patterning region including the chip region is increased, and the number of effective chips per one semiconductor wafer 10 is reduced.

  For example, also for the 1 × 2 block reticle described in the first comparative example, if an attempt is made to add a TEG region related to the formation of the second or more types of TEGs, the width of the scribe region at the periphery of the patterning region may be increased, The width of the scribe region between adjacent chip regions is increased, and the area of the patterning region increases.

  Therefore, a reticle having a design capable of forming a plurality of types of TEGs while suppressing an increase in the area of the patterning region including the chip region (that is, suppressing a decrease in the number of effective chips) is desired.

  Next, a reticle according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic plan view showing a reticle design of the first embodiment and a printing layout in the case of exposure with the reticle of the first embodiment.

  The design of the reticle ret of the first embodiment will be described. In the reticle of the first embodiment, three patterning regions 31 to 33 are arranged in the effective patterning region 2.

  The chip patterning region 31 includes two chip regions M1 and a scribe region 31a disposed around both chip regions M1. Similarly to the first comparative example (see FIG. 9), one chip area M1 is arranged in the X direction (the horizontal direction on the paper surface), and two chip areas M1 are arranged in the Y direction (the vertical direction on the paper surface). A 1 × 2 type block reticle is formed.

  A mask pattern for forming a desired semiconductor chip is formed in each chip region M1. A scribe center 31aC is defined at the center in the width direction of the scribe region 31a. A mask pattern for forming an alignment mark or the like is formed in the scribe region 31a around the chip patterning region 31 as necessary.

  In the first comparative example, the TEG region M2 is disposed in the scribe region 3a between the chip regions M1 arranged in the Y direction of the patterning region 3. In the first embodiment, no TEG area is arranged in the scribe area 31a between the chip areas M1 arranged in the Y direction in the chip patterning area 31, and a light shielding band 31b for TEG arrangement that is long in the X direction is formed. ing. Note that the center of the chip patterning region 31 (the center of the TEG arrangement light shielding band 31b) coincides with the center of the translucent substrate 1 (reticle plate center).

  A first TEG patterning region 32 and a second TEG patterning region 33 are formed in a vacant region outside the chip patterning region 31. TEG regions M2 and M3 are disposed in the first and second TEG patterning regions 32 and 33, respectively.

  The first TEG patterning region 32 includes a first TEG region M2 in which a mask pattern for forming TEG-A is formed, and a blank region 32a disposed around the first TEG region M2.

  The second TEG patterning region 33 includes a second TEG region M3 in which a mask pattern for forming TEG-B is formed, and a blank region 33a disposed around the second TEG region M3.

  The first TEG patterning region 32 is arranged on the upper side in the Y direction of the chip patterning region 31 with the length direction of the first TEG region M2 being aligned with the length direction of the light shielding band 31b for TEG arrangement to be the X direction.

  The second TEG patterning region 33 is arranged on the upper side in the Y direction of the first TEG patterning region 32 with the length direction of the second TEG region M3 being aligned with the length direction of the light shielding strip 31b for TEG placement.

  As will be described later with reference to FIG. 4, the TEG arrangement light shielding band 31 b in the chip patterning region 31, the blank region 32 a in the first TEG patterning region 32, and the blank region 33 a in the second TEG patterning region 33 include An overlay inspection pattern is formed.

  The TEG arrangement light-shielding band 31b is a light-shielding area in all areas except for the portion where the overlay inspection pattern is formed. The blank area 32a and the blank area 33a are all light-transmitting areas except for the portion where the overlay inspection pattern is formed.

  A light shielding band 4 is formed outside the chip patterning region 31 and the first and second TEG patterning regions 32 and 33. The light shielding band 4 is referred to as the outer light shielding band 4 in order to distinguish it from the TEG arrangement light shielding band 31b. The outer light-shielding band 4 corresponds to the light-shielding band 4 described in the first comparative example and demarcates the edges of the patterning regions 31 and the like. The light shielding band 4 of the first comparative example or the like was formed with a narrow width so as to expose the translucent substrate 1 on the outer side, but in the first embodiment (and the second and third embodiments). The outer light shielding band 4 is formed on the entire surface up to the edge of the translucent substrate 1 except for the opening that exposes the patterning regions 31 and the like.

  When the chip patterning region 31 is exposed, the edge of the masking blade is disposed on the outer light shielding band 4 slightly outside the edge of the chip patterning region 31 to define the exposure region 51. The exposure region 51 includes the chip patterning region 31, but does not include the first and second TEG patterning regions 32 and 33, and only the chip patterning region 31 is transferred.

  When the first TEG patterning region 32 is exposed, the edge of the masking blade is arranged on the outer light shielding band 4 slightly outside the edge of the first TEG patterning region 32 to define the exposure region 52. The exposure region 52 includes the first TEG patterning region 32, but does not include the chip patterning region 31 and the second TEG patterning region 33, and only the first TEG patterning region 32 is transferred.

  At the time of exposure of the second TEG patterning region 33, the edge of the masking blade is arranged on the outer light shielding band 4 slightly outside the edge of the second TEG patterning region 33, thereby defining the exposure region 53. The exposure region 53 includes the second TEG patterning region 33, but does not include the chip patterning region 31 and the first TEG patterning region 32, and only the second TEG patterning region 33 is transferred.

  The printing layout of the first embodiment will be described. The chip patterning regions 31 of the reticle ret to be projected in a reduced size are arranged on the semiconductor wafer 10 without any gaps. However, the adjacent patterning regions 31 on the semiconductor wafer 10 are arranged such that the scribe regions 3a overlap each other with the scribe centers 3aC aligned. Similar to the first comparative example, the layout is such that two chip areas M1 are arranged as one unit.

  The arrangement of the TEG will be described. The TEG is arranged in the scribe area 31a between the two chip areas M1 for each unit area. The type of TEG is selected for each row in which the unit areas are arranged in the X direction (the horizontal direction on the paper). Specifically, TEG-A arrangement rows (M2 (TEG-A) exposure rows) and TEG-B arrangement rows (M3 (TEG-B) exposure rows) are alternately arranged.

  As will be described later with reference to FIG. 2, the chip patterning region 31 is transferred by primary exposure. At this time, the transfer portion of the TEG arrangement light shielding band 31b remains unexposed. In the exposure after the secondary exposure, the first TEG region M2 or the second TEG region M3 is transferred into the unexposed portion by the TEG arrangement light shielding band 31b. In this way, TEG-A or TEG-B can be formed.

  Note that, by alternately arranging the TEG-A arrangement rows and the TEG-B arrangement rows, for example, the TEG-A is arranged in a half area on the semiconductor wafer 10 and the other half area is collected. Compared to a layout in which TEG-B is arranged, both TEG-A and TEG-B can be distributed over a wide range on the semiconductor wafer 10. Thereby, data over a wide range on the semiconductor wafer 10 can be obtained from both TEG-A and TEG-B.

  A size example of each region on the reticle ret and the semiconductor wafer 10 will be described. For example, assume a 1/4 times reduced projection. The semiconductor wafer 10 has a diameter of 300 mm (12 inches), for example. In the following, an example of the size on the wafer is shown in parentheses after the example of the size on the reticle.

  The translucent substrate 1 is, for example, 152 mm in the X direction and 152 mm in the Y direction. The effective patterning region 2 is, for example, 104 mm (26 mm) in the X direction and 132 mm (33 mm) in the Y direction.

  The chip patterning region 31 is, for example, 56.88 mm (14.22 mm) in the X direction and 113.32 mm (28.33 mm) in the Y direction. One chip area M1 is, for example, 56 mm (14 mm) in the X direction and 56 mm (14 mm) in the Y direction. The width of the scribe region 31a is, for example, 440 μm (110 μm). The TEG arrangement shading band 31b is, for example, 55.992 mm (13.998 mm) in the X direction and 432 μm (108 μm) in the Y direction.

  The first TEG patterning region 32 (the blank region 32a of the first TEG patterning region) is, for example, 55.996 mm (13.999 mm) in the X direction and 436 μm (109 μm) in the Y direction. The first TEG region M2 is, for example, 53.2 mm (13.3 mm) in the X direction and 400 μm (100 μm) in the Y direction.

  The size of the second TEG patterning region 33 (the margin region 33a of the second TEG patterning region) is, for example, equal to the size of the first TEG patterning region 32 (the margin region 32a of the first TEG patterning region), and the size of the second TEG region M3 is, for example, , Equal to the size of the first TEG region M2. Note that the size of the TEG region can be different if the type of TEG is different.

  It should be noted that the width between the chip patterning region 31 and the first TEG patterning region 32 (that is, the width of the outer light-shielding band 4 in this portion) and the width between the first and second TEG patterning regions 32 and 33 (that is, this) The width of the outer light-shielding band 4 of the portion is, for example, 1500 μm on the reticle. The width of the outer light shielding band 4 disposed between the adjacent patterning regions needs to be thick enough to accurately position the edge of the masking blade within the width.

  Next, an exposure process using the reticle of the first embodiment will be described. First, a photosensitive resist is applied on the semiconductor wafer 10. Spin coating can be used for resist coating.

  Next, the semiconductor wafer 10 is placed at the first exposure position on the wafer stage. Note that the rotation angle of the wafer stage is set to 0 °.

  Next, the masking blade is disposed at a position that defines the exposure region 51 including the chip patterning region 31.

  Then, the first exposure position on the semiconductor wafer 10 is exposed. Further, while moving the semiconductor wafer 10 on the wafer stage, the projection image of the chip patterning region 31 is scanned on the semiconductor wafer 10 and the exposure is repeated to expose the entire surface of the semiconductor wafer 10. An exposure process on the entire surface of the wafer in the chip patterning region 31 is referred to as primary exposure.

  FIG. 2A is a schematic plan view showing the semiconductor wafer 10 in a state where the primary exposure has been completed. On the semiconductor wafer 10, a plurality of chip regions M1 are arranged in a matrix with a scribe region 31a therebetween. An unexposed portion 31b to which the TEG arrangement light shielding band 31b is transferred is left on the scribe region 31a between the two chip regions M1 to which the pattern is transferred simultaneously by one exposure.

  Next, the first TEG region M2 is transferred to the TEG-A arrangement row RA in which the unexposed portions 31b are defined every other row in the X direction. Specifically, first, the first TEG region M2 is aligned with the unexposed portion 31b that is first exposed.

  Next, the masking blade is disposed at a position that defines the exposure region 52 including the first TEG patterning region 32.

  Then, the first TEG region M2 is exposed to the first unexposed portion 31b. Further, while moving the semiconductor wafer 10 on the wafer stage, the projection image of the first TEG region M2 is scanned on the TEG-A arrangement row RA, and the first TEG region M2 is exposed to each unexposed portion 31b, and the entire surface of the wafer is exposed. The first TEG region M2 is transferred to the TEG-A arrangement row RA. The exposure process to the TEG-A arrangement row on the entire wafer surface in the first TEG patterning region 32 is referred to as secondary exposure.

  FIG. 2B is a schematic plan view showing the semiconductor wafer 10 in a state where the secondary exposure has been completed. The first TEG region M2 is transferred to the scribe region 31a on the TEG-A arrangement row RA. A row other than the TEG-A arrangement row RA in which the unexposed portions 31b are arranged in the X direction is a TEG-B arrangement row RB. The unexposed portion 31b remains in the TEG-B arrangement row RB.

  Next, the second TEG region M3 is transferred to the TEG-B arrangement row RB. Specifically, first, the second TEG region M3 is aligned with the unexposed portion 31b that is first exposed.

  Next, the masking blade is disposed at a position that defines the exposure region 53 including the second TEG patterning region 33.

  Then, the second TEG region M3 is exposed to the first unexposed portion 31b. Further, while moving the semiconductor wafer 10 on the wafer stage, the projection image of the second TEG region M3 is scanned on the TEG-B arrangement row RB, and the second TEG region M3 is exposed on each unexposed portion 31b, and the entire surface of the wafer is exposed. The second TEG region M3 is transferred to the TEG-B arrangement row RB. The exposure process to the TEG-B arrangement row on the entire wafer surface in the second TEG patterning region 33 is referred to as tertiary exposure.

  FIG. 2C is a schematic plan view showing the semiconductor wafer 10 in a state where the third exposure has been completed. The second TEG region M3 is transferred to the scribe region 31a on the TEG-B arrangement row RB, and the unexposed portion 31b does not remain.

  In this way, exposure using the reticle of the first embodiment is performed. The above-described arrangement of TEGs is an example. If necessary, it is possible to select which type of TEG is arranged for each unexposed portion 31b.

  When the primary to tertiary exposure is completed, a development process is performed to form a resist pattern. In the development process, the photosensitive portion is removed if the resist is a positive type, and the portions other than the photosensitive portion are removed if the resist is a negative type. A known technique can be used as appropriate for other processes related to semiconductor device manufacturing, such as an etching process after forming a resist pattern.

  As described above, with the reticle of the first embodiment, a plurality of types of TEGs can be formed without expanding the chip patterning region (that is, suppressing the decrease in the number of effective chips).

  Although the example in which the first and second TEG patterning regions 32 and 33 are collectively arranged above the chip patterning region 31 has been described, the first and second TEG patterning regions 32 and 33 can be collectively arranged below the chip patterning region 31. The chip patterning region 31 can be arranged separately above and below.

  Next, with reference to FIG. 3, the relationship between the size of the TEG arrangement shading band 31b and the size of the first TEG patterning region 32 and the like will be described. FIG. 3 is a schematic plan view showing the vicinity of the TEG arrangement shading band 31b and the vicinity of the first TEG patterning region 32 in the chip patterning region 31 of the reticle ret. Since the size condition regarding the second TEG patterning region 33 is the same as the size condition regarding the first TEG patterning region 32, the first TEG patterning region 32 will be described as a representative. In addition, the numerical example of the size given here indicates the size projected on the wafer.

  In the chip patterning region 31, a scribe region portion (inter-chip scribe region portion) 31aP between two chip regions M1 arranged in the Y direction has a size in the X direction that is equal to the size of the chip region M1 in the X direction and is MAX. The size in the Y direction is equal to the width of the scribe region 31a and is SCy. A TEG arrangement shading band 31b is arranged in the inter-chip scribe region portion 31aP. Regarding the size of the TEG arrangement shading band 31b, the X direction is Sx and the Y direction is Sy.

  Regarding the size of the first TEG patterning region 32, that is, the size of the margin region 32a (outer edge), the X direction is TAx and the Y direction is TAy. The first TEG area M2 is arranged inside the blank area 32a. The size of the first TEG region M2 is Tx in the X direction and Ty in the Y direction.

The conditions for the sizes in the X direction and the Y direction will be described. Each size in the X direction is
MAx = TAx + margin for misalignment (1)
TAx = Sx + margin for misalignment (2)
Sx> Tx (3)
Is set to satisfy the condition.

Each size in the Y direction is
SCy = TAy + position misalignment margin (1) ′
TAy = Sy + position misalignment margin (2) ′
Sy> Ty (3) ′
Is set to satisfy the condition.

  The expressions (3) and (3) ′ represent conditions that the first TEG region M2 has a size included in the TEG arrangement light shielding band 31b. If the first TEG region M2 is wider than the TEG arrangement light-shielding band 31b, an unexposed portion necessary for TEG formation cannot be secured, so the conditions of equations (3) and (3) ′ are required.

  The expressions (2) and (2) ′ represent a condition that the TEG arrangement light-shielding band 31b has a size included in the first TEG patterning region 32. That is, it represents a condition that the outer edge of the blank area 32a around the first TEG area M2 can include the TEG arrangement light shielding band 31b. If the TEG arrangement light-shielding band 31b is wider than the first TEG patterning area 32, the edge of the TEG arrangement light-shielding band 31b that protrudes outside the blank area 32a at the time of secondary exposure for transferring the first TEG patterning area 32. However, it will remain unexposed. The conditions of the expressions (2) and (2) ′ are required so that such unnecessary unexposed portions do not remain.

  The expressions (1) and (1) ′ represent a condition that the first TEG patterning region 32 has a size included in the inter-chip scribe region portion 31aP. If the first TEG patterning region 32 is wider than the inter-chip scribe region portion 31aP, the first TEG patterning region 32 is applied to the chip region M1 at the time of secondary exposure for transferring the first TEG patterning region 32. In order to avoid the first TEG patterning region 32 from being applied to the chip region M1, the conditions of the equations (1) and (1) ′ are required.

  Give examples of each size. The misalignment margins in the expressions (1), (1) ′, (2), and (2) ′ are each 1 μm, for example. The size MAx in the X direction of the chip region M1 is, for example, 14000 μm (14 mm). A size TAx in the X direction of the first TEG patterning region 32 (margin region 32a) is set to 13999 μm, for example. The size Sx in the X direction of the TEG arrangement shading band 31b is set to 13998 μm, for example. The size Tx in the X direction of the first TEG region M2 is, for example, 13300 μm.

  The width of the scribe region 31a, that is, the size SCy in the Y direction of the inter-chip scribe region portion 31aP is, for example, 110 μm. The size TAy in the Y direction of the first TEG patterning region 32 (margin region 32a) is set to 109 μm, for example. The size Sy in the Y direction of the TEG arrangement light-shielding band 31b is set to 108 μm, for example. The size Ty in the Y direction of the first TEG region M2 is, for example, 100 μm.

  Next, with reference to FIG. 4, an overlay inspection pattern (a misalignment inspection mark) formed on the TEG arrangement light shielding band 31 b and the like will be described. FIG. 4 is a schematic plan view showing the vicinity of the TEG arrangement light-shielding band 31 b and the vicinity of the first TEG patterning region 32.

  As described with reference to FIG. 2, in the exposure process using the reticle of the first embodiment, the TEG arrangement light shielding band 31b is transferred in the primary exposure. Then, the first TEG region M2 or the second TEG region M3 is transferred to the unexposed portion by the TEG arrangement light shielding band 31b by secondary or tertiary exposure. Thus, since the TEG arrangement shading band 31b and the first TEG region M2 or the second TEG region M3 are separately exposed, it is important that both are accurately aligned.

  Therefore, in order to inspect whether accurate alignment has been performed, an overlay inspection pattern is formed in the TEG arrangement light shielding band 31b, the first TEG patterning region 32, and the second TEG patterning region 33. Since the overlay inspection pattern formed in the first TEG patterning region 32 and the second TEG patterning region 33 is similar, the first TEG patterning region 32 will be described as a representative.

  As the overlay inspection pattern, for example, a bar-in-bar type pattern is used. In addition, an overlay inspection pattern of an appropriate type such as a box in box type or a vernier type can be used as necessary. FIG. 4 illustrates a bar in bar type.

  Overlay inspection patterns p11 and p12 are formed at both ends in the X direction (length direction) of the light shielding strip 31b for TEG placement, respectively. In the TEG arrangement light shielding band 31b, the overlay inspection patterns p11 and p12 are formed by arranging an opening pattern that transmits light.

  Overlay inspection patterns p21 and p22 are formed at both ends in the X direction (length direction) of the blank area 32a of the first TEG patterning area 32, that is, outside the both sides in the length direction of the first TEG area M2. .

  The overlay inspection pattern p11 on the left side of the TEG arrangement shading band 31b and the overlay inspection pattern p21 on the left side of the blank area 32a form a pair of overlapping patterns. The overlay inspection pattern p12 on the right side of the TEG arrangement light-shielding band 31b and the overlay inspection pattern p22 on the right side of the blank area 32a form a pair of overlapping patterns.

  If the overlay inspection pattern is accurately superimposed on the wafer by the secondary exposure to which the first TEG area M2 is transferred, it is determined that the accurate alignment has been performed. By disposing overlay inspection patterns on both sides in the length direction of the TEG region M2 (that is, one set with the TEG region M2 in between), the displacement inspection is favorably performed.

  In the example shown in FIG. 4, the overlay inspection patterns p11 to p22 are formed at the endmost part of the TEG arrangement light shielding band 31b and the blank area 32a. Not exclusively.

  In the first TEG patterning region 32, the overlay inspection patterns p21 and p22 can be arranged at desired positions in the blank region portion 32aP on both sides in the length direction of the first TEG region M1. Then, corresponding overlay inspection patterns p11 and p12 can be arranged on both end portions 31bP of the TEG arrangement light-shielding band 31b on which these blank area portions 32aP are overlaid during exposure.

  In this way, the TEG arrangement light shielding band 31b is used as an arrangement area for a desired type of TEG and also as an area for forming an overlay inspection pattern. The margin area 32a and the like around the TEG area are used for erasing an unexposed portion by the TEG arrangement light shielding band 31b and also used as an area for forming an overlay inspection pattern.

  Next, a reticle according to the second embodiment will be described with reference to FIG. FIG. 5 is a schematic plan view showing the reticle design of the second embodiment. Hereinafter, differences from the first embodiment will be described.

  In the reticle of the first embodiment, in addition to the chip patterning region 31, first and second TEG patterning regions 32 and 33 for forming two types of TEGs are arranged. In the reticle of the second embodiment, two more TEG types are added, and third and fourth TEG patterning regions 34 and 35 are added.

  In the reticle ret of the second embodiment, the center of the chip patterning region 31 is offset downward from the reticle plate center retC in the Y direction. Thereby, the space which can arrange | position the 1st-4th TEG patterning area | regions 32-35 collectively on the Y direction upper side of the chip | tip patterning area | region 31 is ensured.

  The third TEG patterning region 34 includes a third TEG region M4 in which a mask pattern for forming TEG-C is formed, and a blank region 34a disposed around the third TEG region M4. The fourth TEG patterning region 35 includes a fourth TEG region M5 in which a mask pattern for forming TEG-D is formed, and a blank region 35a disposed around the fourth TEG region M5. The size conditions of the third and fourth TEG patterning regions 34 and 35 and the formation of the overlay inspection pattern are the same as those of the first and second TEG patterning regions 32 and 33.

  A third TEG patterning region 34 is disposed above the second TEG patterning region 33 in the Y direction, and a fourth TEG patterning region 35 is disposed above the third TEG patterning region 34 in the Y direction. When the third TEG patterning region 34 is exposed, the exposure region 54 defined by the masking blade includes the third TEG patterning region 34, but does not include the other patterning regions 31 and the like. Further, when the fourth TEG patterning region 35 is exposed, the exposure region 55 defined by the masking blade includes the fourth TEG patterning region 35, but does not include the other patterning regions 31 and the like.

  Thus, by properly offsetting the center of the chip patterning region 31 from the center of the reticle plate, a space for arranging a plurality of TEG patterning regions 32 and the like can be secured.

  The exposure process using the reticle of the second embodiment is basically the same as the exposure process of the first embodiment. However, positioning is performed with an offset added. Specifically, the alignment mark coordinates input to the exposure apparatus can be set as follows. As a first method, a mark coordinate obtained by adding a difference from the reticle plate center to the mark coordinate at the center of the chip patterning region 31 is input. As a second method, a mark coordinate at the center of the chip patterning region 31 is input, and processing that takes into account the difference from the reticle plate center is performed by the offset function of the exposure apparatus.

  The TEG arrangement on the wafer is, for example, a TEG-A arrangement line (M2 (TEG-A) exposure line), a TEG-B arrangement line (M3 (TEG-B) exposure line), or a TEG-C arrangement line. A structure in which (M4 (TEG-C) exposure rows) and TEG-D arrangement rows (M5 (TEG-D) exposure rows) are arranged can be repeated in the column direction. Such a TEG arrangement is an example. It is possible to select which type of TEG is arranged for each unexposed portion 31b as necessary.

  As described above, the reticle of the second embodiment can form more types of TEG than the first embodiment without expanding the chip patterning region.

  Next, a reticle according to the third embodiment will be described with reference to FIGS. FIG. 6A is a schematic plan view showing the reticle design of the third embodiment. Hereinafter, differences from the first embodiment will be described.

  In the reticle of the first embodiment, the first and second TEG patterning regions 32 and 33 are arranged outside the chip patterning region 31 in the Y direction. In the reticle ret of the third embodiment, the first and second TEG patterning regions 32 and 33 are arranged outside the chip patterning region 31 in the X direction (for example, on the right side).

  Along with the arrangement outside the chip patterning region 31 in the X direction, each of the first and second TEG patterning regions 32 and 33 is designed to be rotated by 90 ° with respect to the first embodiment. Thereby, the length direction of the 1st and 2nd TEG patterning area | regions 32 and 33 turns into a Y direction. At the same time, the exposure regions 52 and 53 for exposing the first and second TEG patterning regions 32 and 33 are also designed to be rotated by 90 °.

  The empty area outside the chip patterning area 31 has an elongated shape along the side of the chip area M1 if the empty area is not unnecessarily widened. Therefore, the empty area outside the chip patterning area 31 in the X direction has an elongated shape in the Y direction. In the third embodiment, by setting the length direction of the first and second TEG patterning regions 32 and 33 to the Y direction, the first and second TEG patterning regions 32, 33 is easy to arrange. The size conditions of the first and second TEG patterning regions 32 and 33 and the formation of the overlay inspection pattern are the same as in the first embodiment.

  6B and 6C are schematic plan views showing a printing layout in the case of exposing with the reticle of the third embodiment. The printing layout of the third embodiment is the same as that of the first embodiment (see FIG. 1). 6B shows the posture of the semiconductor wafer 10 (in-plane rotation angle 0 °) during the period of primary exposure (exposure of the chip patterning region 31), and FIG. 6C shows secondary and tertiary exposure (first and third exposures). The posture (in-plane rotation angle 90 °) of the semiconductor wafer 10 during the period of exposure of the second TEG patterning regions 32 and 33 is shown.

  However, the rotation directions of the first and second TEG patterning regions 32 and 33 on the reticle are aligned with the rotation direction of the semiconductor wafer 10 during the secondary and tertiary exposure periods. As will be described in the following exposure process, by aligning the rotational directions of the two, the direction of the TEG in the printing layout becomes the same as that of the first embodiment. Hereinafter, the description will be continued assuming that the rotation angle is + 90 ° (90 ° counterclockwise). If necessary, the rotation angle can be set to -90 ° (90 ° clockwise).

  Next, an exposure process using the reticle of the third embodiment will be described. First, a photosensitive resist is applied on the semiconductor wafer 10. Then, as in the first embodiment, the chip patterning region 31 is transferred onto the entire wafer surface. That is, primary exposure is performed. In the primary exposure, as shown in FIG. 6B, the setting of the rotation angle of the wafer stage is 0 °.

  FIG. 7A is a schematic plan view showing the semiconductor wafer 10 in a state where the primary exposure has been completed. This state is the same as the state in which the primary exposure is completed in the first embodiment (see FIG. 2A). That is, the unexposed portion 31b is left between two chip regions M1 to which the pattern is transferred simultaneously by one exposure.

  Next, the first TEG region M2 is transferred to the TEG-A arrangement row RA in which the unexposed portions 31b are defined every other row in the X direction. That is, secondary exposure is performed. Specifically, first, as shown in FIG. 6C, the rotation angle of the wafer stage of the exposure apparatus is set to + 90 °, and the semiconductor wafer 10 is rotated.

  For this reason, in the secondary exposure, positioning is performed in consideration of wafer rotation. Specifically, the alignment mark coordinates input to the exposure apparatus are values obtained by converting the XY coordinates according to the wafer rotation angle. For example, it is assumed that a certain mark coordinate is X = 1000 μm and Y = 1000 μm at a wafer rotation angle of 0 °. If the wafer rotation angle in the secondary exposure is + 90 °, the mark coordinates after the wafer rotation are X = −1000 μm and Y = 1000 μm.

  The process after the wafer rotation is basically the same as the secondary exposure in the first embodiment except that the scanning direction is rotated by 90 ° corresponding to the wafer rotation.

  That is, after the wafer is rotated, the first TEG region M2 is aligned with the unexposed portion 31b that is first exposed, and the masking blade is disposed at a position that defines the exposure region 52. Then, the first TEG region M2 is exposed to the first unexposed portion 31b. Further, while moving the semiconductor wafer 10 on the wafer stage, the projection image of the first TEG region M2 is scanned on the TEG-A arrangement row RA, and the first TEG region M2 is exposed to each unexposed portion 31b, and the entire surface of the wafer is exposed. The first TEG region M2 is transferred to the TEG-A arrangement row RA.

  FIG. 7B is a schematic plan view showing the semiconductor wafer 10 in a state where the secondary exposure is completed. The first TEG region M2 is arranged on the TEG-A arrangement row RA, and the unexposed portion 31b is left on the TEG-B arrangement row RB.

  Next, the second TEG region M3 is transferred to the TEG-B arrangement row RB. That is, tertiary exposure is performed. In the third exposure, exposure is performed with the semiconductor wafer 10 rotated by + 90 ° following the second exposure. The third embodiment is basically the same as the third exposure in the first embodiment except that the scanning direction is rotated by 90 ° corresponding to the wafer rotation.

  FIG. 7C is a schematic plan view showing the semiconductor wafer 10 in a state where the third exposure has been completed. The second TEG region M3 is transferred on the TEG-B arrangement row RB, and the unexposed portion 31b does not remain. In this way, exposure using the reticle of the third embodiment is performed.

  The rotation direction of the first and second TEG patterning regions 32 and 33 on the reticle and the rotation direction of the semiconductor wafer 10 during the secondary and tertiary exposure periods are aligned, so that the direction of the TEG in the printing layout However, the orientation is the same as that of the first embodiment.

  As described above, even if the reticle of the third embodiment is used, a plurality of types of TEGs can be formed without expanding the chip patterning region as in the first embodiment.

  In the third embodiment, the example in which the first and second TEG patterning regions 32 and 33 are collectively arranged on the right side of the chip patterning region 31 has been described. However, the first and second TEG patterning regions 31 and 33 may be collectively arranged on the left side of the chip patterning region 31. It is also possible to arrange the chip patterning region 31 separately on the left and right sides.

  It is possible to combine the techniques of the first and second embodiments and the third embodiment. That is, the TEG patterning region can be arranged by selecting one of the empty regions above, below, left, and right of the chip patterning region 31 as necessary. Further, if necessary, the chip patterning region 31 can be offset in a desired direction to change the size of the empty region.

  In the third embodiment, separate files are prepared for primary exposure, secondary exposure, and tertiary exposure as exposure files for giving instructions to the exposure apparatus. This is because the wafer cannot be rotated during the processing related to one exposure file.

  In the first embodiment (and the second embodiment), primary to tertiary exposure can be processed with one exposure file. The masking blade opening area changing process (that is, the patterning area changing process) can be performed within one exposure file. It is also possible to change the masking blade opening area for each shot.

  As described above, in the first to third embodiments, the 1 × 2 type block reticle has been described as an example, but the technology of the first to third embodiments is applied to other types of block reticles and single reticles. can do.

  In other words, the reticle design includes a chip patterning region including a chip region and a scribe region, in which a light shielding band for TEG placement is arranged in place of the TEG region conventionally arranged in the scribe region, and separately from the chip patterning region. The TEG patterning region including the TEG region is disposed. A plurality of TEG patterning regions can be arranged so that a plurality of types of TEGs can be formed.

  In the exposure, first, primary exposure for transferring the chip patterning region is performed. In the primary exposure, the transferred portion of the TEG arrangement shading band is unexposed. In the second and subsequent exposures, the selected desired TEG region can be transferred to the unexposed portion.

  In this manner, a plurality of types of TEGs can be easily formed using a single reticle. Since there is no need to expand the chip patterning area, even if a plurality of types of TEGs are formed, the number of effective chips can be kept from decreasing.

  When the TEG is formed using the technique of the above embodiment, the overlay inspection pattern is transferred in the vicinity of the TEG region. According to the transferred overlay inspection pattern, an overlay inspection pattern structure is formed on the semiconductor wafer (the overlay inspection pattern structure formed on the wafer is also simply referred to as an overlay inspection pattern). Accordingly, when the TEG is formed using the technique of the embodiment, the overlay inspection pattern remains in the vicinity of the TEG on the semiconductor wafer.

  For example, in the above-described embodiment, an example in which a semiconductor chip and a plurality of types of TEGs are formed on the same semiconductor wafer has been described. The usage mode of the reticle of the embodiment is not limited to this. For example, a semiconductor wafer and only one kind of TEG-A are formed on a certain semiconductor wafer, and only one semiconductor chip and another kind of TEG-B are formed on another semiconductor wafer. A usage mode is also conceivable in which the type of TEG to be formed is changed for each semiconductor wafer.

  It should be noted that an alignment mark is formed on a semiconductor substrate (for example, an Si substrate) before the initial stage of semiconductor device formation (usually the element isolation step), so that the embodiment can be performed from the initial stage of semiconductor device formation. The TEG formation process can be started.

  The TEG formation process according to the embodiment includes primary exposure that defines an unexposed portion and secondary exposure that transfers a TEG region to the unexposed portion, and requires alignment between the unexposed portion and the TEG region. . If the alignment mark is already formed, it is possible to satisfactorily perform the alignment related to the TEG formation process of the embodiment from the initial stage of the semiconductor device formation. For example, electron beam lithography can be used to form such alignment marks.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

Regarding the embodiment including the first to third examples described above, the following additional notes are further disclosed.
(Appendix 1)
A chip patterning region including a chip region in which a mask pattern for forming a semiconductor chip is formed and a scribe region disposed around the chip region, and a TEG disposition light-shielding band disposed in the scribe region; ,
A first TEG patterning region including a first TEG region in which a mask pattern for forming a first TEG is formed, the first TEG region having a size included in the TEG arrangement light-shielding band;
A reticle having a second TEG patterning region that includes a second TEG region in which a mask pattern for forming a second TEG is formed, and the second TEG region is sized to be included in the TEG arrangement light-shielding band .
(Appendix 2)
The reticle according to claim 1, wherein the first TEG patterning region includes a blank region arranged around the first TEG region, and an outer edge of the blank region is sized to include the TEG light-shielding band. .
(Appendix 3)
The reticle according to appendix 2, wherein the blank area is sized to be included in the scribe area in which the TEG arrangement shading band is arranged.
(Appendix 4)
The first overlay inspection pattern is formed on the TEG arrangement shading band, and the second overlay inspection pattern that is paired with the first overlay inspection pattern is formed on the blank area. 3. The reticle according to 3.
(Appendix 5)
The reticle according to any one of supplementary notes 1 to 4, wherein a length direction of the TEG arrangement light-shielding band and a length direction of the first TEG region are parallel to each other.
(Appendix 6)
The reticle according to any one of supplementary notes 1 to 4, wherein a length direction of the light shielding band for TEG arrangement intersects with a length direction of the first TEG region.
(Appendix 7)
A chip patterning region including a chip region in which a mask pattern for forming a semiconductor chip is formed and a scribe region disposed around the chip region, and a TEG disposition light-shielding band disposed in the scribe region; ,
A first TEG patterning region including a first TEG region in which a mask pattern for forming a first TEG is formed, the first TEG region having a size included in the TEG arrangement light-shielding band;
A reticle having a second TEG patterning region that includes a second TEG region in which a mask pattern for forming a second TEG is formed, and the second TEG region is sized to be included in the TEG arrangement light-shielding band A method of manufacturing a semiconductor device using
A chip region exposure step for transferring the chip patterning region of the reticle to a semiconductor wafer on which a resist is formed;
A method of manufacturing a semiconductor device, comprising: a TEG region exposure step of transferring the first TEG region or the second TEG region of the reticle into an unexposed portion to which the TEG arrangement shading band is transferred in the chip region exposure step. .
(Appendix 8)
The first TEG patterning area includes a blank area arranged around the first TEG area, and an outer edge of the blank area is sized to include the TEG arrangement shading band,
8. The method of manufacturing a semiconductor device according to appendix 7, wherein in the TEG area exposure step, the first TEG area is transferred such that the blank area includes the unexposed portion to which the TEG arrangement light-shielding band is transferred. .
(Appendix 9)
A plurality of semiconductor chip regions arranged side by side;
A scribe region disposed between adjacent semiconductor chip regions;
A semiconductor wafer comprising: a first TEG arranged in the scribe region; and an overlay inspection pattern formed in the scribe region in the vicinity of the first TEG.
(Appendix 10)
The semiconductor wafer according to appendix 9, further comprising a second TEG that is disposed in the scribe region and has a different type from the first TEG.

ret reticle 1 translucent substrate 2 effective patterning region 31 chip patterning region M1 chip region 31a scribe region 31aC scribe center 31b light shielding strip 32 for TEG placement first TEG patterning region M2 first TEG region 32a margin region 33 second TEG patterning region M3 second TEG Area 33a margin area 4 outer light shielding band 51 exposure area 52 (corresponding to the chip patterning area) exposure area 53 (corresponding to the first TEG patterning area) exposure area 53 (corresponding to the second TEG patterning area) 10 semiconductor wafer 11 chip effective area Boundary RA TEG-A placement row RB TEG-B placement row p11, p12, p21, p22 Overlay inspection pattern

Claims (4)

A chip patterning region including a chip region in which a mask pattern for forming a semiconductor chip is formed and a scribe region disposed around the chip region, and a TEG disposition light-shielding band disposed in the scribe region; ,
A first TEG patterning region including a first TEG region in which a mask pattern for forming a first TEG is formed, the first TEG region having a size included in the TEG arrangement light-shielding band;
It includes a first 2TEG region where the mask pattern is formed for forming the second TEG, the first 2TEG region is sized to be contained in the light-shielding band for TEG-placement, possess a first 2TEG patterned region ,
The first TEG patterning area includes a blank area arranged around the first TEG area, and an outer edge of the blank area is sized to include the TEG arrangement shading band,
A reticle in which a first overlay inspection pattern is formed on the TEG arrangement light-shielding band, and a second overlay inspection pattern that is paired with the first overlay inspection pattern is formed in the blank area . A chip patterning region including a chip region in which a mask pattern for forming a semiconductor chip is formed and a scribe region disposed around the chip region, and a TEG disposition light-shielding band disposed in the scribe region; ,
A first TEG patterning region including a first TEG region in which a mask pattern for forming a first TEG is formed, the first TEG region having a size included in the TEG arrangement light-shielding band;
It includes a first 2TEG region where the mask pattern is formed for forming the second TEG, the first 2TEG region is sized to be contained in the light-shielding band for TEG-placement, possess a first 2TEG patterned region ,
The first TEG patterning area includes a blank area arranged around the first TEG area, and an outer edge of the blank area is sized to include the TEG arrangement shading band,
A reticle in which a first overlay inspection pattern is formed on the TEG arrangement light-shielding band and a second overlay inspection pattern that is paired with the first overlay inspection pattern is formed in the blank area is used. A method for manufacturing a semiconductor device, comprising:
A chip region exposure step for transferring the chip patterning region of the reticle to a semiconductor wafer on which a resist is formed;
In the chip region exposing step, the unexposed a portion TEG placement shielding band has been transferred, the semiconductor device having a TEG region exposing step of transferring the first 1TEG patterning region or the second 2TEG patterning area of the reticle Production method. The semiconductor device according to claim 2, further comprising a step of inspecting whether or not patterns corresponding to the first and second overlay inspection patterns transferred to the semiconductor wafer overlap each other. Production method. In the reticle, the direction in which the light shielding strip for TEG arrangement extends differs from the direction in which the first TEG patterning region and the second TEG patterning region extend,
4. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of rotating the semiconductor wafer or the reticle between the chip region exposure step and the TEG region exposure step.

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