JPH10335605A - Manufacture of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the defect generation cause of a semiconductor element, by arranging chip address display patterns showing positions in a wafer, in the vicinity of a semiconductor element region, and changing the number or the form of the chip address display patterns, according to the movement of an exposure region of the semiconductor element region. SOLUTION: Chip address showing patterns (patterns) 3 composed of a plurality of circular patterns having the same size are formed in a chip address showing region 2 which shows the position of a semiconductor forming region 1 in a wafer. By a stepper, the patterns 3 are formed while the number of patterns 3 is reduced every chip 4 when the chip 4 is repeatedly exposed. By the number of the patterns 3, recognition of a chip address is enabled, and a cause that generated the defect can be detected in a short time in cause analysis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for displaying a position (ie, a chip address) of a plurality of semiconductor devices in a wafer formed on the wafer.

[0002]

2. Description of the Related Art Conventionally, a chip address display pattern indicating a position of a semiconductor element (chip) in a wafer is electrically connected to a bonding pad under the film on a passivation protection film made of a silicon nitride film or the like provided in a final step. Therefore, in the photolithography step for making holes, a pattern such as a number is provided in an opening on the final passivation protective film in a portion where a circuit or the like is not formed.

Usually, the processing of the final passivation protective film is to make a hole of about 100 μm on the bonding pad, and the alignment accuracy has a margin of several μm. The address display pattern can also be provided for each chip in a 1: 1 photomask, and no particular problem has occurred.

The chip address can be easily obtained by observing the chip address display pattern using a metallographic microscope even after the wafer is diced from a wafer to individual chips, assembled into a package, and then becomes a finished device. You can know. Therefore, if a chip is found in the process of selecting a defective product or in the market, knowing whether the chip was located at the center or the peripheral portion of the wafer will determine the cause of the failure. Above, help get important clues.

[0005]

However, recently, D
RAM (dynamic random access memory)
For example, the integration and miniaturization of semiconductor devices have been advanced, and a 5: 1 reduction projection exposure apparatus (ie,
Exposure using a stepper) is performed, and even in the photolithography step of the final passivation protective film, 5: 1
Reduced exposure is becoming necessary.

In the 5: 1 reduction exposure, the same photolithography pattern is repeatedly exposed by step and repeat, so that a chip address display pattern could not be provided conventionally.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing chip address display even when applying reduced exposure to all photolithography steps.

[0008]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a wafer. Wherein a chip address display pattern indicating a position in the wafer is provided, and the number or shape of the chip address display pattern is changed according to the movement of the exposure region in the semiconductor element region.

Further, the same number of the chip address display patterns are provided for each of the semiconductor element regions, and each time the exposure region is moved, the exposure range is changed to change the number. .

According to the present invention, the chip address can be displayed on a completed device even if the reduced exposure is applied to all the photolithography steps.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings described below, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Embodiment 1 FIG. 3 is an overall schematic plan view of a wafer to which a method of manufacturing a semiconductor device according to the present invention is applied.

Reference numeral 5 denotes a wafer, and 6 denotes a chip (semiconductor element). Arrows indicate the order of exposure. The number of chips 6 is actually much larger.

FIG. 2 is a schematic plan view of a photo reticle used in the method of manufacturing a semiconductor device according to the present invention.

Reference numeral 4 denotes a photo reticle (photo mask), 1 denotes a semiconductor element formation area (with a grid pattern, hereinafter referred to as a semiconductor element area), and 2 denotes a chip address display area indicating a position of the semiconductor element area 1 in a wafer. Numeral 3 denotes a chip address display pattern formed of the same number of circular patterns of the same size provided in the chip address display area. Note that the chip address display area 2 is shown larger than the semiconductor element area 1, but in practice, it needs only to be recognized by a scanning electron microscope (SEM).
It is formed to several tens μm, for example, 20 μm × 20 μm.

FIG. 1 is a schematic plan view of a principal part of a wafer for explaining the principle of a step-and-repeat method in a method of manufacturing a semiconductor device according to the present invention.

In the wafer process, as shown in FIG. 3, a single 5: 1 reduction projection exposure apparatus (that is, a single projection device) shown in FIG.
Step and repeat (exposure) are repeated using a stepper to form a predetermined pattern of each chip 6 on the wafer 5. Note that the chip address display pattern 3 is opened in the final passivation protection film in a photolithography step in which a hole is formed in the final passivation protection film made of a silicon nitride film or the like to make conduction with a bonding pad under the film. Provided.

As shown in FIG. 1, the exposure range of the chip address display area 2 is increased (or shifted) by 4 for each chip at each step and repeat of moving the exposure range, so that the end of the semiconductor element area 1 is shifted. The number of circular chip address display patterns 3 provided in the section is reduced.
That is, in the X direction, as shown at the bottom of FIG.
The repeat dimensions (indexes) R _{X1 to} R _X3 are made smaller than the shot (or chip) dimensions S _{X1 to} S _X3 to increase the exposure range so that a part is double-exposed, and the chips are arranged in the same number of rows and columns. The vertical columns of the address display pattern 3 are sequentially deleted from the leftmost column. Similarly, in the Y direction, as shown in the leftmost column of FIG. 1, as the step proceeds upward, the step-and-repeat dimensions R _{Y1 to} R _Y3 are made smaller than the shot dimensions S _{Y1 to} S _Y3 . The exposure range is increased so that a part is double-exposed, and the horizontal rows of the chip address display pattern 3 are sequentially erased from the bottom row.

The X of the chip address display pattern 3
The number in the direction is the number of chips 6 in one row in the X direction, and the number in the Y direction is the number of chips 6 in one column in the Y direction.

Therefore, in the present embodiment, chip addresses can be recognized based on the number of chip address display patterns 3 even in a product that requires a 5: 1 stepper for all layers with miniaturization. As the miniaturization progresses, the manufacturing process becomes difficult, and the rate of occurrence of post-dicing post-processes and post-commercial failure increases. At this time, it is very important to know the chip address in the wafer in the analysis of the cause of the failure, and it is possible to reduce the time required to find the cause of the failure.

Embodiment 2 FIG. 4 is a schematic plan view of another photo reticle according to the present invention.

In the present embodiment, a plurality of, in this case, three in the semiconductor element region 1 (one shot) of the photo reticle 4
This shows a case where one chip address display area 2 is provided for one (actually, for example, 10 × 10 = 100, 300 shots) semiconductor element areas 1a, 1b, and 1c.

Third Embodiment FIG. 5 is a schematic plan view of still another photo reticle according to the present invention.

In each of the above-described embodiments, the case where the same number of circular patterns 3 of the same size are provided in each of the chip address display areas 2 has been described. In the present embodiment, however, one rectangular chip address display area is provided. Pattern 3 was provided. Then, the area of the rectangular chip address display pattern 3 is reduced for each step and repeat, and the chip address is recognized based on the size of the area of the chip address display pattern 3.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various changes can be made without departing from the gist of the present invention. It is. For example, it is possible to use various things such as the installation location of the chip address display area 2 and the shape of the chip address display pattern 3. Further, in the above embodiment, as shown in FIG. 1, the exposure range is increased and the number of chip address display patterns 3 is decreased for each step and repeat, but the exposure range is reduced. It is apparent that the number of chip address display patterns 3 may be increased. Further, the present invention is most effective when applied to a submicron LSI such as a 16-M DRAM in which miniaturization is advanced, but is applicable to all semiconductor devices.

[0026]

As described above, according to the present invention,
Even if the reduced exposure is applied to the entire photolithography process, the chip address can be displayed on the finished device, which is effective in determining the cause of the occurrence of a defect in the semiconductor element.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a principal part of a wafer for explaining the principle of a step and repeat method in a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic plan view of a photo reticle used in the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is an overall schematic plan view of a wafer to which the semiconductor device manufacturing method of the present invention is applied.

FIG. 4 is a schematic plan view of another photo reticule according to the present invention.

FIG. 5 is a schematic plan view of still another photo reticle according to the present invention.

[Explanation of symbols]

1, 1a, 1b, 1c: semiconductor element region, 2: chip address display region, 3: chip address display pattern, 4
… Photo reticles, 5… wafers, 6… chips.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are formed on a wafer, wherein a chip address display pattern indicating a position in the wafer is provided in the vicinity of one or more semiconductor element regions; A method of manufacturing a semiconductor device, comprising: changing the number or shape of the chip address display patterns according to the movement of the exposure region in the semiconductor device region. 2. The method according to claim 1, wherein the same number of the plurality of chip address display patterns are provided for each of the semiconductor element regions, and each time the exposure region is moved, the exposure range is changed to change the number. A method for manufacturing a semiconductor device according to claim 1.