JPH0676594A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve a relief rate by means of a redundant circuit by arranging a redundant memory cell on the mid section of a memory cell array when a redundant memory is provided on a dynamic RAM. CONSTITUTION:A dynamic RAM is composed of a memory cell array 1, a row decoder 2, a column decoder 3 and a sense amplifier 4 and the array 1 is provided with redundant memory cells 12, 13 composed of one row and one column i.e., spare memory cells. In such a constitution, concerning the arranging position of the cells 12, 13, by avoiding the outermost periphery on which the periodicity is easily broken, these cells are arranged crosswise on the middle of the array 1 having the stable periodicity of a pattern. Consequently, the probability of the occurrence of defective parts in a redundant row 12 and a redundant column 13 is reduced and a repair enabling rate i.e., the relief rate is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
And a redundant memory cell of a semiconductor memory device.

[0002]

2. Description of the Related Art Recently, semiconductor MOS memories such as dynamic RAMs have been remarkably highly integrated and have a large capacity, and redundant circuit technology is an essential technology for the high integration. It is becoming rare for all memory cells for several tens of megabits to operate normally without any defects. Therefore, in addition to the regular memory cell group, a spare memory cell group is provided in advance. When a defect occurs in the memory, the redundant circuit technology replaces the defective memory cell with a spare memory cell to repair the defective cell.

FIG. 2 shows the structure of a conventional semiconductor memory device.
Will be described with reference to. FIG. 2 is a diagram showing the periphery of a memory cell array of a conventional dynamic RAM.

In FIG. 2, a conventional dynamic RAM
Is composed of a memory cell array 1, a row decoder 2, a column decoder 3, and a sense amplifier 4. Further, the memory cell array 1 is provided with the redundancy circuits 10 and 11 of 1 row and 1 column, that is, spare memory cells.

When the regular memory cell array 1 has a defect, it is replaced with the spare memory cells 10 and 11. Conventionally, the spare memory cells 10 and 11 are located at the outermost periphery of the array. There is a problem that the spare memory cell itself may be defective, and the defect cannot be eliminated even by replacement.

In this case, re-replacement is extremely difficult, and the phenomenon that the periodicity is lost at the outermost periphery of the cell array and defects are more likely to occur is becoming more prominent as the cells become three-dimensional.

[0007]

In the conventional semiconductor memory device as described above, since it is arranged at the outermost periphery of the memory cell array, the periodicity of the array at the outermost periphery is likely to collapse, so that it tends to be defective. Therefore, there is a problem that the defect cannot be eliminated even if the memory cell is replaced.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor memory device capable of improving the repair enable (relief) rate by a redundant circuit.

[0009]

A semiconductor memory device according to a first aspect of the present invention has a redundant memory cell arranged in a central portion of a memory cell array.

In the semiconductor memory device according to the second aspect of the present invention, the redundant memory cells are arranged in other than the outermost periphery where the probability of a defective memory cell array is the lowest.

[0011]

In the present invention, since the redundant memory cell is arranged in the central portion of the memory cell array, the repair enable (relief) rate can be improved.

Further, according to the present invention, since the redundant memory cells are arranged in the areas other than the outermost circumference where the probability of a defective memory cell array is the lowest, the repair enable (relief) rate can be improved.

[0013]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to FIG. First Embodiment FIG. 1 is a diagram showing a first embodiment of the present invention. In FIG. 1, the first embodiment has a memory cell array 1, a row decoder 2, a column decoder 3, and a sense amplifier 4.
It is composed of. In the memory cell array 1, 1
Redundant memory cells 12 and 13 in a row and a column, that is, spare memory cells are provided.

Embodiment 1 of the present invention as compared with FIG. 2 of a conventional example.
However, the locations of the redundant memory cells 12 and 13 are different. That is, it is arranged in the center of the memory cell array 1 having a stable pattern periodicity, avoiding the outermost periphery where the periodicity of the cell array is likely to collapse. By doing so, the probability of failure occurring in the redundant memory cells 12 and 13 is reduced, and the repair enable (repair) rate is improved.

The first embodiment of the present invention, as described above,
The purpose is to improve the repair enable (relief) rate of a semiconductor memory device. Therefore, the spare memory cell groups 12 and 13 (redundant rows, redundant columns) for replacement of the semiconductor memory device are arranged in the central portion of the memory cell array 1 to perform the layout configuration and the circuit configuration.

Example 2. In the first embodiment described above, the case where the redundant memory cells 12 and 13 are arranged in the central portion of the memory cell array 1 has been described. Of course, in consideration of the device-specific design margin, process margin, etc.,
It is a good idea to investigate a location other than the outermost periphery of the memory cell array, which has the lowest probability of failure, and arrange it there.

[0017]

As described above, according to the present invention, the spare memory cell group for replacement (redundant row, redundant column) is arranged in the central portion of the memory cell array or other than the outermost periphery, so that the repair enable rate can be improved. The effect is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a dynamic RA that is a conventional semiconductor memory device.
It is a figure which shows the memory cell array periphery of M.

[Description of Reference Signs] 1 memory cell array 2 row decoder 3 column decoder 4 sense amplifier 12 redundant memory cell (row) 13 redundant memory cell (column)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/108 8728-4M H01L 27/10 325 R

Claims (2)

[Claims] 1. A semiconductor memory device in which a redundant memory cell is arranged in a central portion of a memory cell array. 2. A semiconductor memory device characterized in that redundant memory cells are arranged in a region other than the outermost periphery where the probability of a defective memory cell array is the lowest.