JPH07335844A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve performance and yield by suppressing deviation of characteristics and dimensions due to a layout of a circuit pattern. CONSTITUTION:In a semiconductor device so constructed that a wiring channel region 2 is set up as if to enclose an internal cell region 1 of the central part, its periphery further surrounded by an I/O cell region 3 where circuits are arranged for input and output, etc., of signals to the outside, a wiring channel region is formed of a dummy MOS transistor 20 which is approximately equal, in dimensions and arrangement density, to a multiplicity of MOS transistors 10 provided inside the internal cell region 1. An environment of arrangement density, etc., of MOS transistors in the periphery of the internal cell region 1 is made to equal a group of MOS transistors 10 in the central part to prevent the dimensions of a diffusion layer pattern 10a and a gate pattern 10b in manufacture from deviating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a repetitive structure of fine circuit patterns.

[0002]

2. Description of the Related Art For example, the aspect ratio of a circuit pattern or a photoresist pattern (pattern width or aperture size and The ratio of height and depth) tends to increase.

As the aspect ratio increases,
Generally, the etching rate of the pattern area is slower than that of a flat area without a pattern, and as a result, the circuit characteristics vary even within the same chip. For example, in the case of a MOS transistor, the operating characteristics vary due to the ununiformity of the width dimension of the gate insulating film and the gate electrode in the channel direction.

[0004]

In the past, when the size of the circuit pattern was relatively large and the allowable range of variation in the pattern size was relatively large, the above-mentioned variation did not become a problem, but recently. The present inventor has found that there is a concern that the performance and yield of the semiconductor device may be significantly affected by the drastic miniaturization of the circuit pattern.

For example, as illustrated in FIGS. 3A and 3B, a peripheral portion of an internal cell region 100 densely formed by repeating the same circuit pattern in a conventional logic element such as a gate array. Consider a case where the I / O cell region 300 is provided with the wiring channel region 200 having no circuit element interposed therebetween. In this case, in the internal cell region 100, the densities of the MOS transistor 101 and the MOS transistor 102 formed of the diffusion layer pattern 101a serving as the source and the drain and the gate pattern 101b are different between the edge close to the wiring channel region 200 and the inside. As illustrated in FIG. 4, the MOS transistor 10 on the edge side
The gate pattern 101b of No. 1 is the gate pattern 101
The width of the MOS transistor 102 on the inner side as in c
Is larger than the gate pattern 101b according to the design value of, and the characteristics of the MOS transistors 101 and 102 vary, and a part of the MOS transistor 101 in the region is
As a result of deviating from the standard, there is a concern that the entire device will be judged as a defective product.

In order to control the manufacturing process, a test pattern similar to the circuit pattern is formed on a part of the circuit element, and the test pattern is measured to determine whether or not the circuit pattern has a desired size. Although inspections such as indirect evaluation are performed, the isolated test pattern does not reflect the process state inside the actual circuit pattern in which a large number of circuit elements are densely formed, resulting in low evaluation accuracy. There is.

Regarding the conventional arrangement of circuit patterns in a gate array or the like, for example, Press Journal Co., Ltd., issued January 20, 1992, "Monthly Semiconductor World" 1992.2, P88-P10.
4, etc.

An object of the present invention is to provide a semiconductor device capable of suppressing variations in characteristics and dimensions due to the layout of circuit patterns and improving performance and yield.

Another object of the present invention is to provide a semiconductor device capable of evaluating a manufacturing process or the like with high accuracy.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, in the semiconductor device of the present invention, a dummy circuit pattern having the same or similar shape and density as the circuit pattern, which does not contribute to the actual circuit operation, is formed in the peripheral portion of the element forming region where the circuit patterns are dense. To do.

Further, in the semiconductor device of the present invention, a test pattern region having a structure in which a dummy test pattern having the same or similar shape as the test pattern is arranged in the peripheral portion of the specific test pattern is provided.

[0014]

According to the above means, the circuit pattern located at the peripheral portion in the element forming region is surrounded by the dummy circuit pattern arranged around the element forming region. There is no difference in the arrangement density of the included circuit patterns between the inside of the element formation region and the peripheral portion. In other words, variations in dimensions and characteristics formed by photolithography such as etching due to the arrangement density of circuit patterns are eliminated, and all circuit patterns inside the element formation region can be formed with the same characteristics and dimensions.

Further, by keeping the dummy circuit pattern to the extent of a gate pattern of a MOS structure, the upper portion of the dummy circuit pattern can be freely used for routing a normal wiring pattern, etc., and there is a concern that space will increase. Nor.

On the other hand, by arranging the dummy test pattern around the test pattern, the measurement result of the test pattern accurately reflects the actual state in the circuit pattern, and the evaluation of the formation process using the test pattern The accuracy of is surely improved.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1A is a conceptual diagram showing an example of the configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 1B is a conceptual diagram showing a part of it in an enlarged manner. In this embodiment, a case where the semiconductor device is applied to a gate array will be described.

In the semiconductor device of this embodiment, a wiring channel region 2 is provided so as to surround the internal cell region 1 in the central portion,
Further, the periphery thereof is surrounded by an I / O cell region 3 in which a circuit for inputting / outputting signals to / from the outside is arranged.

Inside the inner cell region 1, a diffusion layer pattern 10a having a fine size and the diffusion layer pattern 10a are formed.
A large number of MOS transistors 10 each including a gate pattern 10b formed so as to cross over the channel direction.
Are arranged in orderly density. Then, a logic circuit having a desired logic function is constructed by appropriately connecting these many MOS transistors 10 with wirings not shown.

On the other hand, in the I / O cell region 3, for example, a large number of MOSs each including a diffusion layer pattern 30a having a relatively large size and a gate pattern 30b formed on the diffusion layer pattern 30a so as to cross the channel direction.
A transistor 30 is provided and is connected to a group of MOS transistors 10 in the internal cell region 1 via a wiring pattern (not shown) provided in the wiring channel region 2, and a logic circuit constructed by the MOS transistor 10 is provided. Input and output of information between the outside and the outside.

In this case, the dummy MOS transistor 2 is formed in the wiring channel region 2 at the same time as the formation of the MOS transistor group 10 in the internal cell region 1 and has substantially the same size and arrangement density as the MOS transistor 10.
0 is placed. This dummy MOS transistor 2
For example, 0 only forms the diffusion layer pattern 20a and the gate pattern 20b, and does not form the wiring pattern or the like. That is, the MO inside the internal cell region 1
The S-transistor 10 does not contribute to the actual logic operation or the like.

Then, the dummy MOS transistor 2
The upper region of 0 is used for routing the wiring pattern (not shown) for connecting the MOS transistor 10 and the MOS transistor 30, which is the original function of the wiring channel region 2.

Here, paying attention to the MOS transistor 11 located at the peripheral portion of the internal cell region 1, the presence of the dummy MOS transistor 20 formed in the wiring channel region 2 causes the MOS transistor 11 to move to the internal cell region 1. Similar to the MOS transistor 10 on the inner side, the surroundings are surrounded by another MOS transistor 10 and a dummy MOS transistor 20 having a shape equivalent to the MOS transistor 10.

Therefore, the environment such as the arrangement density of the MOS transistors 11 located at the peripheral portion of the internal cell region 1 is completely equivalent to that of the internal MOS transistor 10, and the MO
When the diffusion layer pattern 10a, the gate pattern 10b, and the like of the S transistor 10 and the MOS transistor 11 are formed by etching or the like, it is possible to form them uniformly without variation.

That is, the internal MOS transistor 10
And the operating characteristics of the MOS transistor 11 at the peripheral portion become uniform as designed, and M in the internal cell region 1
Defects caused by variations in the characteristics of the OS transistor group 10 can be eliminated, and the yield can be improved.

In the above example, the case where the present invention is applied to a gate array as an example of a semiconductor device has been described. For example, the internal cell region 1 is used as a memory cell formation region and the I / O cell region 3 is used as a sense amplifier or address. Obviously, the same effect can be obtained in a semiconductor memory device or the like by replacing it with a memory peripheral circuit area such as a decoder.

Further, the circuit pattern is not limited to the MOS transistor structure exemplified in the above description, but can be similarly applied to a pattern requiring accuracy such as a bipolar transistor, a resistance pattern, a capacitance pattern.

(Embodiment 2) FIG. 2A is a plan view showing a part of a semiconductor device according to another embodiment of the present invention, and FIG. 2B is a line A--A in FIG. It is sectional drawing of the part shown by.

The semiconductor device of this embodiment is provided with a test pattern region 50 for evaluating the manufacturing process of the semiconductor device, which is composed of, for example, a through hole pattern. The test pattern region 50 is used to inspect the dimension and shape of the through-hole pattern formed in the multilayer thin film 52 laminated on the base film 51, for example.

The test pattern region 50 is arranged in the central portion, and the test pattern 50A is formed in the multilayer thin film 52.
And a dummy test pattern 50B which is disposed so as to surround the periphery of the test pattern 50A and is formed in the multilayer thin film 52 to have substantially the same size and shape as the test pattern 50A.

The test pattern 50A and the dummy test pattern 50B are arranged so that the arrangement density is the same as the through hole pattern (not shown) formed in the multilayer thin film 52 in the actual circuit pattern (not shown).

As a result, the shape of the test pattern 50A located in the central portion of the test pattern region 50 of this embodiment has a through hole in the actual circuit pattern as compared with the case where only the test pattern 50A is provided separately. The pattern forming environment and shape are reflected more accurately, and the evaluation accuracy of the dimensions of the through-hole pattern is improved. Then, by feeding back such an evaluation result to the manufacturing process of the semiconductor device, the yield of the semiconductor device can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the semiconductor device is not limited to the gate array and the memory element, but can be widely applied to those having a structure in which fine circuit patterns are densely formed in a specific region and repeatedly formed.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the semiconductor device of the present invention,
This has the effect of suppressing variations in characteristics and dimensions due to the layout of circuit patterns and improving performance and yield. Further, there is an effect that the manufacturing process can be evaluated with high accuracy.

[Brief description of drawings]

FIG. 1A is a conceptual diagram showing an example of the configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is an enlarged conceptual diagram showing a part thereof.

FIG. 2A is a plan view showing a part of a semiconductor device according to another embodiment of the present invention, and FIG. 2B is a sectional view taken along line AA in FIG. is there.

3A and 3B are a conceptual diagram showing an example of the configuration of a conventional gate array and an enlarged conceptual diagram of a part thereof, respectively.

FIG. 4 is a conceptual diagram illustrating an example of technical problems of the conventional gate array of FIG.

[Explanation of symbols]

1 Internal Cell Area 2 Wiring Channel Area 3 I / O Cell Area 10 MOS Transistor (Circuit Pattern) 11 MOS Transistor (Circuit Pattern) 10a Diffusion Layer Pattern 10b Gate Pattern 20 Dummy MOS Transistor (Dummy Circuit Pattern) 20a Diffusion Layer Pattern 20b Gate Pattern 30 MOS transistor 30a Diffusion layer pattern 30b Gate pattern 50 Test pattern region 50A Test pattern 50B Dummy test pattern 51 Base film 52 Multilayer thin film 100 Internal cell region 101 MOS transistor 101a Diffusion layer pattern 101b Gate pattern 101c Gate pattern 102 MOS transistor 200 Wiring Channel area 300 I / O cell area

Front page continuation (72) Inventor Ken Ono 5-22-1 Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (7)

[Claims] 1. A dummy circuit pattern, which has the same or similar shape as an actual circuit pattern formed inside the element formation region and does not contribute to a circuit operation, is formed in the peripheral portion of the element formation region. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the circuit pattern is a diffusion layer pattern and a gate pattern of a MOS structure. 3. The element formation region is a logic cell formation region surrounded by an input / output cell region via a wiring channel region in the gate array, and the wiring channel located in the peripheral portion of the logic cell formation region. 2. The semiconductor device according to claim 1, wherein dummy logic cells that do not function as the logic cells are arranged in the region with the same shape and arrangement density as the logic cells formed inside the logic cell formation region. 4. The element formation region is, in a semiconductor memory, a memory cell formation region surrounded by a memory peripheral circuit region via a wiring routing region, and the wiring located in the peripheral portion of the memory cell formation region. 2. The semiconductor device according to claim 1, wherein dummy memory cells that do not function as the memory cells are arranged in the routing area with the same shape and arrangement density as the memory cells formed inside the memory cell formation area. . 5. A semiconductor device having a test pattern for evaluating a semiconductor element forming process, wherein a plurality of dummy test patterns having the same or similar shape as the test pattern are provided around the test pattern. A semiconductor device characterized by being arranged. 6. The semiconductor device according to claim 5, wherein the test pattern is a dimension inspection pattern of a through hole or a via hole formed in a thin film forming the semiconductor element. 7. The semiconductor device according to claim 6, wherein the arrangement density of the test pattern and the dummy test pattern is made to match the arrangement density of the through holes or via holes formed in the thin film.