JPH07307446A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a short word line pitch. CONSTITUTION:In a semiconductor device that is provided with a memory cell array having a plurality of work lines, it is provided with an auxiliary word line 14' that is installed on a main word line with comparatively high resistance, has comparatively low resistance, is shorter than the line 14 and whose at least connection parts of the both ends are electrically connected with the main word line, and at the same time it is formed in a manner that the connecting parts of the auxiliary word lines will not be in contact with each other among the adjacent lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a memory cell array in a random access memory (DRAM).

[0002]

2. Description of the Related Art Semiconductor devices (hereinafter, DRAM is taken as an example)
Is "I Triple E Journal of Solid State Circuit" (IEEE JOUNLAL
OFSOLID-STATE CIRCUITS) VOL. SC-20, NO. 5, OCTOBER198
It has the structure as described on page 903 and after. This is shown in FIG. 1. A brief explanation will be given with reference to.

A DRAM is composed of a large number of memory cells arranged in a matrix, a plurality of rows of bit lines (BIT LINE) for taking out data from the memory cells, and a plurality of columns of word lines which intersect the bit lines at right angles and select memory cells. (WOR
D LINE).

In such a DRAM, the word line is
When selected and set to a high potential, it functions to read information from the associated memory cell to the bit line. Also, in the case of writing information, the operation of selecting a memory cell is similarly performed.

In such a DRAM, the read / write operation speed is one of the important factors that determine the performance, and therefore it is necessary to reduce the resistance of the bit line and the word line. Therefore, in the above literature, the polycide layer is used for the bit line, and the word line is formed along the layer formed of the polysilicon layer (hereinafter, this word line is referred to as the main word line) and formed of the aluminum layer (hereinafter, this word line). Is referred to as an auxiliary word line) and is connected.

[0006]

However, such a word line has the following problems. This will be described with reference to FIGS. 2 and 3.

FIG. 2 is a plan view showing an example of the entire DRAM. In the figure, 21 is a row decoder, 22 is a column decoder and sense amplifier, 23 is a block of a memory cell array, 24 is one of word lines, and 25 is one of bit lines. In this example, The memory cell array block 23 is composed of four blocks. Also, FIG. 3 is a diagram in which only the word lines are taken out,
(A) is a top view and (b) is the AA sectional view. In the figure, 34 'indicates an auxiliary word line (broken line), and 36 is a contact for connecting the main word line 34 and the auxiliary word line 34'.

As can be seen from FIG. 3, the word line is difficult to miniaturize due to problems in the manufacturing process, and the width of the auxiliary word line made of aluminum is larger than that of the main word line made of the polysilicon layer. The distance between them must be increased. Otherwise, a short circuit of aluminum of the auxiliary word line 34 'will occur. For example, when the width and interval of the main word lines 34 can be 0.8 μm each, the auxiliary word lines 3
4'must be 1 μm wide and 1.5 μm apart. That is, when the pitch of the main word lines 34 can be set to 1.6 μm, the pitch of the auxiliary word lines 34 ′ must be set to 2.5 μm. Since it is necessary to use the main word line 34 and the auxiliary word line 34 'as a set, the degree of integration of the semiconductor device is regulated by the auxiliary word line 34', which hinders high integration.

In order to prevent this, it can be considered that the main word line 34 is formed of a polycide layer having a resistance one digit lower than that of the polysilicon layer so that the auxiliary word line 34 'is not used. However, since the resistivity of polycide is still several Ω / □, the usable word line length is limited. Due to this length limitation, it is necessary to double the number of memory cell array blocks when the length of the word line is halved. This corresponds to setting the number of memory cell array blocks to eight in FIG. As described above, when the memory cell array block is increased, an extra decoder is required, which causes a problem that the chip becomes large.

[0010]

According to the present invention, a semiconductor device having a memory cell array having a plurality of columns of word lines has a relatively low resistance and a shorter resistance than a main word line having a relatively high resistance. A main word line and at least an auxiliary word line electrically connected at the connection parts at both ends thereof,
The adjacent columns are formed so that the connection portions of the auxiliary word lines do not adjoin each other.

[0011]

According to the present invention, since the auxiliary word line has a relatively low resistance and is electrically connected to the main wiring at the connecting portions located at least at both ends thereof, the resistance of the word line can be reduced, and The two auxiliary word lines of the auxiliary word lines are arranged so that the connecting portions located at both ends thereof are not adjacent to each other, so that the pitch of the word lines can be reduced. You can do it.

[0012]

1 (a) and 1 (b) are a plan view of a word line and an AA sectional view thereof for explaining an embodiment of the present invention.

The sectional shape will be described with reference to FIG.
The aforementioned document FIG. 1. Similarly to the above, on the semiconductor substrate 11,
A field oxide layer 1 and a gate oxide layer 2 are formed. An electrode gate layer 3 of the capacitor, which is formed of the polysilicon layer 3, is formed on this part. Needless to say, the semiconductor substrate 11 has an impurity region serving as another electrode of the capacitor and an impurity region for forming a transistor.

On these layers, a main word line 14 made of a polycide layer is formed via an insulating layer 4. Insulating layers 5 and 6 composed of a glass layer or the like are provided on the word line 14, and a material having a resistance lower than that of the main word line 14 is provided on every other column of the main word line 14 such as aluminum. Auxiliary word line 1 composed of metal layers such as
4'is formed. The main word line 14 and the auxiliary word line 14 'are connected to each other through through holes provided in the insulating layers 5 and 6. Therefore, the cross section of the bit line formed between the insulating layers 5 and 6 is not shown in the AA cross section. That is, the bit line is formed while avoiding the place where the through hole is located.

The plane shape will be described with reference to (a).
Main word line 14 (solid line) composed of polycide layer
Are arranged in parallel in a plurality of columns at almost the minimum pitch that can be formed by the polycide layer. Along this, along this main word line 1
An auxiliary word line 14 '(broken line) shorter than 4 is configured to short-circuit the main word line 14 and is formed so as not to be adjacent to the auxiliary word line 14' in the adjacent column. Since the auxiliary word lines 14 'are configured so as not to be adjacent to each other in this manner, even if the auxiliary word lines 14' become thick or stick out due to difficulty in miniaturization, the auxiliary word lines 14 'are short-circuited. Is gone.

Considering the auxiliary word line 14 'in units of columns,
It may be formed so as to occupy about half the area of the word line area, and may be formed by being divided into a plurality of areas such that the area where the auxiliary word line is formed and the area where the auxiliary word line is not formed alternate with each other by substantially the same length. . The shape for that is a checkerboard pattern when viewed from the memory cell array.

The larger the number of divisions of this auxiliary word line per word line, the more uniform the selection time of the main word line memory cells, but it is considered that about 8 divisions are sufficient because the uniformity is limited to some extent. The auxiliary word line 14 'is electrically connected to the main word line through contact holes formed at both ends of the auxiliary word line 14'.

By thus forming the auxiliary word line 14 'with the metal layer, the resistance of the word line is reduced to about half. Therefore, even if the main word line is formed with the polycide layer, the number of memory cell array blocks is not increased. Is also good.

[0019]

As described above, according to the present invention, since the connecting portions with the main wirings at both ends of the auxiliary word line are formed so as not to be adjacent to each other, the auxiliary word lines are not short-circuited. As a result, the reliability of the semiconductor device can be improved and the degree of integration can be improved in spite of the difficulty of miniaturizing the auxiliary word line.

Although the semiconductor device has been described by taking the DRAM as an example, the present invention is not limited to this, and the SRAM, the ROM, the EPRO are not limited thereto.
The present invention can be applied to all ICs having word lines such as memory ICs such as M and EEPROM and microcomputers including these memories.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line AA.

FIG. 2 is a diagram illustrating an entire DRAM.

3A and 3B are diagrams illustrating a conventional semiconductor device, FIG. 3A is a plan view, and FIG. 3B is a sectional view taken along line AA.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Field oxide film 2 ... Gate oxide film 3 ... Electrode gate layer 4, 5, 6 ... Insulating layer 14 ... Main word line 14 '... Auxiliary word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/768 H01L 21/90 B

Claims (2)

[Claims] 1. A first and a second main wiring extending substantially in parallel and separated from each other, and a first auxiliary wiring having a relatively low resistance and extending along the main wiring and shorter than the main wiring. A second auxiliary wiring having a relatively low resistance, which is shorter than the main wiring and extends along the main wiring, wherein the first auxiliary wiring is at least at both ends of the first auxiliary wiring.
And a second connecting portion electrically connected to the first main wiring, and the second auxiliary wiring is at least at both ends thereof.
Connection part and a fourth connection part, which are electrically connected to the second main wiring, and are located at both ends of the first auxiliary wiring, and the second connection portion and the second connection portion. A semiconductor device characterized in that the third and fourth connecting portions located at both ends of the auxiliary wiring are arranged without any connecting portions being adjacent to each other. 2. The semiconductor device according to claim 1, wherein the first and second auxiliary wirings are thicker than the first and second main wirings.