KR100203870B1 - Process for interconnecting word lines in semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a word line wiring method of a semiconductor memory device.

2. The technical problem to be solved by the invention:

According to the present invention, a word line of a semiconductor memory device, which is formed in a different layer between one word line and an adjacent word line, alternately contacts with neighboring word lines, thereby smoothly supplying voltage, thereby improving chip speed. Provides a wiring method.

3. Summary of the solution of the invention:

The present invention relates to a semiconductor memory device in which a plurality of memory array array blocks and a plurality of word lines are interconnected in a row direction of the array of arrays, and a strapping layer is formed in the same direction as the plurality of word lines. In a word line wiring method, the word line and a word line adjacent thereto are contacted and wired by a plurality of strapping layers formed of different conductive layers.

4. Important uses of the invention:

The present invention is suitably used for a semiconductor memory device.

Description

Word line wiring method of semiconductor memory device

1 is a layout diagram showing wiring of word lines according to the prior art.

2 is an overall block diagram of the invention.

3 is a layout diagram showing word line wiring according to an embodiment of the present invention.

4 is a partial detail of the layout of FIG.

5 is a layout diagram showing wirings of a word line according to another embodiment of the present invention.

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a word line wiring method of a semiconductor memory device.

In general, a semiconductor memory device includes a plurality of bit lines and word lines arranged in a column direction and a row direction, respectively, and a memory connected to the bit lines and word lines. It is composed of a memory cell array with rows. However, as the semiconductor memory device is increasingly integrated in recent years, the gap between the word lines and the bit lines is narrowed. In particular, when the distance between the bit lines is narrowed, the gap between the sense amplifiers connected to the bit lines is also reduced. The layout of the word lines, bit lines, and sense amplifiers in a layout is difficult. In addition, as the design rule of the memory chip is reduced to sub-micron, the design rule of the gate poly, which functions as a word line of an access transistor, is also reduced. For example, it has become quite difficult or impossible to wire a first metal M1 made of aluminum (Al) or tungsten (W) to correspond one-to-one with the gate poly. In addition, even if the layout is possible, a metal contact connecting to the first metal M1 corresponding to the gate poly in the memory pin array strap region is necessary. Since the strap region becomes the region with the least design rule in the memory chip, yield decreases or shrinks the chip narrowly due to a process failure in the memory array array region when the chip is manufactured. ) Causes bottlenecks.

1 is a layout showing the wiring of the word line according to the prior art. Referring to FIG. 1, column selection lines 33 and 34 that are wired in a bit line direction, that is, in a column direction, in a memory array array region may include a second conductive layer, for example, a second conductive layer. External power supply voltage lines (Vcc Line) (hereinafter referred to as Vcc) 30 and 32 formed of metal (Al or W) M2 and wired in a bit line direction in the memory array array strap region; (Hereinafter referred to as Vss) 31 is also formed of the second metal M2. The word lines 35 and 36 connected to a row decoder (not shown) are gate poly, i.e., polysilicon, which are gates of an access transistor in a direction crossing the bit lines in a memory array array region. (Poly Silicon), the gate poly is a material having a large sheet resistance (Load Resistance) is increased. Therefore, since the slope of the voltage level of the word line for accessing the data of the access transistor far from the row decoder is laid down, the sensing speed becomes slow, resulting in a slow memory chip or a malfunction of the chip. Therefore, in order to minimize the loading of the word lines 35 and 36, the first metal M1 is wired in a one-to-one correspondence with the gate poly in the same direction as the word line of the gate poly, and the gate poly and It is essential to reduce the loading of the word lines 35 and 36 by connecting the first metal M1 to the metal contacts 18, 20 and 22.

Accordingly, it is an object of the present invention to provide a word line wiring method of a semiconductor memory device which improves the speed of chips by alternately wiring adjacent word lines to facilitate voltage supply.

Another object of the present invention is to correspond to one metal line per two word line gate polys, so that the semiconductor pitch can double the metal pitch in the memory array array region and the memory array array strap region. To provide a word line wiring method of.

According to the technical concept of the present invention for achieving the above object, a plurality of memory pin error is a block, a plurality of word lines are wired in the row direction of the memory array array block, the plurality of word lines and In the word line wiring method of a semiconductor memory device to form a clamping layer in the same direction, characterized in that the word line and the word line adjacent to it by wiring using a plurality of strapping layers.

Hereinafter, the detailed description of the preferred embodiments of the present invention will be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the drawings represent like reference numerals wherever possible.

2 is an overall block diagram of the present invention. Referring to FIG. 2, the column select lines CSL 33 and 34 wired in the bit line direction in the memory array array regions 10 and 11 are wired to the third metal (Al or W) M3, and the memory array array straps are connected to each other. Vcc (30,32) and Vss (31), which are wired in the bit line direction in the areas (7, 8, 9), are also wired by the third metal M3. The CSLs 33 and 34 are connected to the column decoder 2 and are alternated with adjacent sense amplifiers of the folded bit line sense amplifiers in the form of folded bit line sense amplifiers. Via contacts are generally connected to the contacts 40, 41, 42, and 43 for contacting the metal with the metal.

The word lines 35, 36, 37, and 38, which are started at the row decoder 1, are gate polys that become gates of the access transistor 39 in the direction intersecting the bit lines in the memory array array regions 10 and 11, respectively. Since the gate poly is a material having a large sheet resistance, the word line loading is increased, and the word line voltage level for accessing data of an access transistor far from the row decoder 1 is laid down so that the speed of the memory chip becomes slow. It will cause chip malfunction. Therefore, in the present invention, in order to minimize the loading of the word lines 35, 36, 37, 38, the second metal M2 is placed in the same direction as the odd word lines 35, 37 of the gate poly. The first metal M1 in the same direction as the word lines 36 and 38, and wired in the upper layer in a one-to-one correspondence with the even-numbered (where the odd-numbered and even-numbered numbers may be interchanged with each other. One-to-one correspondence with the even-numbered gate poly is formed and wired. Thus, the entire word lines 35, 36, 37, 38 are in the memory pin array strap regions 7, 8, 9, and the odd word lines 35, 37 are in the gate poly and the second metal M2 is the via contact 12; 13, 14, 15, 16, and 17 to reduce the load of the odd word lines 35 and 37, and the even word lines 36 and 38 are formed by the gate poly and the first metal M1 being connected to the metal contact 18. 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, and 29 have an effect of reducing the even-numbered word line (36, 38) loading. In addition, by alternately wiring the second metal M2 of the odd-numbered word lines 35 and 37 and the first metal M1 of the even-numbered word lines 36 and 38, one metal line is formed per two gate poly lines of the access transistor. As a result of the correspondence, the metal pitch in the memory array array regions 10 and 11 and the memory array array strap regions 7, 8 and 9 can be improved by twice as much as in the prior art.

Meanwhile, via contacts 12, 13, 14, 15, and 16 which connect the second metal M2 of the odd-numbered word lines 35 and 37 to the gate poly of the access transistor in the memory array array strap regions 7, 8, and 9 are provided. , 17) is necessary. As described above, there is also a method of directly connecting the second metal M2 and the gate poly by a via contact. However, when it is difficult to directly connect the second metal M2 and the gate poly, a first metal pad is formed to form a second metal. There is also a method of connecting the line and the first metal pad to the via contact, and the first metal pad and the gate poly to the metal contact. In addition, the metal contacts 18, 19, 20, 21, which connect the first metal M1 of the even-numbered word lines 36, 38 and the gate poly GP of the access transistor in the memory array array strap regions 7, 8, and 9, 22,23,24,25,26,27,28,29). Therefore, in the memory chip of the prior art, the memory chip array strap area is the area having the least design rule. However, in the present invention, the word line strap line alternately uses the first metal M1 and the second metal M2. There is an effect that the word lines can be wired with the design rules twice that of the prior art (7,8,9).

3 is a layout diagram illustrating word line wiring according to an exemplary embodiment of the present invention. Referring to FIG. 3, the column select lines CSL 33 and 34 wired in the bit line direction in the memory array array area are wired to the third metal M3, and the Vcc (30 32) and Vss 31 are also wired to the third metal M3.

In addition, in order to minimize the loading of the word lines 35 and 36, the second metal M2 is wired in one-to-one correspondence in the same direction as the odd word lines 35 made of gate poly, and the even numbered gate poly is used. The first metal M1 is wired in a one-to-one correspondence with the word line 36 in the same direction. The odd word lines 35 are wired to the second metal M2 and the even word lines 36 are wired to the first metal M1 so that the entire word lines 35 and 36 are odd words in the memory array array strap region. Via contacts 12, 13, and 14 connecting the second metal M2 of line 35 and the gate poly of the access transistor are necessary. In addition, when it is difficult to directly connect the second metal M2 and the gate poly, first metal pads 1, 2, and 3 may be formed to connect the second metal line and the first metal pads 1, 2, and 3 to the via contact 12. 13, 14, and the first metal pads 1, 2, 3 and the gate poly may be connected to the metal contacts 4, 5, and 6 to reduce the load of the odd word lines 35. In addition, the even word line 36 connects the gate poly and the first metal to the metal contacts 18, 19, 20, 21, 22, and 23. The metal pads 1, 2, In order to guarantee the pitch of 3), the first metal M1 of the even word line in the memory array array region is cut and connected to the gate poly with metal contacts 18, 19, 20 and 19, 21, 23, respectively. In this manner, the loading of the even-numbered word line 36 is reduced.

In addition, the second metal M2 of the odd-numbered word line 35 and the first metal M1 of the even-numbered word line 36 are alternately wired so that one metal line per two gate poly lines of the access transistor is corresponded. This results in an effect of doubling the metal pitch in the memory array array region and the memory array array strap region over the prior art.

4 is a detailed view of FIG. Referring to FIG. 4, the CSLs 33 and 34 are wired to the third metal M3 in the bit line direction in the memory array array area, and the Vss 31 is also the third metal in the bit line direction in the memory array array area. Wire to M3. Therefore, in order to minimize the loading of the word lines 35 and 36, the second metal M2 is wired in one-to-one correspondence in the same direction as the odd word line 35 made of gate poly and the even word made of gate poly. The first metal M1 is wired in a one-to-one correspondence in the same direction as the line 36. Accordingly, a via contact 13 is required in which the entire word lines 35 and 36 connect the second metal M2 of the odd-numbered word line 35 to the gate poly of the access transistor in the memory V array strap region. In addition, when it is difficult to directly connect the second metal M2 and the gate poly, a first metal pad is formed to connect the second metal line 70 and the first metal pad 2 to the via contact 13 and the first metal pad. The metal pad 2 and the gate poly are connected to the metal contact 5 to reduce the load of the odd word line 35. In addition, the even word line 36 is connected to the gate poly and the first metal metal FH contacts 20 and 21. In order to ensure the pitch of the first metal pad 2 of the odd word line 35, the memory is secured. In the array strap region, the first metal line of the even word line 35 is cut and connected to the gate poly by metal contacts 20 and 21, respectively, to reduce the load of the even word line 36. . The second metal line 70 of the odd-numbered word line 35 and the first metal line of the even-numbered word line 36 alternately wire word lines alternately to form a memory array array region and a memory array array region. Has an effect of improving the metal pitch twice as compared to the prior art.

5 is one embodiment according to the present invention. Referring to FIG. 5, the CSLs 33 and 34 are routed to the third metal M3 in the bit line direction in the memory array array area and Vcc (30, 32) and Vss (in the bit line direction in the memory array array area. 31 is also wired to the third metal M3. In addition, the odd word lines 35 are wired to the second metal M2 and the even word lines 36 are wired to the first metal M1 to form strapping layers of all the word lines 35 and 36. Cyrillic can reduce the loading. In the memory array array region, via contacts 12, 13, and 14 are formed to connect the second metal M2 of the odd-numbered word line 35 and the gate poly of the access transistor to reduce the load of the odd-numbered word line 35. The first metal M1 of the even word line 36 and the gate poly are connected to the metal contacts 19, 21, and 23 to reduce the load of the even word line 36. In addition, as a result of alternately wiring the second metal line of the odd-numbered word line 35 and the first metal line of the even-numbered word line 36, each metal line is matched per two gate poly lines of the access transistor. Therefore, there is an effect of doubling the metal pitch in the memory array array region and the memory array array region.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Claims (8)

A word line of a semiconductor memory device in which a plurality of memory array array blocks and a plurality of word lines are interconnected in the row direction of the array array, and a strapping layer is formed in the same direction as the plurality of word lines. A wiring method according to claim 1, wherein the word line and the word line adjacent thereto are wired using a plurality of strapping layers. The word line interconnection method of claim 1, wherein the conductive layer is formed of aluminum or tungsten. A word of a semiconductor memory device in which a plurality of memory array array FJRs and a plurality of word lines are interconnected in the row direction of the array array, and a strapping layer is formed in the same direction as the plurality of word lines. In the line wiring method: A first step of wiring the first strapping layer to the first contact means through the first conductive layer in the same direction as any one of the word lines; And a second process of wiring a second strapping layer to a second contact means through a second conductive layer in the same direction as at least one of the word lines adjacent to the word line. Line wiring method. The method of claim 3, wherein the first and second strapping layers are alternately wired up and down by the word lines adjacent to each other. The word line wiring method of claim 3, wherein the first conductive layer and the second conductive layer are formed of aluminum. 4. The method of claim 3, wherein the first contact means is made of a metal contact. 4. The word line wiring method of claim 3, wherein the second contact means comprises a via contact. The word line wiring line of claim 3, wherein the second strapping layer is formed between the second conductive layer and the word line by using the first contact means as a pad of the first conductive layer. Way.