JPS56142662A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS56142662A
JPS56142662A JP4593580A JP4593580A JPS56142662A JP S56142662 A JPS56142662 A JP S56142662A JP 4593580 A JP4593580 A JP 4593580A JP 4593580 A JP4593580 A JP 4593580A JP S56142662 A JPS56142662 A JP S56142662A
Authority
JP
Japan
Prior art keywords
regions
chip
step checking
check
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4593580A
Other languages
Japanese (ja)
Other versions
JPS6212664B2 (en
Inventor
Fusao Tsubokura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4593580A priority Critical patent/JPS56142662A/en
Publication of JPS56142662A publication Critical patent/JPS56142662A/en
Publication of JPS6212664B2 publication Critical patent/JPS6212664B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To limit the area occupying the step checking element to the minimum limit by dispersing a plurality of different step checking elements in the respective chips. CONSTITUTION:Chip regions 3-1-3-4 are disposed on a semiconductor substrate 2, and each chip region has equal function element regions 4-1-4-4 and equal arranged regions 20-1-20-4. Different step checking elements 16, 17, 18, 19 are dispersed in the check regions 20-1-20-4. The check steps can be simplified by disposing the check regions at the same chip regions, and the mask can also be readily formed. Thus, the area occupying the step checking elements can be limited to the minimum limit, the degree of freedom on the layout can be increased, and the mask can be readily manufactured, and the chip can be made to small sizes.
JP4593580A 1980-04-08 1980-04-08 Manufacture of semiconductor integrated circuit Granted JPS56142662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4593580A JPS56142662A (en) 1980-04-08 1980-04-08 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4593580A JPS56142662A (en) 1980-04-08 1980-04-08 Manufacture of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS56142662A true JPS56142662A (en) 1981-11-07
JPS6212664B2 JPS6212664B2 (en) 1987-03-19

Family

ID=12733119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4593580A Granted JPS56142662A (en) 1980-04-08 1980-04-08 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS56142662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63278242A (en) * 1987-05-09 1988-11-15 Fujitsu Ltd Semiconductor device and method of testing flatness of surface thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685456U (en) * 1993-05-25 1994-12-06 新キャタピラー三菱株式会社 Fixing mechanism in rotary operation lever device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63278242A (en) * 1987-05-09 1988-11-15 Fujitsu Ltd Semiconductor device and method of testing flatness of surface thereof

Also Published As

Publication number Publication date
JPS6212664B2 (en) 1987-03-19

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