JPS62226641A - Layout of semiconductor logic integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the automatic wiring operation and to improve the extent of integration of a chip. by providing supply mains through circuit blocks seperately from a design of signal wirings. CONSTITUTION:In the first step of designing a layout, a distance (c) between prospective lines to be cut. a distance (p) between supply mains and a width (w) of a supply main region are determined. In the next step, columns of logic cells 3 are arranged such that the prospective lines to be cut 7 are included in a chip at intervals of the distance (c) and all the virtual lines drawn at intervals of the distance (c) correspond to the boundaries of the logic cells. After that, signal wirings are provided between circuit blocks 4. The circuit blocks 4 are arranged such that the lines 7 are aligned between the upper and lower adjacent blocks 4. (N) of the lines 7 are selected as lines to be practical]y cut at intervals of the distance (p), and the entire layout is cut along the cutting lines 6 through the width (w). Supply mains 2 are provided in the cut regions vertically in a single straight line. After that, supply branch lines 5 are provided between the mains 2 and the cut portions of the blocks 4.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to an automatic layout method using a computer for semiconductor logic integrated circuit devices, and in particular to a method for automatically laying out circuit blocks in a hierarchical manner. The present invention relates to a wiring method for the 'rIi source line.

(Prior art) With the increasing scale of semiconductor logic integrated circuits and the increasing variety of products in small quantities,
Technology that uses computers to design these designs is becoming increasingly important. In particular, the layout design of the arrangement of logic elements constituting a circuit and the wiring between logic elements is a field suitable for computer use.

A building block method has been used as one of the automatic layout methods for logic integrated circuits.

However, with this method, as the number of logic elements constituting the circuit board increases, the time required for placement and wiring has become extremely long.

In response, methods have been proposed in which circuit blocks are divided hierarchically and laid out (for example, Kitazawa, Adachi,
Ueda “Large-scale layout program: ALPHA-Ir
Information Processing Society of Japan Design Automation Study Group Material 19-4.198
(See 3). When circuit blocks are arranged hierarchically, it is common to lay out each circuit block using a polycell method (standard cell method) and between circuit blocks using a general cell method. By the way, the power line (
In the PolyCell method, logic cells (including ground lines (hereinafter the same shall apply)) are wired in a straight line by arranging logic cells in columns, but in the General Cell method, they must be routed between multiple circuit blocks. This generally results in bent wiring.

FIG. 4 schematically shows an example of a power supply line layout in a logic integrated circuit using conventional hierarchical circuit blocks. 11 is a semiconductor chip, on which a plurality of circuit blocks 14 are arranged. Inside each circuit block 14, a cell column 13 consisting of a plurality of logic cells is arranged in a polycell manner. When wiring between each circuit block 14, a power supply line 12 for supplying power to each circuit block 14 is simultaneously wired.

Such conventional hierarchical logic integrated circuits have the following problems. First, wiring between circuit blocks becomes extremely difficult. That is, since the power supply lines of the circuit blocks are wired together with the signal lines in the wiring area between the circuit blocks, they affect the signal wiring.

In general, power supply lines are wider than signal lines, and therefore it is necessary to perform wiring processing by mixing wiring with different widths, which makes it difficult to create an automatic wiring program. Second, the wiring area is wasted. That is, the power supply lines provided between circuit blocks of different sizes inevitably have irregular shapes, with bends formed at various locations as shown in FIG. Furthermore, since the power supply line is wide, it is necessary to use a large wiring area to bend it, which results in a reduction in the degree of integration of the entire chip.

(Point m while the invention attempts to solve the problem) As described above, in the conventional method of laying out circuit blocks hierarchically, there are difficulties in wiring the power supply lines, making wiring processing difficult, and it is difficult to sufficiently increase the degree of integration. The problem was that it was not possible.

The present invention has been made in view of the above points, and an object of the present invention is to provide a layout method for a hierarchically structured semiconductor integrated circuit device, which facilitates automatic wiring processing and makes it possible to improve the degree of chip integration. shall be.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a wiring design that excludes power supply lines in advance when wiring power supply lines that connect circuit blocks of a logic circuit that is laid out hierarchically. After doing this, make a straight cut in the circuit block layout by cutting [1] and wiring the power supply main line in a straight line in this cut area. To this end, in the present invention, the circuit blocks on the chip are cut out at least at one location. Since the power supply main line is disposed to pass through the circuit blocks, each circuit block is supplied with power by wiring a branch line from the power supply main line.

In the present invention, in order to ensure that circuit operation is not hindered even if a straight cut is made in the layout after signal wiring is designed, only the wiring intersects with the cut. Since only wiring exists in the wiring area between circuit blocks, a cut can be made at any position, but when making a cut in a circuit block, it is necessary to avoid the element area. For this reason, at the circuit block design stage, a straight cutting candidate line is set so as to be located on the boundary of a plurality of logic cells constituting the circuit block. - If it is difficult to position a straight cutting candidate line on the boundary between logic cells in each circuit block, a through cell may be added as a spacer that allows the wiring to pass through.

(Function) According to the method of the present invention, since the power main line passing through the circuit block is wired separately from the signal wiring design, it becomes easy to create an automatic wiring program. Further, since it is not necessary to arrange wide, curved power supply lines in the wiring area, the wiring area only needs to have the space necessary for arranging the signal lines, and the degree of integration of the chip can be improved.

(Example) The present invention will be explained in detail below.

FIG. 1 is a schematic diagram of a logic integrated circuit chip laid out according to an embodiment of the present invention. The semiconductor chip 1 includes
A plurality of circuit blocks 4 are arranged in a polycell layout.

That is, each circuit block 4 is constituted by a plurality of cell columns 3 in which a plurality of logic cells are arranged in columns. The circuit block 4 and the wiring area between the blocks are cut out by a cutting line 6, and the power main line 2 is wired in a straight line in this cut out area. A power supply branch line 5 is wired between this power supply main line 2 and the cut end of each circuit block 4.

In the cell row 3, a plurality of logic cells are arranged adjacent to each other, and the power supply terminals come out on the left and right sides of each logic cell, so by wiring the power supply branch line 5 in this way, The power terminals of both will be commonly connected.

A specific procedure for realizing the power supply wiring as shown in FIG. 1 will be described below with reference to FIGS. 2 and 3. Second
The figure shows a state in which circuit blocks are placed with cutting candidate lines inserted, and FIG. 3 shows a flowchart. First, at the beginning of layout design, the cutting candidate line interval C2, the power trunk interval p, and the width W of the power trunk area are set. The power supply main line interval p is determined so that a sufficient number of power supply main lines can be inserted to supply power to the circuit, and the power supply main line area width W is determined so that a power supply main line with a width sufficient to supply power to the circuit can be inserted. do. The cutting candidate line interval C is set to be p - nc (n is an integer). Next, the circuit block is designed using the polycell method. At this time, the logic cells are arranged so that cutting candidate lines are inserted at every interval C on the chip, and all straight lines virtually drawn at every interval C become boundaries of logic cells. If all the logic cells have the same size, the cutting candidate line can be set on the logic cell boundary without special consideration. FIG. 2 shows a state in which three circuit blocks 4 each consisting of a plurality of cell columns 3 are arranged, with the logic cell arrangement being devised so that the cutting candidate line 7 rides on the boundary of each logic cell. It may not be possible to make the cutting candidate line 7 ride on the logic cell boundary simply by devising the arrangement of the logic cells, but in that case, through cells may be inserted as appropriate. Since the through cell can also be used for passing signal wiring, it does not necessarily create an invalid area. However, it is necessary to take into consideration that when the cutting candidate line interval C is small, a large number of through cells may be required, and the area efficiency will decrease. Further, it is an essential condition that the cutting candidate line interval C is set to be equal to or larger than the maximum cell width.

Next, signal wiring processing between each circuit block 4 is performed. As this wiring method, conventionally known channel wiring methods, line segment search methods, maze methods, etc. can be used. At this time, it should be noted that the circuit blocks 4 are arranged so that the cutting candidate lines 7 are aligned between vertically adjacent circuit blocks. That is, the wiring area 8 where horizontal wiring is performed
There is no restriction on the width of the wiring area 9, which can be selected regardless of the position of the cutting candidate line 7, but there is a restriction on the width of the wiring area 9 in which the vertical signal wiring is provided. Generally, the width of the wiring area is determined by the number of wires passing through it, but in this embodiment, the width of the wiring area 9 must be adjusted not in units of wiring pitch but in units of cutting candidate line interval C. Therefore, it is necessary to take into account that if the cutting candidate line interval C is too large, an unnecessarily large wiring area width will be taken, and the wiring efficiency will be reduced.

Next, from among the plurality of cutting candidate lines 7, zero cutting lines are selected with an interval p, and the entire layout is cut along the cutting lines 6 by a width W as shown in FIG. Then, the power main line 2 is laid vertically and in a straight line in the incised area. The power main line 2 may be connected to the power line around the chip. Thereafter, a power supply branch line 5 is wired between the power supply main line 2 and the cut end of each circuit block.

Finally, in order to repair the signal wires that were cut due to cutting out the layout, horizontal signal wires are laid in the necessary parts of the cut out area.

As described above, according to this embodiment, when configuring a logic integrated circuit by laying out circuit blocks hierarchically, the power supply wiring between the circuit blocks is processed separately from the signal wiring, so that the automatic wiring program Creation becomes easier, and wiring processing between blocks becomes much easier. In addition, since the power supply lines between each circuit block are formed in a straight line without any bends, the wiring area is not wasted.
It disappears. Although the number of power supply lines is small, considering that they are much wider than the signal lines and that there are no bends in the power supply lines, this embodiment has a large effect in reducing the chip area.

Note that the present invention is not limited to the above-mentioned embodiments,
Various modifications can be made without departing from the spirit of the invention.

[Effects of the Invention] As described above, according to the present invention, automatic wiring processing of large-scale logic integrated circuits in which circuit blocks are laid out in a hierarchical manner becomes easy, and it is possible to improve the degree of integration of integrated circuit chips. can.

[Brief Description of the Drawings] Fig. 1 is a diagram showing the structure of an integrated circuit chip according to an embodiment of the present invention, Fig. 2 is a diagram showing an intermediate stage of its design, and Fig. 3 is a flow diagram showing its design procedure. , FIG. 4 is a diagram showing the structure of a conventional integrated circuit chip. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Power main line, 3... Cell row, 4... Circuit block, 5... Power supply branch line, 6...
... Cutting line, 7... Cutting candidate line, 8.9... Wiring area. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a method of dividing a semiconductor logic integrated circuit into a plurality of circuit blocks and automatically laying them out hierarchically, a plurality of circuit blocks each consisting of a plurality of logic cells,
A process of designing circuit blocks so that a vertical cutting candidate line that is crossed by the power supply line is included in each circuit block, and designing the circuit blocks so that the cutting candidate lines of adjacent circuit blocks are aligned in a straight line between the plurality of designed circuit blocks. a step of wiring the signal lines while adjusting the arrangement; a step of cutting each of the circuit blocks and the inter-block wiring area at the cutting candidate line position; and a step of wiring a power main line in a straight line in the cut area. A layout method for a semiconductor logic integrated circuit device, comprising the step of wiring a power supply branch line between the power supply main line and the power supply line in each circuit block. (2) Each of the circuit blocks is constructed by arranging logic cells according to a standard cell method.
A layout method for a semiconductor logic integrated circuit device as described in .