JPS63161638A - Power supply wiring method of semiconductor integrated circuit - Google Patents

Power supply wiring method of semiconductor integrated circuit

Info

Publication number
JPS63161638A
JPS63161638A JP30794786A JP30794786A JPS63161638A JP S63161638 A JPS63161638 A JP S63161638A JP 30794786 A JP30794786 A JP 30794786A JP 30794786 A JP30794786 A JP 30794786A JP S63161638 A JPS63161638 A JP S63161638A
Authority
JP
Japan
Prior art keywords
cell
power
power supply
cells
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30794786A
Other languages
Japanese (ja)
Inventor
Masahiko Kawamura
河村 匡彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP30794786A priority Critical patent/JPS63161638A/en
Publication of JPS63161638A publication Critical patent/JPS63161638A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To constitute a semiconductor integrated circuit by connecting a plurality of cell lines to power cells by a minimum cell area by conforming width by using the cells for power supply, in which the positions of equipotential power terminals in the horizontal direction of the upper and lower sides of the cells for power supply inserted into cell lines differ, and arranging power lines. CONSTITUTION:Power lines 4 in the vertical direction displaying power wirings in the horizontal direction and power lines 6 in the horizontal direction are connected by contact holes 5, and the power lines 6 in the horizontal direction is connected to a power line for a standard cell adjacent to a power cell. Since horizontal pitches in the power cell can be changed, this method has a merit that a dummy cell for conforming width as seen in conventional methods may not be employed. Power cells having the different angles of the cranks of wiring patterns in the cell are registered previously to a plurality of cell libraries actually in the power cells, and it is preferable that the optimum power cell is selected in response to the condition of the arrangement of other standard cell.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は標準セル方式のセミカスタム集積回路に係り、
特に各セル行への電源供給を効率よく行うことのできる
セミカスタムの半導体集積回路電源配線方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a standard cell type semi-custom integrated circuit,
In particular, the present invention relates to a semi-custom semiconductor integrated circuit power wiring method that can efficiently supply power to each cell row.

(従来の技術) 半導体集積回路の構成法として標準セル方式が多用され
ている。これはあらかじめ設計された能動素子等を含む
標準セルを、複数の行(または列)状に配置し、各セル
相互間の結線を自動配線プログラム等により行うもので
あり1人手設計による設計手法に比べ、開発に要する期
間の短縮化が図れることを特徴とする。このような標準
セル方式の集積回路における電源の供給方法の一つとし
て。
(Prior Art) The standard cell method is often used as a construction method for semiconductor integrated circuits. In this method, standard cells containing pre-designed active elements, etc. are arranged in multiple rows (or columns), and connections between each cell are made using an automatic wiring program, etc., making it a one-man design method. In comparison, it is characterized by shortening the period required for development. As one of the power supply methods for such standard cell type integrated circuits.

第3図に示すように各セル行1の中央付込に、電源配線
4の水平方向の座標がすべて等しくなるように、第4図
に示すような電源供給用の特殊なセル(電源セルと呼ぶ
)3を挿入し、第3図に示すように、電源配線4は信号
配線にて使用する金属配線よりも太めの配線(通常2層
目のM配線=2Atと略す)を用いて、垂直方向に2本
平行して貫通させる。当該電源セル3の左右に配置され
た標準セル内には上下に水平方向にIMにて電源用の配
線6がすでに施されており、第4図に示すように電源セ
ル3内ではコンタクトホール5により2A−tを他のセ
ルと同じ位置の1Mに接続しており。
As shown in FIG. 3, a special cell for power supply (power supply cell and power supply cell) as shown in FIG. As shown in Fig. 3, the power supply wiring 4 is vertically connected by using a wiring that is thicker than the metal wiring used for the signal wiring (usually abbreviated as second layer M wiring = 2At). Pass two lines parallel to each other. In the standard cells arranged on the left and right sides of the power supply cell 3, power supply wiring 6 is already provided by IM in the vertical and horizontal directions, and as shown in FIG. 2A-t is connected to 1M at the same location as other cells.

垂直方向に貫かれた2Atの終端を図示しない電源用の
パッドに接続することにより、すべての標準セルに電源
が供給されることになる。なお、7はダミーセルである
。この方法の問題点は、電源セルの種類が第4図に示す
ような、上下辺の等電位端子の水平方向の座標が等しい
ものに限られ、第3図のように太い2Mで電源線4を垂
直方向に直線的に通すためには、当該電源セルの各行へ
の挿入場所が、自ずと水平方向の座標が等しくなるよう
な位置でなければならない。しかしながら、標準セルで
実現する回路は多種多様であり、いつも直線的に電源セ
ルを挿入できるとは限らず、そうでない場合は適宜電源
セル位置調整のため、セル幅合わせ用のダミーセルを追
加せねばならない。
Power is supplied to all the standard cells by connecting the end of the 2At that is passed through in the vertical direction to a power supply pad (not shown). Note that 7 is a dummy cell. The problem with this method is that the type of power supply cell is limited to those in which the horizontal coordinates of the equipotential terminals on the upper and lower sides are equal, as shown in Figure 4, and the power supply line is In order to pass the power cell in a straight line in the vertical direction, the insertion position of the power supply cell in each row must be such that the horizontal coordinates are naturally equal. However, there are a wide variety of circuits realized using standard cells, and it is not always possible to insert power cells in a straight line. If this is not the case, it is necessary to add dummy cells to adjust the cell width in order to adjust the position of the power cells. No.

ダミーセルの追加は、チップ面積の増大につながるばか
りか1回路内のトータルのセル数の増加をもたらし、自
動配置/配線プログラムの負担となり、設計効率を低下
させる。その上、このセル幅合わせの調整は、セル行が
増えるほど、また一つの行内に幅広のセルが多いほど、
困難さを増し。
Adding dummy cells not only increases the chip area but also increases the total number of cells in one circuit, which places a burden on automatic placement/routing programs and reduces design efficiency. Furthermore, the more cell rows there are, or the more wide cells there are in one row, the more the cell width adjustment becomes more difficult.
Increased difficulty.

多数のダミーセルを要する。A large number of dummy cells are required.

(発明が解決しようとする問題点) 本発明は、このような問題点に鑑みてなされたもので、
電源セル挿入のために行う幅合わせセルの追加を減らす
ことができ、電源線の配線を効率よく行えるようにした
半導体集積回路の配線方法を提供することを目的とする
(Problems to be Solved by the Invention) The present invention has been made in view of these problems.
It is an object of the present invention to provide a wiring method for a semiconductor integrated circuit that can reduce the addition of width matching cells for inserting power supply cells and can efficiently route power supply lines.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 本発明は、この目的を達成するため、標準セル方式のセ
ミカスタム集積回路において、第2図に例示するように
セル内部で垂直方向の配線パターンをクランクさせ1等
電位端子の上下辺でのX座標が異なるような電源セルも
用意し、このセルと従来のような電源セルを適宜各セル
行内に挿入し。
(Means for Solving the Problems) In order to achieve this object, the present invention, in a standard cell type semi-custom integrated circuit, cranks a vertical wiring pattern inside the cell as illustrated in FIG. A power supply cell with different X coordinates on the upper and lower sides of the first equipotential terminal is also prepared, and this cell and a conventional power supply cell are inserted into each cell row as appropriate.

これら電源セル挿入のために要する幅合わせセルの個数
を可能な限り減らしめることを特徴とする。
The present invention is characterized in that the number of width adjustment cells required for inserting these power supply cells can be reduced as much as possible.

(作用) 電源供給用特殊セル内の配線パターンを、第2図に示す
ごとくクランクさせることにより、従来。
(Function) By cranking the wiring pattern in the special cell for power supply as shown in FIG.

幅合わせセルにより調整していた第4図のような電源セ
ルの水平方向の座標を、調整なしかまたは幅合わせ用の
ダミーセルの個数を減らすことが可能となる。このこと
は、第2図に示すように、電源セルをクランクの角度を
変えて、何種類か用意することにより、より効果が出て
くる。
The horizontal coordinates of the power supply cells as shown in FIG. 4, which have been adjusted by width adjustment cells, can be adjusted without adjustment or by reducing the number of dummy cells for width adjustment. This becomes more effective by preparing several types of power cells with different crank angles, as shown in FIG.

(実施例) 以下1図面を参照して本発明の詳細な説明する。(Example) The present invention will be described in detail below with reference to one drawing.

第1図は1本発明に係る標準セル方式集積回路における
電源供給用セルの一実施例である。図中。
FIG. 1 shows an embodiment of a power supply cell in a standard cell type integrated circuit according to the present invention. In the figure.

lが標準セルからなるセル行であり、符号2で示す部分
が本発明に係る新しい方式の電源セルである。第2図は
、第1図における本発明に係る電源セル2の詳細な図で
あり1図中4が2Mを利用した垂直方向の電源配線、6
がIA/、による水平方向の電源配線を示す垂直方向の
電源線4と水平方向の電源線6はコンタクトホール5に
よって接続され、水平方向の電源線6は当該電源セルに
隣接する標準セルの電源線と接続される。
1 is a cell row consisting of standard cells, and a portion designated by 2 is a new type of power supply cell according to the present invention. FIG. 2 is a detailed diagram of the power supply cell 2 according to the present invention in FIG.
A vertical power line 4 and a horizontal power line 6 are connected through a contact hole 5, and the horizontal power line 6 is connected to the power source of a standard cell adjacent to the power cell in question. connected to the line.

本発明に係る第2図に示すような電源セルを用いた第1
図に示す電源配線方法では、電源セル内で水平方向ピッ
チの変更が可能となるため、従来方法のように幅合わせ
のためのダミーセルを用いなくてよいメリットがある。
A first method using a power supply cell as shown in FIG. 2 according to the present invention.
The power supply wiring method shown in the figure has the advantage that it is not necessary to use dummy cells for width adjustment as in the conventional method, since the horizontal pitch can be changed within the power supply cells.

これらの本発明に係る電源セルは実際上は、セル内配線
パターンのクランクの角度の異なるものを複数個セルラ
イブラリに登録しておき、他の標準セルの配置具合に応
じて最適なものを選択することが望ましい。
In practice, for these power cells according to the present invention, a plurality of cell wiring patterns with different crank angles are registered in a cell library, and the optimal one is selected according to the arrangement of other standard cells. It is desirable to do so.

その他、本発明は要旨を逸脱しない範囲で種々変形して
実施することが可能である。
In addition, the present invention can be implemented with various modifications without departing from the scope.

第5〜7図を用いて、本発明の配線方法と従来法とを対
比して説明する。第5図は電源セル挿入以前の標準セル
の配置を示す図であり、1行目にハセル幅2ユニットの
セル4個が並び、2行目には同5ユニツトと3ユニツト
のセルが並ぶ。
The wiring method of the present invention and the conventional method will be compared and explained using FIGS. 5 to 7. FIG. 5 is a diagram showing the arrangement of standard cells before the power supply cells are inserted. In the first row, four cells each having a width of 2 units are lined up, and in the second row, cells having a width of 5 units and 3 units are lined up.

従来の方法で、第5図に示すセル行にセル幅2ユニツト
の電源セルを挿入する場合は、第6図に示すように、1
行目の左端、2行目の右端にそれぞれ幅合わせ用のダミ
ーセル(セル幅lユニットとする)を追加せねば、垂直
方向に2/L/、の電源線を配線できず、トータルのセ
ル幅は1.2行目とも11ユニツトとなる。
When inserting a power supply cell with a cell width of 2 units into the cell row shown in FIG. 5 using the conventional method, as shown in FIG.
Unless we add dummy cells for width adjustment (the cell width is l units) to the left end of the row and the right end of the second row, we cannot route the power supply line of 2/L/ in the vertical direction, and the total cell width Both the 1st and 2nd lines have 11 units.

一方、第7図に示すように、本発明に従うセル幅2ユニ
ツトの電源セルを挿入すれば1幅合わせ用ダミーセルが
不要になり、トータルのセル幅は1.2行目とも10ユ
ニツトで済む。
On the other hand, as shown in FIG. 7, if a power supply cell with a cell width of 2 units according to the present invention is inserted, a dummy cell for 1 width adjustment becomes unnecessary, and the total cell width can be reduced to 10 units in both the 1st and 2nd rows.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ダミーセルを用いることなく最少板の
セル面積で、複数のセル行を電源セルに結線して半導体
集積回路を構成できる。
According to the present invention, a semiconductor integrated circuit can be constructed by connecting a plurality of cell rows to power supply cells with a minimum cell area of a board without using dummy cells.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る一実施例の全体図、第2図は本発
明に係る電源供給用セルの詳細図、第3図は従来方式の
電源供給用セルの使用法による説明図、第4図は第3図
で用いられている電源供給用セルの詳細図、第5図は電
源セル挿入以前のセル配置図、第6図は舅5図の回路に
従来方式の電源セルを挿入した図、8g7図は第5図の
回路に本発明に従う電源セルを挿入した図である。 I・・・標準セル行、2・・・本発明に従う電源セル、
3・・・従来方式の電源セル、4・−・垂直方向の電源
配線、5・・・コンタクトホール、6・・・水平方向の
電源配線、7・・・セル行幅調整用ダミーセル。 代理人 弁理士 則 近 憲 佑 同    竹 花 喜久男 \J へ  〈 頓 ’、J)/?l−J
FIG. 1 is an overall view of an embodiment according to the present invention, FIG. 2 is a detailed view of a power supply cell according to the present invention, FIG. 3 is an explanatory diagram of how to use a conventional power supply cell, and FIG. Figure 4 is a detailed diagram of the power supply cell used in Figure 3, Figure 5 is a cell layout diagram before power cell insertion, and Figure 6 is a diagram of the conventional power supply cell inserted into the circuit shown in Figure 5. Figure 8g7 is a diagram in which a power supply cell according to the present invention is inserted into the circuit of Figure 5. I... Standard cell row, 2... Power supply cell according to the present invention,
3... Conventional power supply cell, 4... Vertical power supply wiring, 5... Contact hole, 6... Horizontal power supply wiring, 7... Dummy cell for cell row width adjustment. Agent Patent Attorney Nori Ken Yudo Takehana Kikuo\J To〈ton', J)/? l-J

Claims (1)

【特許請求の範囲】[Claims] 半導体基板に、能動素子を備えたセル行を複数個並べ、
その間に配線を施して所望の回路を実現する標準セル方
式の半導体集積回路において、当該セル行に対して垂直
方向に電源線を配設するために、セル行内に挿入する電
源供給用セルの上下辺の水平方向の等電位電源端子位置
がそれぞれ異なるような電源供給用セルを用いて幅合せ
を行なって前記電源供給用セルの電源線を配線すること
を特徴とする半導体集積回路の電源配線方法。
Multiple cell rows equipped with active elements are arranged on a semiconductor substrate,
In standard cell type semiconductor integrated circuits in which a desired circuit is realized by wiring between them, power supply lines are placed above and below the power supply cells inserted into the cell row in order to arrange the power supply lines perpendicularly to the cell row. A power supply wiring method for a semiconductor integrated circuit, characterized in that the power supply lines of the power supply cells are wired by aligning the widths using power supply cells whose sides have different equipotential power supply terminal positions in the horizontal direction. .
JP30794786A 1986-12-25 1986-12-25 Power supply wiring method of semiconductor integrated circuit Pending JPS63161638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30794786A JPS63161638A (en) 1986-12-25 1986-12-25 Power supply wiring method of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30794786A JPS63161638A (en) 1986-12-25 1986-12-25 Power supply wiring method of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS63161638A true JPS63161638A (en) 1988-07-05

Family

ID=17975086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30794786A Pending JPS63161638A (en) 1986-12-25 1986-12-25 Power supply wiring method of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS63161638A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02185056A (en) * 1989-01-12 1990-07-19 Fujitsu Ltd Automatic arranging method of cell of semiconductor integrated circuit
JPH0563084A (en) * 1991-08-30 1993-03-12 Nec Corp Designing method for layout of semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02185056A (en) * 1989-01-12 1990-07-19 Fujitsu Ltd Automatic arranging method of cell of semiconductor integrated circuit
JPH0563084A (en) * 1991-08-30 1993-03-12 Nec Corp Designing method for layout of semiconductor integrated circuit

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