JPH0563084A - Designing method for layout of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress an increase in an area, an increase in the number of steps of forming a cell library and complexity of management by automatically generating the cell library for wiring a bus in a layout system and art working it at the time of outputting. CONSTITUTION:When cell columns are generated, inserting positions of power source.ground bus wirings are then designated and thicknesses of the bus wirings and intervals between the bus wirings and between the bus wirings and cells are given, a predetermined cell library is automatically generated on a layout data base. Here, the positions of power source.ground terminals 104 for the bus wirings are generated on a rectangular intersection rectangle for coupling an equipotential terminals of a bus wiring width 103, a power source.ground terminal 103 for the cell columns and a power source ground bus wiring position. And, a short-circuit contact of the bus wirings and the supply wiring is automatically generated by art working outputting thereby to supply power source.ground potentials to the bus wirings and right and left cell columns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for a semiconductor integrated circuit, and more particularly to a layout design for a standard cell-based integrated circuit.

[0002]

2. Description of the Related Art Conventionally, when a standard cell-based layout is automatically performed, a power source and a ground terminal of each standard cell are brought into close contact with each other and energized to form a cell row. At this time, when the integrated circuit becomes large in size, the cells near the center of the cell row are
It becomes difficult to supply the ground potential. In addition, an increase in cell column length causes an increase in wiring length, which makes it difficult to guarantee timing in clock signal supply. In order to solve this problem, there is a layout method in which a power supply / ground bus wiring for supplying a potential and a clock bus wiring for supplying a clock signal are passed through a cell row. The following two methods are typical as conventional methods for automatically realizing this with a computer.

A case where the power supply / ground bus wiring is passed through the cell array will be described below as an example. First, the first method is to divide a cell row in the middle and use it as a channel and pass a bus wiring through the channel by a wiring program. The second method is to prepare a cell for bus wiring in a cell library in advance and insert this cell into a cell row by a placement program.
The wiring program connects the bus wiring to the cell. Specifically, the function of this cell is to short-circuit the power / ground bus wiring and the power / ground supply terminal of each cell column. As a structure, it has only a bus line, a line for supplying a power supply / ground potential to a cell row, and a contact for short-circuiting these two types of power supply / ground lines. FIG. 6 is a model diagram of a result obtained by using the first method, FIG. 7 is an example of cells created as a library in advance by the second method,
FIG. 8 shows a model diagram of a result obtained by using the second method.

[0004]

In the above-mentioned conventional technique, when the first method is adopted, normal channel wiring is carried out by the channels into which the cell columns are divided. As a result, the bus lines are bent, the left and right cell columns are displaced, and the signal lines are assigned to the divided channels, which often causes the divided channels to swell and increase the chip area (115 in FIG. 6). Further, when the second method is adopted, the designer needs to prepare a cell library for power / ground and clock bus wiring in advance. Since the shape, wiring width, etc. of this cell vary greatly depending on the characteristics of the integrated circuit, it is almost always a dedicated library unique to each integrated circuit. Therefore, the number of man-hours required for creating the library is increased more than necessary and the management is complicated.

[0005]

According to the layout design method of a semiconductor integrated circuit of the present invention, in a standard cell-based layout, when a power supply / ground bus wiring and a clock bus wiring are generated in a cell row, the chip area is reduced. In order not to increase the number and to eliminate the need to prepare the bus wiring cell library in advance, the designer inputs the minimum information to automatically generate the power / ground bus wiring cells suitable for the design integrated circuit in the layout system. It has the function of generating and arranging automatically.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of the design method of the present invention. First, after generating a cell row, the designer specifies the insertion position of the power / ground bus wiring. At this time, the thickness of the power / ground bus wiring and the bus wiring spacing line / the spacing between the bus wiring and the cell are also given at the same time. The present invention automatically generates cells as shown in FIG. 2 as a library on the layout database based on this information. This cell has two types of power supply and ground terminals. The power / ground terminal 103 is connected to the left and right standard cells on the same cell row, and supplies a potential to the left and right cell rows divided by this cell. 104 power supply
The ground terminal is for connecting to the power supply / ground bus wiring, and is for generating a bus wiring by a wiring program. The position of the terminal 104 occurs on a rectangular intersection rectangle connecting the equipotential terminals of the power ground bus wiring position obtained from the power / bus wiring width and each interval given by the designer 102. At this time, the terminals connected to the downward bus lines are generated above the intersection rectangle, and the terminals connected to the upward bus lines are generated below the intersection rectangle. By generating the terminal at such a position, redundant wiring in this cell can be prevented. This cell has no artwork yet at this stage. Next, the cell is placed at the position designated by the designer. Next, with automatic wiring, 10
Connect the wiring to the power / ground terminal of 4. As a result,
The substance of bus wiring can be created. FIG. 3 is a diagram after this processing. Finally, in the artwork output process, the power supply / ground potential is supplied to the bus line and the left and right cell columns by automatically generating the potential supply wiring to the cell column and the contact that short-circuits the bus wiring and the cell supply wiring. FIG. 4 shows an artwork diagram of a power / ground bus cell generated in the present invention.

Next, a second embodiment of the present invention will be described. According to the present embodiment, the clock bus can be realized by reducing the chip area and man-hours. The flow is exactly the same as in Example 1. The processing contents are the same until the automatic wiring. Power supply·
The difference from the ground bus is that the clock does not short-circuit with the power supply / ground wiring like the normal signal line, and therefore does not output the contact for short-circuiting the cell column supply power / ground wiring and the bus wiring at the time of output. FIG. 5 shows the vicinity of the clock bus wiring after layout using the clock bus library created in this embodiment. Each phase will be described with reference to this figure. First, the bus position / width /
As a result of specifying the interval, a library having 111 and 112 terminals is generated. Next, this library is placed and automatic wiring is performed according to the netlist. As a result, 1
The bus wiring 113 is connected to the clock bus terminal 11. Finally, in the output process, the power supply / ground wiring 114 connecting the power supply terminals to the cell columns is generated.

[0008]

As described above, according to the present invention, in the standard cell-based layout design, when the power / ground bus wiring and the clock bus wiring are generated, the bus wiring cell library is automatically generated inside the layout system. Since the artwork is created at the time of output, the problem of the conventional method is that the area is increased and the number of library creation steps is increased.
The complexity of management can be suppressed. Further, since the layout system is completely closed by the internal processing, the layout system external environment / operation form is completely the same as the conventional one.

[Brief description of drawings]

FIG. 1 is a flowchart of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention.

FIG. 3 is a diagram for explaining an example of the present invention.

FIG. 4 is a diagram for explaining an example of the present invention.

FIG. 5 is a diagram for explaining a second embodiment of the present invention.

FIG. 6 is a diagram for explaining a problem to be solved by the present invention.

FIG. 7 is a diagram for explaining a problem to be solved by the present invention.

FIG. 8 is a diagram for explaining a problem to be solved by the present invention.

[Explanation of symbols]

101 Spacing with Bus Wiring 102 Bus Wiring Width 103 Power Supply / Ground Terminal for Cell Row Supply 104 Power Supply / Ground Terminal for Bus Wiring 105 Power Wiring from Above 106 Power Wiring from Below 107 Ground Bus Wiring from Above 108 Ground bus wiring from below 109 Wiring for power supply / ground supply to cell row 110 Short contact between bus wiring and supply wiring 111 Clock bus terminal 112 Power supply / ground terminal 113 Clock bus wiring 114 Power supply / ground wiring 115 Power supply・ Channel for ground bus wiring 116 Power supply / ground bus wiring 117 Power supply / ground bus wiring terminal 118 Power supply / ground supply terminal to cell column 119 Short contact between bus wiring and supply wiring 120 Power supply / ground bus cell 121 Power supply Ground bus wiring

Claims (1)

[Claims] 1. In a computer-based automatic design of a standard cell-based integrated circuit, a bus wiring is provided at an arbitrary position of a chip, a branch line is extended from the bus wiring, and a wiring is supplied to each cell or cell column. A layout design method for a semiconductor integrated circuit, which is realized by automatically creating and arranging a cell library for power / ground bus wiring and clock bus wiring suitable for an integrated circuit in a layout system.