JPH0645474A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a printed circuit board, on which a semiconductor device is mounted, from having partially dense interconnection. CONSTITUTION:Many lead pins 2 protruding vertically from the back of a package 1 are so arranged that the pitches between the adjoining pins become wider toward the periphery of the package. Therefore, a printed circuit board on which this semiconductor device is mounted has wider pitches for interconnection to the lead pins 2, which correspond to the pin pitches at outer portions. Thus, wires which connect to the inner pins can be laid between the outer pins with some space, thus preventing the reliability of the device from decreasing due to dense interconnection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pin arrangement of a pin grid array package semiconductor device.

[0002]

2. Description of the Related Art As shown in the back view of FIG. 2, a lead pin array of a conventional pin grid array (PGA) package semiconductor device has a large number of lead pins 2 vertically drawn from the back surface of a package 1 in the center. Except for the blank areas, they are planted at equal pin intervals in a wide annular area along the four sides of the square package outline.

[0003]

As described above, since all the pin intervals are the same, the wiring density of the wiring board on which this package is mounted is such that the wiring connected to the pins on the central side of the package is the same as the peripheral area. Since it passes between the wirings connected to the pins, it is overcrowded in the peripheral portion. Therefore, there is a problem in that the reliability of the peripheral wiring becomes worse than that of the central wiring. Therefore, in order to avoid this drawback, the mounting board is multi-layered, and the wiring connecting to the pin on the center side is drawn to the lower wiring layer. However, there is a drawback that the cost increases when the substrate is multi-layered.

[0004]

In order to solve the above problems, the present invention provides a PGA package in which a large number of lead pins are implanted in a wide annular region along the periphery of the back surface of the package except for the central portion. The pin spacing is gradually increased from the side toward the periphery.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a rear view of a package according to an embodiment of the present invention. In the figure, a large number of lead pins 2 are planted in quadruple rows in a wide annular region along the outer periphery of the back surface of the square package 1. Exceptionally, there is one lead pin 3 at one corner of the central square blank, which is an index pin that serves as an index for defining the package direction. As for many other pins, the pin spacing d in the row increases from the center side to the outer side of the periphery.
1, and the column-to-column spacing d2 is gradually increased.

[0006]

As described above, according to the present invention, since the pin arrangement on the back surface of the package is gradually widened from the center of the inner side to the periphery of the outer side, adjacent pin intervals are gradually widened. Since the wiring connecting to the lead pins of the package on the board has a wide pin spacing in the portion corresponding to the periphery of the package, many wirings connecting to the pins inside from the periphery also maintain sufficient spacing between the wide pins. Therefore, there is an effect that it is possible to prevent a decrease in reliability due to an excessively close spacing between wirings connected to pins on the periphery of the mounted semiconductor device on the wiring board.

[Brief description of drawings]

FIG. 1 is a back view of an embodiment package of the present invention.

FIG. 2 is a back view of a conventional PGA package semiconductor device.

[Explanation of symbols]

 1 Package 2 Lead pin 3 Index pin

Claims (1)

[Claims] 1. A semiconductor device of a pin grid array package, wherein a plurality of lead pins which are vertically pulled out from the back surface of the package have a pin interval which is gradually widened from the center side toward the periphery. apparatus.